Merge branch 'master' into 14a_rework3
[proxmark3-svn] / armsrc / iso14443a.c
1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12
13 #include "iso14443a.h"
14
15 #include "proxmark3.h"
16 #include "apps.h"
17 #include "util.h"
18 #include "string.h"
19 #include "cmd.h"
20 #include "iso14443crc.h"
21 #include "crapto1/crapto1.h"
22 #include "mifareutil.h"
23 #include "mifaresniff.h"
24 #include "BigBuf.h"
25 #include "protocols.h"
26 #include "parity.h"
27
28 typedef struct {
29 enum {
30 DEMOD_UNSYNCD,
31 // DEMOD_HALF_SYNCD,
32 // DEMOD_MOD_FIRST_HALF,
33 // DEMOD_NOMOD_FIRST_HALF,
34 DEMOD_MANCHESTER_DATA
35 } state;
36 uint16_t twoBits;
37 uint16_t highCnt;
38 uint16_t bitCount;
39 uint16_t collisionPos;
40 uint16_t syncBit;
41 uint8_t parityBits;
42 uint8_t parityLen;
43 uint16_t shiftReg;
44 uint16_t samples;
45 uint16_t len;
46 uint32_t startTime, endTime;
47 uint8_t *output;
48 uint8_t *parity;
49 } tDemod;
50
51 typedef enum {
52 MOD_NOMOD = 0,
53 MOD_SECOND_HALF,
54 MOD_FIRST_HALF,
55 MOD_BOTH_HALVES
56 } Modulation_t;
57
58 typedef struct {
59 enum {
60 STATE_UNSYNCD,
61 STATE_START_OF_COMMUNICATION,
62 STATE_MILLER_X,
63 STATE_MILLER_Y,
64 STATE_MILLER_Z,
65 // DROP_NONE,
66 // DROP_FIRST_HALF,
67 } state;
68 uint16_t shiftReg;
69 int16_t bitCount;
70 uint16_t len;
71 uint16_t byteCntMax;
72 uint16_t posCnt;
73 uint16_t syncBit;
74 uint8_t parityBits;
75 uint8_t parityLen;
76 uint32_t fourBits;
77 uint32_t startTime, endTime;
78 uint8_t *output;
79 uint8_t *parity;
80 } tUart;
81
82 static uint32_t iso14a_timeout;
83 int rsamples = 0;
84 uint8_t trigger = 0;
85 // the block number for the ISO14443-4 PCB
86 static uint8_t iso14_pcb_blocknum = 0;
87
88 //
89 // ISO14443 timing:
90 //
91 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
92 #define REQUEST_GUARD_TIME (7000/16 + 1)
93 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
94 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
95 // bool LastCommandWasRequest = false;
96
97 //
98 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
99 //
100 // When the PM acts as reader and is receiving tag data, it takes
101 // 3 ticks delay in the AD converter
102 // 16 ticks until the modulation detector completes and sets curbit
103 // 8 ticks until bit_to_arm is assigned from curbit
104 // 8*16 ticks for the transfer from FPGA to ARM
105 // 4*16 ticks until we measure the time
106 // - 8*16 ticks because we measure the time of the previous transfer
107 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
108
109 // When the PM acts as a reader and is sending, it takes
110 // 4*16 ticks until we can write data to the sending hold register
111 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
112 // 8 ticks until the first transfer starts
113 // 8 ticks later the FPGA samples the data
114 // 1 tick to assign mod_sig_coil
115 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
116
117 // When the PM acts as tag and is receiving it takes
118 // 2 ticks delay in the RF part (for the first falling edge),
119 // 3 ticks for the A/D conversion,
120 // 8 ticks on average until the start of the SSC transfer,
121 // 8 ticks until the SSC samples the first data
122 // 7*16 ticks to complete the transfer from FPGA to ARM
123 // 8 ticks until the next ssp_clk rising edge
124 // 4*16 ticks until we measure the time
125 // - 8*16 ticks because we measure the time of the previous transfer
126 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
127
128 // The FPGA will report its internal sending delay in
129 uint16_t FpgaSendQueueDelay;
130 // the 5 first bits are the number of bits buffered in mod_sig_buf
131 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
132 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
133
134 // When the PM acts as tag and is sending, it takes
135 // 4*16 + 8 ticks until we can write data to the sending hold register
136 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
137 // 8 ticks later the FPGA samples the first data
138 // + 16 ticks until assigned to mod_sig
139 // + 1 tick to assign mod_sig_coil
140 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
141 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8 + 8*16 + 8 + 16 + 1 + DELAY_FPGA_QUEUE)
142
143 // When the PM acts as sniffer and is receiving tag data, it takes
144 // 3 ticks A/D conversion
145 // 14 ticks to complete the modulation detection
146 // 8 ticks (on average) until the result is stored in to_arm
147 // + the delays in transferring data - which is the same for
148 // sniffing reader and tag data and therefore not relevant
149 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
150
151 // When the PM acts as sniffer and is receiving reader data, it takes
152 // 2 ticks delay in analogue RF receiver (for the falling edge of the
153 // start bit, which marks the start of the communication)
154 // 3 ticks A/D conversion
155 // 8 ticks on average until the data is stored in to_arm.
156 // + the delays in transferring data - which is the same for
157 // sniffing reader and tag data and therefore not relevant
158 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
159
160 //variables used for timing purposes:
161 //these are in ssp_clk cycles:
162 static uint32_t NextTransferTime;
163 static uint32_t LastTimeProxToAirStart;
164 static uint32_t LastProxToAirDuration;
165
166
167
168 // CARD TO READER - manchester
169 // Sequence D: 11110000 modulation with subcarrier during first half
170 // Sequence E: 00001111 modulation with subcarrier during second half
171 // Sequence F: 00000000 no modulation with subcarrier
172 // READER TO CARD - miller
173 // Sequence X: 00001100 drop after half a period
174 // Sequence Y: 00000000 no drop
175 // Sequence Z: 11000000 drop at start
176 #define SEC_D 0xf0
177 #define SEC_E 0x0f
178 #define SEC_F 0x00
179 #define SEC_X 0x0c
180 #define SEC_Y 0x00
181 #define SEC_Z 0xc0
182
183 void iso14a_set_trigger(bool enable) {
184 trigger = enable;
185 }
186
187
188 void iso14a_set_timeout(uint32_t timeout) {
189 iso14a_timeout = timeout;
190 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
191 }
192
193
194 static void iso14a_set_ATS_timeout(uint8_t *ats) {
195
196 uint8_t tb1;
197 uint8_t fwi;
198 uint32_t fwt;
199
200 if (ats[0] > 1) { // there is a format byte T0
201 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
202 if ((ats[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
203 tb1 = ats[3];
204 } else {
205 tb1 = ats[2];
206 }
207 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
208 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
209
210 iso14a_set_timeout(fwt/(8*16));
211 }
212 }
213 }
214
215
216 //-----------------------------------------------------------------------------
217 // Generate the parity value for a byte sequence
218 //
219 //-----------------------------------------------------------------------------
220 void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
221 {
222 uint16_t paritybit_cnt = 0;
223 uint16_t paritybyte_cnt = 0;
224 uint8_t parityBits = 0;
225
226 for (uint16_t i = 0; i < iLen; i++) {
227 // Generate the parity bits
228 parityBits |= ((oddparity8(pbtCmd[i])) << (7-paritybit_cnt));
229 if (paritybit_cnt == 7) {
230 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
231 parityBits = 0; // and advance to next Parity Byte
232 paritybyte_cnt++;
233 paritybit_cnt = 0;
234 } else {
235 paritybit_cnt++;
236 }
237 }
238
239 // save remaining parity bits
240 par[paritybyte_cnt] = parityBits;
241
242 }
243
244 void AppendCrc14443a(uint8_t* data, int len)
245 {
246 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
247 }
248
249 static void AppendCrc14443b(uint8_t* data, int len)
250 {
251 ComputeCrc14443(CRC_14443_B,data,len,data+len,data+len+1);
252 }
253
254
255 //=============================================================================
256 // ISO 14443 Type A - Miller decoder
257 //=============================================================================
258 // Basics:
259 // This decoder is used when the PM3 acts as a tag.
260 // The reader will generate "pauses" by temporarily switching of the field.
261 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
262 // The FPGA does a comparison with a threshold and would deliver e.g.:
263 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
264 // The Miller decoder needs to identify the following sequences:
265 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
266 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
267 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
268 // Note 1: the bitstream may start at any time. We therefore need to sync.
269 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
270 //-----------------------------------------------------------------------------
271 static tUart Uart;
272
273 // Lookup-Table to decide if 4 raw bits are a modulation.
274 // We accept the following:
275 // 0001 - a 3 tick wide pause
276 // 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
277 // 0111 - a 2 tick wide pause shifted left
278 // 1001 - a 2 tick wide pause shifted right
279 const bool Mod_Miller_LUT[] = {
280 false, true, false, true, false, false, false, true,
281 false, true, false, false, false, false, false, false
282 };
283 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
284 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
285
286 static void UartReset()
287 {
288 Uart.state = STATE_UNSYNCD;
289 Uart.bitCount = 0;
290 Uart.len = 0; // number of decoded data bytes
291 Uart.parityLen = 0; // number of decoded parity bytes
292 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
293 Uart.parityBits = 0; // holds 8 parity bits
294 Uart.startTime = 0;
295 Uart.endTime = 0;
296 }
297
298 static void UartInit(uint8_t *data, uint8_t *parity)
299 {
300 Uart.output = data;
301 Uart.parity = parity;
302 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
303 UartReset();
304 }
305
306 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
307 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
308 {
309
310 Uart.fourBits = (Uart.fourBits << 8) | bit;
311
312 if (Uart.state == STATE_UNSYNCD) { // not yet synced
313
314 Uart.syncBit = 9999; // not set
315 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
316 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
317 // we therefore look for a ...xx11111111111100x11111xxxxxx... pattern
318 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
319 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00000111 11111111 11101111 10000000
320 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00000111 11111111 10001111 10000000
321 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
322 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
323 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
324 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
325 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
326 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
327 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
328 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
329
330 if (Uart.syncBit != 9999) { // found a sync bit
331 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
332 Uart.startTime -= Uart.syncBit;
333 Uart.endTime = Uart.startTime;
334 Uart.state = STATE_START_OF_COMMUNICATION;
335 }
336
337 } else {
338
339 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
340 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
341 UartReset();
342 } else { // Modulation in first half = Sequence Z = logic "0"
343 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
344 UartReset();
345 } else {
346 Uart.bitCount++;
347 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
348 Uart.state = STATE_MILLER_Z;
349 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
350 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
351 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
352 Uart.parityBits <<= 1; // make room for the parity bit
353 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
354 Uart.bitCount = 0;
355 Uart.shiftReg = 0;
356 if((Uart.len&0x0007) == 0) { // every 8 data bytes
357 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
358 Uart.parityBits = 0;
359 }
360 }
361 }
362 }
363 } else {
364 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
365 Uart.bitCount++;
366 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
367 Uart.state = STATE_MILLER_X;
368 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
369 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
370 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
371 Uart.parityBits <<= 1; // make room for the new parity bit
372 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
373 Uart.bitCount = 0;
374 Uart.shiftReg = 0;
375 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
376 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
377 Uart.parityBits = 0;
378 }
379 }
380 } else { // no modulation in both halves - Sequence Y
381 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
382 Uart.state = STATE_UNSYNCD;
383 Uart.bitCount--; // last "0" was part of EOC sequence
384 Uart.shiftReg <<= 1; // drop it
385 if(Uart.bitCount > 0) { // if we decoded some bits
386 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
387 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
388 Uart.parityBits <<= 1; // add a (void) parity bit
389 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
390 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
391 return true;
392 } else if (Uart.len & 0x0007) { // there are some parity bits to store
393 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
394 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
395 }
396 if (Uart.len) {
397 return true; // we are finished with decoding the raw data sequence
398 } else {
399 UartReset(); // Nothing received - start over
400 }
401 }
402 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
403 UartReset();
404 } else { // a logic "0"
405 Uart.bitCount++;
406 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
407 Uart.state = STATE_MILLER_Y;
408 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
409 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
410 Uart.parityBits <<= 1; // make room for the parity bit
411 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
412 Uart.bitCount = 0;
413 Uart.shiftReg = 0;
414 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
415 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
416 Uart.parityBits = 0;
417 }
418 }
419 }
420 }
421 }
422
423 }
424
425 return false; // not finished yet, need more data
426 }
427
428
429
430 //=============================================================================
431 // ISO 14443 Type A - Manchester decoder
432 //=============================================================================
433 // Basics:
434 // This decoder is used when the PM3 acts as a reader.
435 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
436 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
437 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
438 // The Manchester decoder needs to identify the following sequences:
439 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
440 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
441 // 8 ticks unmodulated: Sequence F = end of communication
442 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
443 // Note 1: the bitstream may start at any time. We therefore need to sync.
444 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
445 static tDemod Demod;
446
447 // Lookup-Table to decide if 4 raw bits are a modulation.
448 // We accept three or four "1" in any position
449 const bool Mod_Manchester_LUT[] = {
450 false, false, false, false, false, false, false, true,
451 false, false, false, true, false, true, true, true
452 };
453
454 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
455 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
456
457
458 static void DemodReset()
459 {
460 Demod.state = DEMOD_UNSYNCD;
461 Demod.len = 0; // number of decoded data bytes
462 Demod.parityLen = 0;
463 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
464 Demod.parityBits = 0; //
465 Demod.collisionPos = 0; // Position of collision bit
466 Demod.twoBits = 0xffff; // buffer for 2 Bits
467 Demod.highCnt = 0;
468 Demod.startTime = 0;
469 Demod.endTime = 0;
470 }
471
472 static void DemodInit(uint8_t *data, uint8_t *parity)
473 {
474 Demod.output = data;
475 Demod.parity = parity;
476 DemodReset();
477 }
478
479 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
480 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
481 {
482
483 Demod.twoBits = (Demod.twoBits << 8) | bit;
484
485 if (Demod.state == DEMOD_UNSYNCD) {
486
487 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
488 if (Demod.twoBits == 0x0000) {
489 Demod.highCnt++;
490 } else {
491 Demod.highCnt = 0;
492 }
493 } else {
494 Demod.syncBit = 0xFFFF; // not set
495 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
496 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
497 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
498 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
499 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
500 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
501 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
502 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
503 if (Demod.syncBit != 0xFFFF) {
504 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
505 Demod.startTime -= Demod.syncBit;
506 Demod.bitCount = offset; // number of decoded data bits
507 Demod.state = DEMOD_MANCHESTER_DATA;
508 }
509 }
510
511 } else {
512
513 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
514 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
515 if (!Demod.collisionPos) {
516 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
517 }
518 } // modulation in first half only - Sequence D = 1
519 Demod.bitCount++;
520 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
521 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
522 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
523 Demod.parityBits <<= 1; // make room for the parity bit
524 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
525 Demod.bitCount = 0;
526 Demod.shiftReg = 0;
527 if((Demod.len&0x0007) == 0) { // every 8 data bytes
528 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
529 Demod.parityBits = 0;
530 }
531 }
532 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
533 } else { // no modulation in first half
534 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
535 Demod.bitCount++;
536 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
537 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
538 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
539 Demod.parityBits <<= 1; // make room for the new parity bit
540 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
541 Demod.bitCount = 0;
542 Demod.shiftReg = 0;
543 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
544 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
545 Demod.parityBits = 0;
546 }
547 }
548 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
549 } else { // no modulation in both halves - End of communication
550 if(Demod.bitCount > 0) { // there are some remaining data bits
551 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
552 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
553 Demod.parityBits <<= 1; // add a (void) parity bit
554 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
555 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
556 return true;
557 } else if (Demod.len & 0x0007) { // there are some parity bits to store
558 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
559 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
560 }
561 if (Demod.len) {
562 return true; // we are finished with decoding the raw data sequence
563 } else { // nothing received. Start over
564 DemodReset();
565 }
566 }
567 }
568
569 }
570
571 return false; // not finished yet, need more data
572 }
573
574 //=============================================================================
575 // Finally, a `sniffer' for ISO 14443 Type A
576 // Both sides of communication!
577 //=============================================================================
578
579 //-----------------------------------------------------------------------------
580 // Record the sequence of commands sent by the reader to the tag, with
581 // triggering so that we start recording at the point that the tag is moved
582 // near the reader.
583 //-----------------------------------------------------------------------------
584 void RAMFUNC SnoopIso14443a(uint8_t param) {
585 // param:
586 // bit 0 - trigger from first card answer
587 // bit 1 - trigger from first reader 7-bit request
588
589 LEDsoff();
590
591 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
592
593 // Allocate memory from BigBuf for some buffers
594 // free all previous allocations first
595 BigBuf_free();
596
597 // The command (reader -> tag) that we're receiving.
598 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
599 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
600
601 // The response (tag -> reader) that we're receiving.
602 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
603 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
604
605 // The DMA buffer, used to stream samples from the FPGA
606 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
607
608 // init trace buffer
609 clear_trace();
610 set_tracing(true);
611
612 uint8_t *data = dmaBuf;
613 uint8_t previous_data = 0;
614 int maxDataLen = 0;
615 int dataLen = 0;
616 bool TagIsActive = false;
617 bool ReaderIsActive = false;
618
619 // Set up the demodulator for tag -> reader responses.
620 DemodInit(receivedResponse, receivedResponsePar);
621
622 // Set up the demodulator for the reader -> tag commands
623 UartInit(receivedCmd, receivedCmdPar);
624
625 // Setup and start DMA.
626 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
627
628 // We won't start recording the frames that we acquire until we trigger;
629 // a good trigger condition to get started is probably when we see a
630 // response from the tag.
631 // triggered == false -- to wait first for card
632 bool triggered = !(param & 0x03);
633
634 // And now we loop, receiving samples.
635 for(uint32_t rsamples = 0; true; ) {
636
637 if(BUTTON_PRESS()) {
638 DbpString("cancelled by button");
639 break;
640 }
641
642 LED_A_ON();
643 WDT_HIT();
644
645 int register readBufDataP = data - dmaBuf;
646 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
647 if (readBufDataP <= dmaBufDataP){
648 dataLen = dmaBufDataP - readBufDataP;
649 } else {
650 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
651 }
652 // test for length of buffer
653 if(dataLen > maxDataLen) {
654 maxDataLen = dataLen;
655 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
656 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
657 break;
658 }
659 }
660 if(dataLen < 1) continue;
661
662 // primary buffer was stopped( <-- we lost data!
663 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
664 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
665 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
666 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
667 }
668 // secondary buffer sets as primary, secondary buffer was stopped
669 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
670 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
671 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
672 }
673
674 LED_A_OFF();
675
676 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
677
678 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
679 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
680 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
681 LED_C_ON();
682
683 // check - if there is a short 7bit request from reader
684 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = true;
685
686 if(triggered) {
687 if (!LogTrace(receivedCmd,
688 Uart.len,
689 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
690 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
691 Uart.parity,
692 true)) break;
693 }
694 /* And ready to receive another command. */
695 UartReset();
696 /* And also reset the demod code, which might have been */
697 /* false-triggered by the commands from the reader. */
698 DemodReset();
699 LED_B_OFF();
700 }
701 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
702 }
703
704 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
705 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
706 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
707 LED_B_ON();
708
709 if (!LogTrace(receivedResponse,
710 Demod.len,
711 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
712 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
713 Demod.parity,
714 false)) break;
715
716 if ((!triggered) && (param & 0x01)) triggered = true;
717
718 // And ready to receive another response.
719 DemodReset();
720 // And reset the Miller decoder including itS (now outdated) input buffer
721 UartInit(receivedCmd, receivedCmdPar);
722
723 LED_C_OFF();
724 }
725 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
726 }
727 }
728
729 previous_data = *data;
730 rsamples++;
731 data++;
732 if(data == dmaBuf + DMA_BUFFER_SIZE) {
733 data = dmaBuf;
734 }
735 } // main cycle
736
737 DbpString("COMMAND FINISHED");
738
739 FpgaDisableSscDma();
740 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
741 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
742 LEDsoff();
743 }
744
745 //-----------------------------------------------------------------------------
746 // Prepare tag messages
747 //-----------------------------------------------------------------------------
748 static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
749 {
750 ToSendReset();
751
752 // Correction bit, might be removed when not needed
753 ToSendStuffBit(0);
754 ToSendStuffBit(0);
755 ToSendStuffBit(0);
756 ToSendStuffBit(0);
757 ToSendStuffBit(1); // 1
758 ToSendStuffBit(0);
759 ToSendStuffBit(0);
760 ToSendStuffBit(0);
761
762 // Send startbit
763 ToSend[++ToSendMax] = SEC_D;
764 LastProxToAirDuration = 8 * ToSendMax - 4;
765
766 for(uint16_t i = 0; i < len; i++) {
767 uint8_t b = cmd[i];
768
769 // Data bits
770 for(uint16_t j = 0; j < 8; j++) {
771 if(b & 1) {
772 ToSend[++ToSendMax] = SEC_D;
773 } else {
774 ToSend[++ToSendMax] = SEC_E;
775 }
776 b >>= 1;
777 }
778
779 // Get the parity bit
780 if (parity[i>>3] & (0x80>>(i&0x0007))) {
781 ToSend[++ToSendMax] = SEC_D;
782 LastProxToAirDuration = 8 * ToSendMax - 4;
783 } else {
784 ToSend[++ToSendMax] = SEC_E;
785 LastProxToAirDuration = 8 * ToSendMax;
786 }
787 }
788
789 // Send stopbit
790 ToSend[++ToSendMax] = SEC_F;
791
792 // Convert from last byte pos to length
793 ToSendMax++;
794 }
795
796
797 static void Code4bitAnswerAsTag(uint8_t cmd)
798 {
799 int i;
800
801 ToSendReset();
802
803 // Correction bit, might be removed when not needed
804 ToSendStuffBit(0);
805 ToSendStuffBit(0);
806 ToSendStuffBit(0);
807 ToSendStuffBit(0);
808 ToSendStuffBit(1); // 1
809 ToSendStuffBit(0);
810 ToSendStuffBit(0);
811 ToSendStuffBit(0);
812
813 // Send startbit
814 ToSend[++ToSendMax] = SEC_D;
815
816 uint8_t b = cmd;
817 for(i = 0; i < 4; i++) {
818 if(b & 1) {
819 ToSend[++ToSendMax] = SEC_D;
820 LastProxToAirDuration = 8 * ToSendMax - 4;
821 } else {
822 ToSend[++ToSendMax] = SEC_E;
823 LastProxToAirDuration = 8 * ToSendMax;
824 }
825 b >>= 1;
826 }
827
828 // Send stopbit
829 ToSend[++ToSendMax] = SEC_F;
830
831 // Convert from last byte pos to length
832 ToSendMax++;
833 }
834
835
836 static uint8_t *LastReaderTraceTime = NULL;
837
838 static void EmLogTraceReader(void) {
839 // remember last reader trace start to fix timing info later
840 LastReaderTraceTime = BigBuf_get_addr() + BigBuf_get_traceLen();
841 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, true);
842 }
843
844
845 static void FixLastReaderTraceTime(uint32_t tag_StartTime) {
846 uint32_t reader_EndTime = Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG;
847 uint32_t reader_StartTime = Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG;
848 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
849 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
850 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
851 reader_StartTime = tag_StartTime - exact_fdt - reader_modlen;
852 LastReaderTraceTime[0] = (reader_StartTime >> 0) & 0xff;
853 LastReaderTraceTime[1] = (reader_StartTime >> 8) & 0xff;
854 LastReaderTraceTime[2] = (reader_StartTime >> 16) & 0xff;
855 LastReaderTraceTime[3] = (reader_StartTime >> 24) & 0xff;
856 }
857
858
859 static void EmLogTraceTag(uint8_t *tag_data, uint16_t tag_len, uint8_t *tag_Parity, uint32_t ProxToAirDuration) {
860 uint32_t tag_StartTime = LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG;
861 uint32_t tag_EndTime = (LastTimeProxToAirStart + ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG;
862 LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, false);
863 FixLastReaderTraceTime(tag_StartTime);
864 }
865
866
867 //-----------------------------------------------------------------------------
868 // Wait for commands from reader
869 // Stop when button is pressed
870 // Or return true when command is captured
871 //-----------------------------------------------------------------------------
872 static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
873 {
874 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
875 // only, since we are receiving, not transmitting).
876 // Signal field is off with the appropriate LED
877 LED_D_OFF();
878 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
879
880 // Now run a `software UART' on the stream of incoming samples.
881 UartInit(received, parity);
882
883 // clear RXRDY:
884 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
885
886 for(;;) {
887 WDT_HIT();
888
889 if(BUTTON_PRESS()) return false;
890
891 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
892 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
893 if(MillerDecoding(b, 0)) {
894 *len = Uart.len;
895 EmLogTraceReader();
896 return true;
897 }
898 }
899 }
900 }
901
902
903 static int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
904 int EmSend4bit(uint8_t resp);
905 static int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
906 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
907 int EmSendPrecompiledCmd(tag_response_info_t *response_info, bool correctionNeeded);
908
909
910 static bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
911 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
912 // This will need the following byte array for a modulation sequence
913 // 144 data bits (18 * 8)
914 // 18 parity bits
915 // 2 Start and stop
916 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
917 // 1 just for the case
918 // ----------- +
919 // 166 bytes, since every bit that needs to be send costs us a byte
920 //
921
922
923 // Prepare the tag modulation bits from the message
924 GetParity(response_info->response, response_info->response_n, &(response_info->par));
925 CodeIso14443aAsTagPar(response_info->response,response_info->response_n, &(response_info->par));
926
927 // Make sure we do not exceed the free buffer space
928 if (ToSendMax > max_buffer_size) {
929 Dbprintf("Out of memory, when modulating bits for tag answer:");
930 Dbhexdump(response_info->response_n, response_info->response, false);
931 return false;
932 }
933
934 // Copy the byte array, used for this modulation to the buffer position
935 memcpy(response_info->modulation, ToSend, ToSendMax);
936
937 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
938 response_info->modulation_n = ToSendMax;
939 response_info->ProxToAirDuration = LastProxToAirDuration;
940
941 return true;
942 }
943
944
945 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
946 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
947 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits for the modulation
948 // -> need 273 bytes buffer
949 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
950
951 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info, uint8_t **buffer, size_t *max_buffer_size) {
952
953 // Retrieve and store the current buffer index
954 response_info->modulation = *buffer;
955
956 // Forward the prepare tag modulation function to the inner function
957 if (prepare_tag_modulation(response_info, *max_buffer_size)) {
958 // Update the free buffer offset and the remaining buffer size
959 *buffer += ToSendMax;
960 *max_buffer_size -= ToSendMax;
961 return true;
962 } else {
963 return false;
964 }
965 }
966
967 //-----------------------------------------------------------------------------
968 // Main loop of simulated tag: receive commands from reader, decide what
969 // response to send, and send it.
970 //-----------------------------------------------------------------------------
971 void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
972 {
973 uint8_t sak;
974
975 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
976 uint8_t response1[2];
977
978 switch (tagType) {
979 case 1: { // MIFARE Classic
980 // Says: I am Mifare 1k - original line
981 response1[0] = 0x04;
982 response1[1] = 0x00;
983 sak = 0x08;
984 } break;
985 case 2: { // MIFARE Ultralight
986 // Says: I am a stupid memory tag, no crypto
987 response1[0] = 0x04;
988 response1[1] = 0x00;
989 sak = 0x00;
990 } break;
991 case 3: { // MIFARE DESFire
992 // Says: I am a DESFire tag, ph33r me
993 response1[0] = 0x04;
994 response1[1] = 0x03;
995 sak = 0x20;
996 } break;
997 case 4: { // ISO/IEC 14443-4
998 // Says: I am a javacard (JCOP)
999 response1[0] = 0x04;
1000 response1[1] = 0x00;
1001 sak = 0x28;
1002 } break;
1003 case 5: { // MIFARE TNP3XXX
1004 // Says: I am a toy
1005 response1[0] = 0x01;
1006 response1[1] = 0x0f;
1007 sak = 0x01;
1008 } break;
1009 default: {
1010 Dbprintf("Error: unkown tagtype (%d)",tagType);
1011 return;
1012 } break;
1013 }
1014
1015 // The second response contains the (mandatory) first 24 bits of the UID
1016 uint8_t response2[5] = {0x00};
1017
1018 // Check if the uid uses the (optional) part
1019 uint8_t response2a[5] = {0x00};
1020
1021 if (uid_2nd) {
1022 response2[0] = 0x88;
1023 num_to_bytes(uid_1st,3,response2+1);
1024 num_to_bytes(uid_2nd,4,response2a);
1025 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
1026
1027 // Configure the ATQA and SAK accordingly
1028 response1[0] |= 0x40;
1029 sak |= 0x04;
1030 } else {
1031 num_to_bytes(uid_1st,4,response2);
1032 // Configure the ATQA and SAK accordingly
1033 response1[0] &= 0xBF;
1034 sak &= 0xFB;
1035 }
1036
1037 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
1038 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
1039
1040 // Prepare the mandatory SAK (for 4 and 7 byte UID)
1041 uint8_t response3[3] = {0x00};
1042 response3[0] = sak;
1043 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
1044
1045 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
1046 uint8_t response3a[3] = {0x00};
1047 response3a[0] = sak & 0xFB;
1048 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
1049
1050 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
1051 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1052 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1053 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1054 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1055 // TC(1) = 0x02: CID supported, NAD not supported
1056 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1057
1058 #define TAG_RESPONSE_COUNT 7
1059 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1060 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1061 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1062 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1063 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1064 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1065 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1066 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1067 };
1068
1069 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1070 // Such a response is less time critical, so we can prepare them on the fly
1071 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1072 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1073 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1074 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1075 tag_response_info_t dynamic_response_info = {
1076 .response = dynamic_response_buffer,
1077 .response_n = 0,
1078 .modulation = dynamic_modulation_buffer,
1079 .modulation_n = 0
1080 };
1081
1082 // We need to listen to the high-frequency, peak-detected path.
1083 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1084
1085 BigBuf_free_keep_EM();
1086
1087 // allocate buffers:
1088 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1089 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1090 uint8_t *free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1091 size_t free_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
1092 // clear trace
1093 clear_trace();
1094 set_tracing(true);
1095
1096 // Prepare the responses of the anticollision phase
1097 // there will be not enough time to do this at the moment the reader sends it REQA
1098 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1099 prepare_allocated_tag_modulation(&responses[i], &free_buffer_pointer, &free_buffer_size);
1100 }
1101
1102 int len = 0;
1103
1104 // To control where we are in the protocol
1105 int order = 0;
1106 int lastorder;
1107
1108 // Just to allow some checks
1109 int happened = 0;
1110 int happened2 = 0;
1111 int cmdsRecvd = 0;
1112
1113 cmdsRecvd = 0;
1114 tag_response_info_t* p_response;
1115
1116 LED_A_ON();
1117 for(;;) {
1118 // Clean receive command buffer
1119 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
1120 DbpString("Button press");
1121 break;
1122 }
1123
1124 p_response = NULL;
1125
1126 // Okay, look at the command now.
1127 lastorder = order;
1128 if(receivedCmd[0] == 0x26) { // Received a REQUEST
1129 p_response = &responses[0]; order = 1;
1130 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
1131 p_response = &responses[0]; order = 6;
1132 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
1133 p_response = &responses[1]; order = 2;
1134 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
1135 p_response = &responses[2]; order = 20;
1136 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
1137 p_response = &responses[3]; order = 3;
1138 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
1139 p_response = &responses[4]; order = 30;
1140 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
1141 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
1142 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1143 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1144 p_response = NULL;
1145 } else if(receivedCmd[0] == 0x50) { // Received a HALT
1146 p_response = NULL;
1147 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
1148 p_response = &responses[5]; order = 7;
1149 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
1150 if (tagType == 1 || tagType == 2) { // RATS not supported
1151 EmSend4bit(CARD_NACK_NA);
1152 p_response = NULL;
1153 } else {
1154 p_response = &responses[6]; order = 70;
1155 }
1156 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
1157 uint32_t nr = bytes_to_num(receivedCmd,4);
1158 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1159 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1160 } else {
1161 // Check for ISO 14443A-4 compliant commands, look at left nibble
1162 switch (receivedCmd[0]) {
1163
1164 case 0x0B:
1165 case 0x0A: { // IBlock (command)
1166 dynamic_response_info.response[0] = receivedCmd[0];
1167 dynamic_response_info.response[1] = 0x00;
1168 dynamic_response_info.response[2] = 0x90;
1169 dynamic_response_info.response[3] = 0x00;
1170 dynamic_response_info.response_n = 4;
1171 } break;
1172
1173 case 0x1A:
1174 case 0x1B: { // Chaining command
1175 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1176 dynamic_response_info.response_n = 2;
1177 } break;
1178
1179 case 0xaa:
1180 case 0xbb: {
1181 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1182 dynamic_response_info.response_n = 2;
1183 } break;
1184
1185 case 0xBA: { //
1186 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1187 dynamic_response_info.response_n = 2;
1188 } break;
1189
1190 case 0xCA:
1191 case 0xC2: { // Readers sends deselect command
1192 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1193 dynamic_response_info.response_n = 2;
1194 } break;
1195
1196 default: {
1197 // Never seen this command before
1198 Dbprintf("Received unknown command (len=%d):",len);
1199 Dbhexdump(len,receivedCmd,false);
1200 // Do not respond
1201 dynamic_response_info.response_n = 0;
1202 } break;
1203 }
1204
1205 if (dynamic_response_info.response_n > 0) {
1206 // Copy the CID from the reader query
1207 dynamic_response_info.response[1] = receivedCmd[1];
1208
1209 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1210 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1211 dynamic_response_info.response_n += 2;
1212
1213 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1214 Dbprintf("Error preparing tag response");
1215 break;
1216 }
1217 p_response = &dynamic_response_info;
1218 }
1219 }
1220
1221 // Count number of wakeups received after a halt
1222 if(order == 6 && lastorder == 5) { happened++; }
1223
1224 // Count number of other messages after a halt
1225 if(order != 6 && lastorder == 5) { happened2++; }
1226
1227 if(cmdsRecvd > 999) {
1228 DbpString("1000 commands later...");
1229 break;
1230 }
1231 cmdsRecvd++;
1232
1233 if (p_response != NULL) {
1234 EmSendPrecompiledCmd(p_response, receivedCmd[0] == 0x52);
1235 }
1236
1237 if (!tracing) {
1238 Dbprintf("Trace Full. Simulation stopped.");
1239 break;
1240 }
1241 }
1242
1243 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1244 LED_A_OFF();
1245 BigBuf_free_keep_EM();
1246 }
1247
1248
1249 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1250 // of bits specified in the delay parameter.
1251 static void PrepareDelayedTransfer(uint16_t delay)
1252 {
1253 uint8_t bitmask = 0;
1254 uint8_t bits_to_shift = 0;
1255 uint8_t bits_shifted = 0;
1256
1257 delay &= 0x07;
1258 if (delay) {
1259 for (uint16_t i = 0; i < delay; i++) {
1260 bitmask |= (0x01 << i);
1261 }
1262 ToSend[ToSendMax++] = 0x00;
1263 for (uint16_t i = 0; i < ToSendMax; i++) {
1264 bits_to_shift = ToSend[i] & bitmask;
1265 ToSend[i] = ToSend[i] >> delay;
1266 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1267 bits_shifted = bits_to_shift;
1268 }
1269 }
1270 }
1271
1272
1273 //-------------------------------------------------------------------------------------
1274 // Transmit the command (to the tag) that was placed in ToSend[].
1275 // Parameter timing:
1276 // if NULL: transfer at next possible time, taking into account
1277 // request guard time and frame delay time
1278 // if == 0: transfer immediately and return time of transfer
1279 // if != 0: delay transfer until time specified
1280 //-------------------------------------------------------------------------------------
1281 static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
1282 {
1283
1284 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1285
1286 uint32_t ThisTransferTime = 0;
1287
1288 if (timing) {
1289 if(*timing == 0) { // Measure time
1290 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1291 } else {
1292 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1293 }
1294 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1295 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1296 LastTimeProxToAirStart = *timing;
1297 } else {
1298 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1299 while(GetCountSspClk() < ThisTransferTime);
1300 LastTimeProxToAirStart = ThisTransferTime;
1301 }
1302
1303 // clear TXRDY
1304 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1305
1306 uint16_t c = 0;
1307 for(;;) {
1308 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1309 AT91C_BASE_SSC->SSC_THR = cmd[c];
1310 c++;
1311 if(c >= len) {
1312 break;
1313 }
1314 }
1315 }
1316
1317 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1318 }
1319
1320
1321 //-----------------------------------------------------------------------------
1322 // Prepare reader command (in bits, support short frames) to send to FPGA
1323 //-----------------------------------------------------------------------------
1324 static void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
1325 {
1326 int i, j;
1327 int last;
1328 uint8_t b;
1329
1330 ToSendReset();
1331
1332 // Start of Communication (Seq. Z)
1333 ToSend[++ToSendMax] = SEC_Z;
1334 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1335 last = 0;
1336
1337 size_t bytecount = nbytes(bits);
1338 // Generate send structure for the data bits
1339 for (i = 0; i < bytecount; i++) {
1340 // Get the current byte to send
1341 b = cmd[i];
1342 size_t bitsleft = MIN((bits-(i*8)),8);
1343
1344 for (j = 0; j < bitsleft; j++) {
1345 if (b & 1) {
1346 // Sequence X
1347 ToSend[++ToSendMax] = SEC_X;
1348 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1349 last = 1;
1350 } else {
1351 if (last == 0) {
1352 // Sequence Z
1353 ToSend[++ToSendMax] = SEC_Z;
1354 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1355 } else {
1356 // Sequence Y
1357 ToSend[++ToSendMax] = SEC_Y;
1358 last = 0;
1359 }
1360 }
1361 b >>= 1;
1362 }
1363
1364 // Only transmit parity bit if we transmitted a complete byte
1365 if (j == 8 && parity != NULL) {
1366 // Get the parity bit
1367 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
1368 // Sequence X
1369 ToSend[++ToSendMax] = SEC_X;
1370 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1371 last = 1;
1372 } else {
1373 if (last == 0) {
1374 // Sequence Z
1375 ToSend[++ToSendMax] = SEC_Z;
1376 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1377 } else {
1378 // Sequence Y
1379 ToSend[++ToSendMax] = SEC_Y;
1380 last = 0;
1381 }
1382 }
1383 }
1384 }
1385
1386 // End of Communication: Logic 0 followed by Sequence Y
1387 if (last == 0) {
1388 // Sequence Z
1389 ToSend[++ToSendMax] = SEC_Z;
1390 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1391 } else {
1392 // Sequence Y
1393 ToSend[++ToSendMax] = SEC_Y;
1394 last = 0;
1395 }
1396 ToSend[++ToSendMax] = SEC_Y;
1397
1398 // Convert to length of command:
1399 ToSendMax++;
1400 }
1401
1402
1403 //-----------------------------------------------------------------------------
1404 // Wait for commands from reader
1405 // Stop when button is pressed (return 1) or field was gone (return 2)
1406 // Or return 0 when command is captured
1407 //-----------------------------------------------------------------------------
1408 int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
1409 {
1410 *len = 0;
1411
1412 uint32_t timer = 0, vtime = 0;
1413 int analogCnt = 0;
1414 int analogAVG = 0;
1415
1416 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1417 // only, since we are receiving, not transmitting).
1418 // Signal field is off with the appropriate LED
1419 LED_D_OFF();
1420 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1421
1422 // Set ADC to read field strength
1423 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1424 AT91C_BASE_ADC->ADC_MR =
1425 ADC_MODE_PRESCALE(63) |
1426 ADC_MODE_STARTUP_TIME(1) |
1427 ADC_MODE_SAMPLE_HOLD_TIME(15);
1428 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1429 // start ADC
1430 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1431
1432 // Now run a 'software UART' on the stream of incoming samples.
1433 UartInit(received, parity);
1434
1435 // Clear RXRDY:
1436 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1437
1438 for(;;) {
1439 WDT_HIT();
1440
1441 if (BUTTON_PRESS()) return 1;
1442
1443 // test if the field exists
1444 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1445 analogCnt++;
1446 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1447 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1448 if (analogCnt >= 32) {
1449 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1450 vtime = GetTickCount();
1451 if (!timer) timer = vtime;
1452 // 50ms no field --> card to idle state
1453 if (vtime - timer > 50) return 2;
1454 } else
1455 if (timer) timer = 0;
1456 analogCnt = 0;
1457 analogAVG = 0;
1458 }
1459 }
1460
1461 // receive and test the miller decoding
1462 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1463 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1464 if(MillerDecoding(b, 0)) {
1465 *len = Uart.len;
1466 EmLogTraceReader();
1467 return 0;
1468 }
1469 }
1470
1471 }
1472 }
1473
1474
1475 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
1476 {
1477 uint8_t b;
1478 uint16_t i = 0;
1479
1480 // Modulate Manchester
1481 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1482
1483 // include correction bit if necessary
1484 if (Uart.parityBits & 0x01) {
1485 correctionNeeded = true;
1486 }
1487 if(correctionNeeded) {
1488 // 1236, so correction bit needed
1489 i = 0;
1490 } else {
1491 i = 1;
1492 }
1493
1494 // clear receiving shift register and holding register
1495 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1496 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1497 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1498 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1499
1500 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1501 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1502 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1503 if (AT91C_BASE_SSC->SSC_RHR) break;
1504 }
1505
1506 LastTimeProxToAirStart = (GetCountSspClk() & 0xfffffff8) + (correctionNeeded?8:0);
1507
1508 // send cycle
1509 for(; i < respLen; ) {
1510 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1511 AT91C_BASE_SSC->SSC_THR = resp[i++];
1512 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1513 }
1514
1515 if(BUTTON_PRESS()) {
1516 break;
1517 }
1518 }
1519
1520 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1521 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
1522 for (i = 0; i < fpga_queued_bits/8; ) {
1523 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1524 AT91C_BASE_SSC->SSC_THR = SEC_F;
1525 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1526 i++;
1527 }
1528 }
1529
1530 return 0;
1531 }
1532
1533
1534 static int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1535 Code4bitAnswerAsTag(resp);
1536 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1537 // do the tracing for the previous reader request and this tag answer:
1538 EmLogTraceTag(&resp, 1, NULL, LastProxToAirDuration);
1539 return res;
1540 }
1541
1542
1543 int EmSend4bit(uint8_t resp){
1544 return EmSend4bitEx(resp, false);
1545 }
1546
1547
1548 static int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
1549 CodeIso14443aAsTagPar(resp, respLen, par);
1550 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1551 // do the tracing for the previous reader request and this tag answer:
1552 EmLogTraceTag(resp, respLen, par, LastProxToAirDuration);
1553 return res;
1554 }
1555
1556
1557 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1558 uint8_t par[MAX_PARITY_SIZE];
1559 GetParity(resp, respLen, par);
1560 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
1561 }
1562
1563
1564 int EmSendCmd(uint8_t *resp, uint16_t respLen){
1565 uint8_t par[MAX_PARITY_SIZE];
1566 GetParity(resp, respLen, par);
1567 return EmSendCmdExPar(resp, respLen, false, par);
1568 }
1569
1570
1571 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
1572 return EmSendCmdExPar(resp, respLen, false, par);
1573 }
1574
1575
1576 int EmSendPrecompiledCmd(tag_response_info_t *response_info, bool correctionNeeded) {
1577 int ret = EmSendCmd14443aRaw(response_info->modulation, response_info->modulation_n, correctionNeeded);
1578 // do the tracing for the previous reader request and this tag answer:
1579 EmLogTraceTag(response_info->response, response_info->response_n, &(response_info->par), response_info->ProxToAirDuration);
1580 return ret;
1581 }
1582
1583
1584 //-----------------------------------------------------------------------------
1585 // Wait a certain time for tag response
1586 // If a response is captured return true
1587 // If it takes too long return false
1588 //-----------------------------------------------------------------------------
1589 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
1590 {
1591 uint32_t c;
1592
1593 // Set FPGA mode to "reader listen mode", no modulation (listen
1594 // only, since we are receiving, not transmitting).
1595 // Signal field is on with the appropriate LED
1596 LED_D_ON();
1597 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1598
1599 // Now get the answer from the card
1600 DemodInit(receivedResponse, receivedResponsePar);
1601
1602 // clear RXRDY:
1603 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1604
1605 c = 0;
1606 for(;;) {
1607 WDT_HIT();
1608
1609 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1610 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1611 if(ManchesterDecoding(b, offset, 0)) {
1612 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1613 return true;
1614 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
1615 return false;
1616 }
1617 }
1618 }
1619 }
1620
1621
1622 void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
1623 {
1624 CodeIso14443aBitsAsReaderPar(frame, bits, par);
1625
1626 // Send command to tag
1627 TransmitFor14443a(ToSend, ToSendMax, timing);
1628 if(trigger)
1629 LED_A_ON();
1630
1631 // Log reader command in trace buffer
1632 if (tracing) {
1633 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, true);
1634 }
1635 }
1636
1637
1638 void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
1639 {
1640 ReaderTransmitBitsPar(frame, len*8, par, timing);
1641 }
1642
1643
1644 static void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
1645 {
1646 // Generate parity and redirect
1647 uint8_t par[MAX_PARITY_SIZE];
1648 GetParity(frame, len/8, par);
1649 ReaderTransmitBitsPar(frame, len, par, timing);
1650 }
1651
1652
1653 void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
1654 {
1655 // Generate parity and redirect
1656 uint8_t par[MAX_PARITY_SIZE];
1657 GetParity(frame, len, par);
1658 ReaderTransmitBitsPar(frame, len*8, par, timing);
1659 }
1660
1661
1662 static int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
1663 {
1664 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return false;
1665 if (tracing) {
1666 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, false);
1667 }
1668 return Demod.len;
1669 }
1670
1671
1672 int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
1673 {
1674 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return false;
1675 if (tracing) {
1676 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, false);
1677 }
1678 return Demod.len;
1679 }
1680
1681 // performs iso14443a anticollision (optional) and card select procedure
1682 // fills the uid and cuid pointer unless NULL
1683 // fills the card info record unless NULL
1684 // if anticollision is false, then the UID must be provided in uid_ptr[]
1685 // and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
1686 // requests ATS unless no_rats is true
1687 int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr, bool anticollision, uint8_t num_cascades, bool no_rats) {
1688 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1689 uint8_t sel_all[] = { 0x93,0x20 };
1690 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1691 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1692 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1693 uint8_t resp_par[MAX_PARITY_SIZE];
1694 byte_t uid_resp[4];
1695 size_t uid_resp_len;
1696
1697 uint8_t sak = 0x04; // cascade uid
1698 int cascade_level = 0;
1699 int len;
1700
1701 // init card struct
1702 if(p_hi14a_card) {
1703 p_hi14a_card->uidlen = 0;
1704 memset(p_hi14a_card->uid, 0, 10);
1705 p_hi14a_card->ats_len = 0;
1706 }
1707
1708 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1709 ReaderTransmitBitsPar(wupa, 7, NULL, NULL);
1710
1711 // Receive the ATQA
1712 if(!ReaderReceive(resp, resp_par)) return 0;
1713
1714 if(p_hi14a_card) {
1715 memcpy(p_hi14a_card->atqa, resp, 2);
1716 }
1717
1718 if (anticollision) {
1719 // clear uid
1720 if (uid_ptr) {
1721 memset(uid_ptr,0,10);
1722 }
1723 }
1724
1725 // check for proprietary anticollision:
1726 if ((resp[0] & 0x1F) == 0) {
1727 return 3;
1728 }
1729
1730 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1731 // which case we need to make a cascade 2 request and select - this is a long UID
1732 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1733 for(; sak & 0x04; cascade_level++) {
1734 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1735 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1736
1737 if (anticollision) {
1738 // SELECT_ALL
1739 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1740 if (!ReaderReceive(resp, resp_par)) return 0;
1741
1742 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1743 memset(uid_resp, 0, 4);
1744 uint16_t uid_resp_bits = 0;
1745 uint16_t collision_answer_offset = 0;
1746 // anti-collision-loop:
1747 while (Demod.collisionPos) {
1748 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1749 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1750 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1751 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1752 }
1753 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1754 uid_resp_bits++;
1755 // construct anticollosion command:
1756 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1757 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1758 sel_uid[2+i] = uid_resp[i];
1759 }
1760 collision_answer_offset = uid_resp_bits%8;
1761 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1762 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
1763 }
1764 // finally, add the last bits and BCC of the UID
1765 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1766 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1767 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1768 }
1769
1770 } else { // no collision, use the response to SELECT_ALL as current uid
1771 memcpy(uid_resp, resp, 4);
1772 }
1773 } else {
1774 if (cascade_level < num_cascades - 1) {
1775 uid_resp[0] = 0x88;
1776 memcpy(uid_resp+1, uid_ptr+cascade_level*3, 3);
1777 } else {
1778 memcpy(uid_resp, uid_ptr+cascade_level*3, 4);
1779 }
1780 }
1781 uid_resp_len = 4;
1782
1783 // calculate crypto UID. Always use last 4 Bytes.
1784 if(cuid_ptr) {
1785 *cuid_ptr = bytes_to_num(uid_resp, 4);
1786 }
1787
1788 // Construct SELECT UID command
1789 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1790 memcpy(sel_uid+2, uid_resp, 4); // the UID received during anticollision, or the provided UID
1791 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1792 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1793 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1794
1795 // Receive the SAK
1796 if (!ReaderReceive(resp, resp_par)) return 0;
1797 sak = resp[0];
1798
1799 // Test if more parts of the uid are coming
1800 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1801 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1802 // http://www.nxp.com/documents/application_note/AN10927.pdf
1803 uid_resp[0] = uid_resp[1];
1804 uid_resp[1] = uid_resp[2];
1805 uid_resp[2] = uid_resp[3];
1806 uid_resp_len = 3;
1807 }
1808
1809 if(uid_ptr && anticollision) {
1810 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1811 }
1812
1813 if(p_hi14a_card) {
1814 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1815 p_hi14a_card->uidlen += uid_resp_len;
1816 }
1817 }
1818
1819 if(p_hi14a_card) {
1820 p_hi14a_card->sak = sak;
1821 }
1822
1823 // PICC compilant with iso14443a-4 ---> (SAK & 0x20 != 0)
1824 if( (sak & 0x20) == 0) return 2;
1825
1826 if (!no_rats) {
1827 // Request for answer to select
1828 AppendCrc14443a(rats, 2);
1829 ReaderTransmit(rats, sizeof(rats), NULL);
1830
1831 if (!(len = ReaderReceive(resp, resp_par))) return 0;
1832
1833 if(p_hi14a_card) {
1834 memcpy(p_hi14a_card->ats, resp, len);
1835 p_hi14a_card->ats_len = len;
1836 }
1837
1838 // reset the PCB block number
1839 iso14_pcb_blocknum = 0;
1840
1841 // set default timeout based on ATS
1842 iso14a_set_ATS_timeout(resp);
1843 }
1844 return 1;
1845 }
1846
1847
1848 void iso14443a_setup(uint8_t fpga_minor_mode) {
1849 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1850 // Set up the synchronous serial port
1851 FpgaSetupSsc();
1852 // connect Demodulated Signal to ADC:
1853 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1854
1855 // Signal field is on with the appropriate LED
1856 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1857 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1858 LED_D_ON();
1859 } else {
1860 LED_D_OFF();
1861 }
1862 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
1863
1864 // Start the timer
1865 StartCountSspClk();
1866
1867 DemodReset();
1868 UartReset();
1869 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1870 iso14a_set_timeout(1060); // 10ms default
1871 }
1872
1873
1874 int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1875 uint8_t parity[MAX_PARITY_SIZE];
1876 uint8_t real_cmd[cmd_len+4];
1877 real_cmd[0] = 0x0a; //I-Block
1878 // put block number into the PCB
1879 real_cmd[0] |= iso14_pcb_blocknum;
1880 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1881 memcpy(real_cmd+2, cmd, cmd_len);
1882 AppendCrc14443a(real_cmd,cmd_len+2);
1883
1884 ReaderTransmit(real_cmd, cmd_len+4, NULL);
1885 size_t len = ReaderReceive(data, parity);
1886 uint8_t *data_bytes = (uint8_t *) data;
1887 if (!len)
1888 return 0; //DATA LINK ERROR
1889 // if we received an I- or R(ACK)-Block with a block number equal to the
1890 // current block number, toggle the current block number
1891 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1892 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1893 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1894 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1895 {
1896 iso14_pcb_blocknum ^= 1;
1897 }
1898
1899 return len;
1900 }
1901
1902
1903 //-----------------------------------------------------------------------------
1904 // Read an ISO 14443a tag. Send out commands and store answers.
1905 //
1906 //-----------------------------------------------------------------------------
1907 void ReaderIso14443a(UsbCommand *c)
1908 {
1909 iso14a_command_t param = c->arg[0];
1910 uint8_t *cmd = c->d.asBytes;
1911 size_t len = c->arg[1] & 0xffff;
1912 size_t lenbits = c->arg[1] >> 16;
1913 uint32_t timeout = c->arg[2];
1914 uint32_t arg0 = 0;
1915 byte_t buf[USB_CMD_DATA_SIZE] = {0};
1916 uint8_t par[MAX_PARITY_SIZE];
1917 bool cantSELECT = false;
1918
1919 if(param & ISO14A_CONNECT) {
1920 clear_trace();
1921 }
1922
1923 set_tracing(true);
1924
1925 if(param & ISO14A_REQUEST_TRIGGER) {
1926 iso14a_set_trigger(true);
1927 }
1928
1929 if(param & ISO14A_CONNECT) {
1930 LED_A_ON();
1931 clear_trace();
1932 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
1933 if(!(param & ISO14A_NO_SELECT)) {
1934 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1935 arg0 = iso14443a_select_card(NULL, card, NULL, true, 0, param & ISO14A_NO_RATS);
1936
1937 // if we cant select then we cant send data
1938 if (arg0 != 1 && arg0 != 2) {
1939 // 1 - all is OK with ATS, 2 - without ATS
1940 cantSELECT = true;
1941 }
1942
1943 LED_B_ON();
1944 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1945 LED_B_OFF();
1946 }
1947 }
1948
1949 if(param & ISO14A_SET_TIMEOUT) {
1950 iso14a_set_timeout(timeout);
1951 }
1952
1953 if(param & ISO14A_APDU && !cantSELECT) {
1954 arg0 = iso14_apdu(cmd, len, buf);
1955 LED_B_ON();
1956 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1957 LED_B_OFF();
1958 }
1959
1960 if(param & ISO14A_RAW && !cantSELECT) {
1961 if(param & ISO14A_APPEND_CRC) {
1962 if(param & ISO14A_TOPAZMODE) {
1963 AppendCrc14443b(cmd,len);
1964 } else {
1965 AppendCrc14443a(cmd,len);
1966 }
1967 len += 2;
1968 if (lenbits) lenbits += 16;
1969 }
1970 if(lenbits>0) { // want to send a specific number of bits (e.g. short commands)
1971 if(param & ISO14A_TOPAZMODE) {
1972 int bits_to_send = lenbits;
1973 uint16_t i = 0;
1974 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
1975 bits_to_send -= 7;
1976 while (bits_to_send > 0) {
1977 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
1978 bits_to_send -= 8;
1979 }
1980 } else {
1981 GetParity(cmd, lenbits/8, par);
1982 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
1983 }
1984 } else { // want to send complete bytes only
1985 if(param & ISO14A_TOPAZMODE) {
1986 uint16_t i = 0;
1987 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
1988 while (i < len) {
1989 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
1990 }
1991 } else {
1992 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
1993 }
1994 }
1995 arg0 = ReaderReceive(buf, par);
1996
1997 LED_B_ON();
1998 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1999 LED_B_OFF();
2000 }
2001
2002 if(param & ISO14A_REQUEST_TRIGGER) {
2003 iso14a_set_trigger(false);
2004 }
2005
2006 if(param & ISO14A_NO_DISCONNECT) {
2007 return;
2008 }
2009
2010 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2011 LEDsoff();
2012 }
2013
2014
2015 // Determine the distance between two nonces.
2016 // Assume that the difference is small, but we don't know which is first.
2017 // Therefore try in alternating directions.
2018 static int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2019
2020 uint16_t i;
2021 uint32_t nttmp1, nttmp2;
2022
2023 if (nt1 == nt2) return 0;
2024
2025 nttmp1 = nt1;
2026 nttmp2 = nt2;
2027
2028 for (i = 1; i < 32768; i++) {
2029 nttmp1 = prng_successor(nttmp1, 1);
2030 if (nttmp1 == nt2) return i;
2031 nttmp2 = prng_successor(nttmp2, 1);
2032 if (nttmp2 == nt1) return -i;
2033 }
2034
2035 return(-99999); // either nt1 or nt2 are invalid nonces
2036 }
2037
2038
2039 //-----------------------------------------------------------------------------
2040 // Recover several bits of the cypher stream. This implements (first stages of)
2041 // the algorithm described in "The Dark Side of Security by Obscurity and
2042 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2043 // (article by Nicolas T. Courtois, 2009)
2044 //-----------------------------------------------------------------------------
2045 void ReaderMifare(bool first_try)
2046 {
2047 // Mifare AUTH
2048 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2049 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2050 static uint8_t mf_nr_ar3;
2051
2052 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE];
2053 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE];
2054
2055 if (first_try) {
2056 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2057 }
2058
2059 // free eventually allocated BigBuf memory. We want all for tracing.
2060 BigBuf_free();
2061
2062 clear_trace();
2063 set_tracing(true);
2064
2065 byte_t nt_diff = 0;
2066 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2067 static byte_t par_low = 0;
2068 bool led_on = true;
2069 uint8_t uid[10] ={0};
2070 uint32_t cuid;
2071
2072 uint32_t nt = 0;
2073 uint32_t previous_nt = 0;
2074 static uint32_t nt_attacked = 0;
2075 byte_t par_list[8] = {0x00};
2076 byte_t ks_list[8] = {0x00};
2077
2078 #define PRNG_SEQUENCE_LENGTH (1 << 16);
2079 static uint32_t sync_time;
2080 static int32_t sync_cycles;
2081 int catch_up_cycles = 0;
2082 int last_catch_up = 0;
2083 uint16_t elapsed_prng_sequences;
2084 uint16_t consecutive_resyncs = 0;
2085 int isOK = 0;
2086
2087 if (first_try) {
2088 mf_nr_ar3 = 0;
2089 sync_time = GetCountSspClk() & 0xfffffff8;
2090 sync_cycles = PRNG_SEQUENCE_LENGTH; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the tag nonces).
2091 nt_attacked = 0;
2092 par[0] = 0;
2093 }
2094 else {
2095 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
2096 mf_nr_ar3++;
2097 mf_nr_ar[3] = mf_nr_ar3;
2098 par[0] = par_low;
2099 }
2100
2101 LED_A_ON();
2102 LED_B_OFF();
2103 LED_C_OFF();
2104
2105
2106 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2107 #define MAX_SYNC_TRIES 32
2108 #define NUM_DEBUG_INFOS 8 // per strategy
2109 #define MAX_STRATEGY 3
2110 uint16_t unexpected_random = 0;
2111 uint16_t sync_tries = 0;
2112 int16_t debug_info_nr = -1;
2113 uint16_t strategy = 0;
2114 int32_t debug_info[MAX_STRATEGY][NUM_DEBUG_INFOS];
2115 uint32_t select_time;
2116 uint32_t halt_time;
2117
2118 for(uint16_t i = 0; true; i++) {
2119
2120 LED_C_ON();
2121 WDT_HIT();
2122
2123 // Test if the action was cancelled
2124 if(BUTTON_PRESS()) {
2125 isOK = -1;
2126 break;
2127 }
2128
2129 if (strategy == 2) {
2130 // test with additional hlt command
2131 halt_time = 0;
2132 int len = mifare_sendcmd_short(NULL, false, 0x50, 0x00, receivedAnswer, receivedAnswerPar, &halt_time);
2133 if (len && MF_DBGLEVEL >= 3) {
2134 Dbprintf("Unexpected response of %d bytes to hlt command (additional debugging).", len);
2135 }
2136 }
2137
2138 if (strategy == 3) {
2139 // test with FPGA power off/on
2140 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2141 SpinDelay(200);
2142 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2143 SpinDelay(100);
2144 }
2145
2146 if(!iso14443a_select_card(uid, NULL, &cuid, true, 0, true)) {
2147 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
2148 continue;
2149 }
2150 select_time = GetCountSspClk();
2151
2152 elapsed_prng_sequences = 1;
2153 if (debug_info_nr == -1) {
2154 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
2155 catch_up_cycles = 0;
2156
2157 // if we missed the sync time already, advance to the next nonce repeat
2158 while(GetCountSspClk() > sync_time) {
2159 elapsed_prng_sequences++;
2160 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2161 }
2162
2163 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2164 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2165 } else {
2166 // collect some information on tag nonces for debugging:
2167 #define DEBUG_FIXED_SYNC_CYCLES PRNG_SEQUENCE_LENGTH
2168 if (strategy == 0) {
2169 // nonce distances at fixed time after card select:
2170 sync_time = select_time + DEBUG_FIXED_SYNC_CYCLES;
2171 } else if (strategy == 1) {
2172 // nonce distances at fixed time between authentications:
2173 sync_time = sync_time + DEBUG_FIXED_SYNC_CYCLES;
2174 } else if (strategy == 2) {
2175 // nonce distances at fixed time after halt:
2176 sync_time = halt_time + DEBUG_FIXED_SYNC_CYCLES;
2177 } else {
2178 // nonce_distances at fixed time after power on
2179 sync_time = DEBUG_FIXED_SYNC_CYCLES;
2180 }
2181 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2182 }
2183
2184 // Receive the (4 Byte) "random" nonce
2185 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2186 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2187 continue;
2188 }
2189
2190 previous_nt = nt;
2191 nt = bytes_to_num(receivedAnswer, 4);
2192
2193 // Transmit reader nonce with fake par
2194 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2195
2196 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2197 int nt_distance = dist_nt(previous_nt, nt);
2198 if (nt_distance == 0) {
2199 nt_attacked = nt;
2200 } else {
2201 if (nt_distance == -99999) { // invalid nonce received
2202 unexpected_random++;
2203 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
2204 isOK = -3; // Card has an unpredictable PRNG. Give up
2205 break;
2206 } else {
2207 continue; // continue trying...
2208 }
2209 }
2210 if (++sync_tries > MAX_SYNC_TRIES) {
2211 if (strategy > MAX_STRATEGY || MF_DBGLEVEL < 3) {
2212 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2213 break;
2214 } else { // continue for a while, just to collect some debug info
2215 debug_info[strategy][debug_info_nr] = nt_distance;
2216 debug_info_nr++;
2217 if (debug_info_nr == NUM_DEBUG_INFOS) {
2218 strategy++;
2219 debug_info_nr = 0;
2220 }
2221 continue;
2222 }
2223 }
2224 sync_cycles = (sync_cycles - nt_distance/elapsed_prng_sequences);
2225 if (sync_cycles <= 0) {
2226 sync_cycles += PRNG_SEQUENCE_LENGTH;
2227 }
2228 if (MF_DBGLEVEL >= 3) {
2229 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
2230 }
2231 continue;
2232 }
2233 }
2234
2235 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2236 catch_up_cycles = -dist_nt(nt_attacked, nt);
2237 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2238 catch_up_cycles = 0;
2239 continue;
2240 }
2241 catch_up_cycles /= elapsed_prng_sequences;
2242 if (catch_up_cycles == last_catch_up) {
2243 consecutive_resyncs++;
2244 }
2245 else {
2246 last_catch_up = catch_up_cycles;
2247 consecutive_resyncs = 0;
2248 }
2249 if (consecutive_resyncs < 3) {
2250 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
2251 }
2252 else {
2253 sync_cycles = sync_cycles + catch_up_cycles;
2254 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
2255 last_catch_up = 0;
2256 catch_up_cycles = 0;
2257 consecutive_resyncs = 0;
2258 }
2259 continue;
2260 }
2261
2262 consecutive_resyncs = 0;
2263
2264 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2265 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2266 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2267
2268 if (nt_diff == 0) {
2269 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2270 }
2271
2272 led_on = !led_on;
2273 if(led_on) LED_B_ON(); else LED_B_OFF();
2274
2275 par_list[nt_diff] = SwapBits(par[0], 8);
2276 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2277
2278 // Test if the information is complete
2279 if (nt_diff == 0x07) {
2280 isOK = 1;
2281 break;
2282 }
2283
2284 nt_diff = (nt_diff + 1) & 0x07;
2285 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2286 par[0] = par_low;
2287 } else {
2288 if (nt_diff == 0 && first_try)
2289 {
2290 par[0]++;
2291 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
2292 isOK = -2;
2293 break;
2294 }
2295 } else {
2296 par[0] = ((par[0] & 0x1F) + 1) | par_low;
2297 }
2298 }
2299 }
2300
2301
2302 mf_nr_ar[3] &= 0x1F;
2303
2304 if (isOK == -4) {
2305 if (MF_DBGLEVEL >= 3) {
2306 for (uint16_t i = 0; i <= MAX_STRATEGY; i++) {
2307 for(uint16_t j = 0; j < NUM_DEBUG_INFOS; j++) {
2308 Dbprintf("collected debug info[%d][%d] = %d", i, j, debug_info[i][j]);
2309 }
2310 }
2311 }
2312 }
2313
2314 byte_t buf[28];
2315 memcpy(buf + 0, uid, 4);
2316 num_to_bytes(nt, 4, buf + 4);
2317 memcpy(buf + 8, par_list, 8);
2318 memcpy(buf + 16, ks_list, 8);
2319 memcpy(buf + 24, mf_nr_ar, 4);
2320
2321 cmd_send(CMD_ACK, isOK, 0, 0, buf, 28);
2322
2323 // Thats it...
2324 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2325 LEDsoff();
2326
2327 set_tracing(false);
2328 }
2329
2330
2331 //-----------------------------------------------------------------------------
2332 // MIFARE sniffer.
2333 //
2334 //-----------------------------------------------------------------------------
2335 void RAMFUNC SniffMifare(uint8_t param) {
2336 // param:
2337 // bit 0 - trigger from first card answer
2338 // bit 1 - trigger from first reader 7-bit request
2339
2340 // C(red) A(yellow) B(green)
2341 LEDsoff();
2342 // init trace buffer
2343 clear_trace();
2344 set_tracing(true);
2345
2346 // The command (reader -> tag) that we're receiving.
2347 // The length of a received command will in most cases be no more than 18 bytes.
2348 // So 32 should be enough!
2349 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2350 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
2351 // The response (tag -> reader) that we're receiving.
2352 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
2353 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
2354
2355 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2356
2357 // free eventually allocated BigBuf memory
2358 BigBuf_free();
2359 // allocate the DMA buffer, used to stream samples from the FPGA
2360 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
2361 uint8_t *data = dmaBuf;
2362 uint8_t previous_data = 0;
2363 int maxDataLen = 0;
2364 int dataLen = 0;
2365 bool ReaderIsActive = false;
2366 bool TagIsActive = false;
2367
2368 // Set up the demodulator for tag -> reader responses.
2369 DemodInit(receivedResponse, receivedResponsePar);
2370
2371 // Set up the demodulator for the reader -> tag commands
2372 UartInit(receivedCmd, receivedCmdPar);
2373
2374 // Setup for the DMA.
2375 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2376
2377 LED_D_OFF();
2378
2379 // init sniffer
2380 MfSniffInit();
2381
2382 // And now we loop, receiving samples.
2383 for(uint32_t sniffCounter = 0; true; ) {
2384
2385 if(BUTTON_PRESS()) {
2386 DbpString("cancelled by button");
2387 break;
2388 }
2389
2390 LED_A_ON();
2391 WDT_HIT();
2392
2393 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2394 // check if a transaction is completed (timeout after 2000ms).
2395 // if yes, stop the DMA transfer and send what we have so far to the client
2396 if (MfSniffSend(2000)) {
2397 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2398 sniffCounter = 0;
2399 data = dmaBuf;
2400 maxDataLen = 0;
2401 ReaderIsActive = false;
2402 TagIsActive = false;
2403 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2404 }
2405 }
2406
2407 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2408 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2409 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2410 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2411 } else {
2412 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
2413 }
2414 // test for length of buffer
2415 if(dataLen > maxDataLen) { // we are more behind than ever...
2416 maxDataLen = dataLen;
2417 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
2418 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
2419 break;
2420 }
2421 }
2422 if(dataLen < 1) continue;
2423
2424 // primary buffer was stopped ( <-- we lost data!
2425 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2426 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2427 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
2428 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
2429 }
2430 // secondary buffer sets as primary, secondary buffer was stopped
2431 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2432 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
2433 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2434 }
2435
2436 LED_A_OFF();
2437
2438 if (sniffCounter & 0x01) {
2439
2440 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2441 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2442 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2443 LED_C_INV();
2444 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, true)) break;
2445
2446 /* And ready to receive another command. */
2447 UartInit(receivedCmd, receivedCmdPar);
2448
2449 /* And also reset the demod code */
2450 DemodReset();
2451 }
2452 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2453 }
2454
2455 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2456 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2457 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2458 LED_C_INV();
2459
2460 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, false)) break;
2461
2462 // And ready to receive another response.
2463 DemodReset();
2464 // And reset the Miller decoder including its (now outdated) input buffer
2465 UartInit(receivedCmd, receivedCmdPar);
2466 }
2467 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2468 }
2469 }
2470
2471 previous_data = *data;
2472 sniffCounter++;
2473 data++;
2474 if(data == dmaBuf + DMA_BUFFER_SIZE) {
2475 data = dmaBuf;
2476 }
2477
2478 } // main cycle
2479
2480 DbpString("COMMAND FINISHED");
2481
2482 FpgaDisableSscDma();
2483 MfSniffEnd();
2484
2485 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
2486 LEDsoff();
2487 }
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