Merge pull request #64 from jessegit/csetuidfix
[proxmark3-svn] / armsrc / iso14443a.c
1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12
13 #include "proxmark3.h"
14 #include "apps.h"
15 #include "util.h"
16 #include "string.h"
17 #include "cmd.h"
18
19 #include "iso14443crc.h"
20 #include "iso14443a.h"
21 #include "crapto1.h"
22 #include "mifareutil.h"
23
24 static uint32_t iso14a_timeout;
25 int rsamples = 0;
26 int tracing = TRUE;
27 uint8_t trigger = 0;
28 // the block number for the ISO14443-4 PCB
29 static uint8_t iso14_pcb_blocknum = 0;
30
31 //
32 // ISO14443 timing:
33 //
34 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
35 #define REQUEST_GUARD_TIME (7000/16 + 1)
36 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
37 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
38 // bool LastCommandWasRequest = FALSE;
39
40 //
41 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
42 //
43 // When the PM acts as reader and is receiving tag data, it takes
44 // 3 ticks delay in the AD converter
45 // 16 ticks until the modulation detector completes and sets curbit
46 // 8 ticks until bit_to_arm is assigned from curbit
47 // 8*16 ticks for the transfer from FPGA to ARM
48 // 4*16 ticks until we measure the time
49 // - 8*16 ticks because we measure the time of the previous transfer
50 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
51
52 // When the PM acts as a reader and is sending, it takes
53 // 4*16 ticks until we can write data to the sending hold register
54 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
55 // 8 ticks until the first transfer starts
56 // 8 ticks later the FPGA samples the data
57 // 1 tick to assign mod_sig_coil
58 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
59
60 // When the PM acts as tag and is receiving it takes
61 // 2 ticks delay in the RF part (for the first falling edge),
62 // 3 ticks for the A/D conversion,
63 // 8 ticks on average until the start of the SSC transfer,
64 // 8 ticks until the SSC samples the first data
65 // 7*16 ticks to complete the transfer from FPGA to ARM
66 // 8 ticks until the next ssp_clk rising edge
67 // 4*16 ticks until we measure the time
68 // - 8*16 ticks because we measure the time of the previous transfer
69 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
70
71 // The FPGA will report its internal sending delay in
72 uint16_t FpgaSendQueueDelay;
73 // the 5 first bits are the number of bits buffered in mod_sig_buf
74 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
75 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
76
77 // When the PM acts as tag and is sending, it takes
78 // 4*16 ticks until we can write data to the sending hold register
79 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
80 // 8 ticks until the first transfer starts
81 // 8 ticks later the FPGA samples the data
82 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
83 // + 1 tick to assign mod_sig_coil
84 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
85
86 // When the PM acts as sniffer and is receiving tag data, it takes
87 // 3 ticks A/D conversion
88 // 14 ticks to complete the modulation detection
89 // 8 ticks (on average) until the result is stored in to_arm
90 // + the delays in transferring data - which is the same for
91 // sniffing reader and tag data and therefore not relevant
92 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
93
94 // When the PM acts as sniffer and is receiving reader data, it takes
95 // 2 ticks delay in analogue RF receiver (for the falling edge of the
96 // start bit, which marks the start of the communication)
97 // 3 ticks A/D conversion
98 // 8 ticks on average until the data is stored in to_arm.
99 // + the delays in transferring data - which is the same for
100 // sniffing reader and tag data and therefore not relevant
101 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
102
103 //variables used for timing purposes:
104 //these are in ssp_clk cycles:
105 static uint32_t NextTransferTime;
106 static uint32_t LastTimeProxToAirStart;
107 static uint32_t LastProxToAirDuration;
108
109
110
111 // CARD TO READER - manchester
112 // Sequence D: 11110000 modulation with subcarrier during first half
113 // Sequence E: 00001111 modulation with subcarrier during second half
114 // Sequence F: 00000000 no modulation with subcarrier
115 // READER TO CARD - miller
116 // Sequence X: 00001100 drop after half a period
117 // Sequence Y: 00000000 no drop
118 // Sequence Z: 11000000 drop at start
119 #define SEC_D 0xf0
120 #define SEC_E 0x0f
121 #define SEC_F 0x00
122 #define SEC_X 0x0c
123 #define SEC_Y 0x00
124 #define SEC_Z 0xc0
125
126 const uint8_t OddByteParity[256] = {
127 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
128 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
129 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
130 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
131 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
132 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
133 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
134 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
135 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
136 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
137 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
138 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
139 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
140 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
141 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
142 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
143 };
144
145 void iso14a_set_trigger(bool enable) {
146 trigger = enable;
147 }
148
149 void iso14a_clear_trace() {
150 uint8_t *trace = BigBuf_get_addr();
151 uint16_t max_traceLen = BigBuf_max_traceLen();
152 memset(trace, 0x44, max_traceLen);
153 traceLen = 0;
154 }
155
156 void iso14a_set_tracing(bool enable) {
157 tracing = enable;
158 }
159
160 void iso14a_set_timeout(uint32_t timeout) {
161 iso14a_timeout = timeout;
162 }
163
164 //-----------------------------------------------------------------------------
165 // Generate the parity value for a byte sequence
166 //
167 //-----------------------------------------------------------------------------
168 byte_t oddparity (const byte_t bt)
169 {
170 return OddByteParity[bt];
171 }
172
173 void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
174 {
175 uint16_t paritybit_cnt = 0;
176 uint16_t paritybyte_cnt = 0;
177 uint8_t parityBits = 0;
178
179 for (uint16_t i = 0; i < iLen; i++) {
180 // Generate the parity bits
181 parityBits |= ((OddByteParity[pbtCmd[i]]) << (7-paritybit_cnt));
182 if (paritybit_cnt == 7) {
183 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
184 parityBits = 0; // and advance to next Parity Byte
185 paritybyte_cnt++;
186 paritybit_cnt = 0;
187 } else {
188 paritybit_cnt++;
189 }
190 }
191
192 // save remaining parity bits
193 par[paritybyte_cnt] = parityBits;
194
195 }
196
197 void AppendCrc14443a(uint8_t* data, int len)
198 {
199 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
200 }
201
202 // The function LogTrace() is also used by the iClass implementation in iClass.c
203 bool RAMFUNC LogTrace(const uint8_t *btBytes, uint16_t iLen, uint32_t timestamp_start, uint32_t timestamp_end, uint8_t *parity, bool readerToTag)
204 {
205 if (!tracing) return FALSE;
206
207 uint8_t *trace = BigBuf_get_addr();
208 uint16_t num_paritybytes = (iLen-1)/8 + 1; // number of valid paritybytes in *parity
209 uint16_t duration = timestamp_end - timestamp_start;
210
211 // Return when trace is full
212 uint16_t max_traceLen = BigBuf_max_traceLen();
213 if (traceLen + sizeof(iLen) + sizeof(timestamp_start) + sizeof(duration) + num_paritybytes + iLen >= max_traceLen) {
214 tracing = FALSE; // don't trace any more
215 return FALSE;
216 }
217
218 // Traceformat:
219 // 32 bits timestamp (little endian)
220 // 16 bits duration (little endian)
221 // 16 bits data length (little endian, Highest Bit used as readerToTag flag)
222 // y Bytes data
223 // x Bytes parity (one byte per 8 bytes data)
224
225 // timestamp (start)
226 trace[traceLen++] = ((timestamp_start >> 0) & 0xff);
227 trace[traceLen++] = ((timestamp_start >> 8) & 0xff);
228 trace[traceLen++] = ((timestamp_start >> 16) & 0xff);
229 trace[traceLen++] = ((timestamp_start >> 24) & 0xff);
230
231 // duration
232 trace[traceLen++] = ((duration >> 0) & 0xff);
233 trace[traceLen++] = ((duration >> 8) & 0xff);
234
235 // data length
236 trace[traceLen++] = ((iLen >> 0) & 0xff);
237 trace[traceLen++] = ((iLen >> 8) & 0xff);
238
239 // readerToTag flag
240 if (!readerToTag) {
241 trace[traceLen - 1] |= 0x80;
242 }
243
244 // data bytes
245 if (btBytes != NULL && iLen != 0) {
246 memcpy(trace + traceLen, btBytes, iLen);
247 }
248 traceLen += iLen;
249
250 // parity bytes
251 if (parity != NULL && iLen != 0) {
252 memcpy(trace + traceLen, parity, num_paritybytes);
253 }
254 traceLen += num_paritybytes;
255
256 return TRUE;
257 }
258
259 //=============================================================================
260 // ISO 14443 Type A - Miller decoder
261 //=============================================================================
262 // Basics:
263 // This decoder is used when the PM3 acts as a tag.
264 // The reader will generate "pauses" by temporarily switching of the field.
265 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
266 // The FPGA does a comparison with a threshold and would deliver e.g.:
267 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
268 // The Miller decoder needs to identify the following sequences:
269 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
270 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
271 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
272 // Note 1: the bitstream may start at any time. We therefore need to sync.
273 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
274 //-----------------------------------------------------------------------------
275 static tUart Uart;
276
277 // Lookup-Table to decide if 4 raw bits are a modulation.
278 // We accept two or three consecutive "0" in any position with the rest "1"
279 const bool Mod_Miller_LUT[] = {
280 TRUE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE,
281 TRUE, TRUE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE
282 };
283 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x00F0) >> 4])
284 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x000F)])
285
286 void UartReset()
287 {
288 Uart.state = STATE_UNSYNCD;
289 Uart.bitCount = 0;
290 Uart.len = 0; // number of decoded data bytes
291 Uart.parityLen = 0; // number of decoded parity bytes
292 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
293 Uart.parityBits = 0; // holds 8 parity bits
294 Uart.twoBits = 0x0000; // buffer for 2 Bits
295 Uart.highCnt = 0;
296 Uart.startTime = 0;
297 Uart.endTime = 0;
298 }
299
300 void UartInit(uint8_t *data, uint8_t *parity)
301 {
302 Uart.output = data;
303 Uart.parity = parity;
304 UartReset();
305 }
306
307 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
308 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
309 {
310
311 Uart.twoBits = (Uart.twoBits << 8) | bit;
312
313 if (Uart.state == STATE_UNSYNCD) { // not yet synced
314
315 if (Uart.highCnt < 2) { // wait for a stable unmodulated signal
316 if (Uart.twoBits == 0xffff) {
317 Uart.highCnt++;
318 } else {
319 Uart.highCnt = 0;
320 }
321 } else {
322 Uart.syncBit = 0xFFFF; // not set
323 // we look for a ...1111111100x11111xxxxxx pattern (the start bit)
324 if ((Uart.twoBits & 0xDF00) == 0x1F00) Uart.syncBit = 8; // mask is 11x11111 xxxxxxxx,
325 // check for 00x11111 xxxxxxxx
326 else if ((Uart.twoBits & 0xEF80) == 0x8F80) Uart.syncBit = 7; // both masks shifted right one bit, left padded with '1'
327 else if ((Uart.twoBits & 0xF7C0) == 0xC7C0) Uart.syncBit = 6; // ...
328 else if ((Uart.twoBits & 0xFBE0) == 0xE3E0) Uart.syncBit = 5;
329 else if ((Uart.twoBits & 0xFDF0) == 0xF1F0) Uart.syncBit = 4;
330 else if ((Uart.twoBits & 0xFEF8) == 0xF8F8) Uart.syncBit = 3;
331 else if ((Uart.twoBits & 0xFF7C) == 0xFC7C) Uart.syncBit = 2;
332 else if ((Uart.twoBits & 0xFFBE) == 0xFE3E) Uart.syncBit = 1;
333 if (Uart.syncBit != 0xFFFF) { // found a sync bit
334 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
335 Uart.startTime -= Uart.syncBit;
336 Uart.endTime = Uart.startTime;
337 Uart.state = STATE_START_OF_COMMUNICATION;
338 }
339 }
340
341 } else {
342
343 if (IsMillerModulationNibble1(Uart.twoBits >> Uart.syncBit)) {
344 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation in both halves - error
345 UartReset();
346 } else { // Modulation in first half = Sequence Z = logic "0"
347 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
348 UartReset();
349 } else {
350 Uart.bitCount++;
351 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
352 Uart.state = STATE_MILLER_Z;
353 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
354 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
355 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
356 Uart.parityBits <<= 1; // make room for the parity bit
357 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
358 Uart.bitCount = 0;
359 Uart.shiftReg = 0;
360 if((Uart.len&0x0007) == 0) { // every 8 data bytes
361 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
362 Uart.parityBits = 0;
363 }
364 }
365 }
366 }
367 } else {
368 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
369 Uart.bitCount++;
370 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
371 Uart.state = STATE_MILLER_X;
372 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
373 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
374 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
375 Uart.parityBits <<= 1; // make room for the new parity bit
376 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
377 Uart.bitCount = 0;
378 Uart.shiftReg = 0;
379 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
380 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
381 Uart.parityBits = 0;
382 }
383 }
384 } else { // no modulation in both halves - Sequence Y
385 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
386 Uart.state = STATE_UNSYNCD;
387 Uart.bitCount--; // last "0" was part of EOC sequence
388 Uart.shiftReg <<= 1; // drop it
389 if(Uart.bitCount > 0) { // if we decoded some bits
390 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
391 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
392 Uart.parityBits <<= 1; // add a (void) parity bit
393 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
394 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
395 return TRUE;
396 } else if (Uart.len & 0x0007) { // there are some parity bits to store
397 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
398 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
399 }
400 if (Uart.len) {
401 return TRUE; // we are finished with decoding the raw data sequence
402 } else {
403 UartReset(); // Nothing received - start over
404 Uart.highCnt = 1;
405 }
406 }
407 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
408 UartReset();
409 Uart.highCnt = 1;
410 } else { // a logic "0"
411 Uart.bitCount++;
412 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
413 Uart.state = STATE_MILLER_Y;
414 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
415 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
416 Uart.parityBits <<= 1; // make room for the parity bit
417 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
418 Uart.bitCount = 0;
419 Uart.shiftReg = 0;
420 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
421 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
422 Uart.parityBits = 0;
423 }
424 }
425 }
426 }
427 }
428
429 }
430
431 return FALSE; // not finished yet, need more data
432 }
433
434
435
436 //=============================================================================
437 // ISO 14443 Type A - Manchester decoder
438 //=============================================================================
439 // Basics:
440 // This decoder is used when the PM3 acts as a reader.
441 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
442 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
443 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
444 // The Manchester decoder needs to identify the following sequences:
445 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
446 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
447 // 8 ticks unmodulated: Sequence F = end of communication
448 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
449 // Note 1: the bitstream may start at any time. We therefore need to sync.
450 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
451 static tDemod Demod;
452
453 // Lookup-Table to decide if 4 raw bits are a modulation.
454 // We accept three or four "1" in any position
455 const bool Mod_Manchester_LUT[] = {
456 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
457 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
458 };
459
460 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
461 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
462
463
464 void DemodReset()
465 {
466 Demod.state = DEMOD_UNSYNCD;
467 Demod.len = 0; // number of decoded data bytes
468 Demod.parityLen = 0;
469 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
470 Demod.parityBits = 0; //
471 Demod.collisionPos = 0; // Position of collision bit
472 Demod.twoBits = 0xffff; // buffer for 2 Bits
473 Demod.highCnt = 0;
474 Demod.startTime = 0;
475 Demod.endTime = 0;
476 }
477
478 void DemodInit(uint8_t *data, uint8_t *parity)
479 {
480 Demod.output = data;
481 Demod.parity = parity;
482 DemodReset();
483 }
484
485 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
486 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
487 {
488
489 Demod.twoBits = (Demod.twoBits << 8) | bit;
490
491 if (Demod.state == DEMOD_UNSYNCD) {
492
493 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
494 if (Demod.twoBits == 0x0000) {
495 Demod.highCnt++;
496 } else {
497 Demod.highCnt = 0;
498 }
499 } else {
500 Demod.syncBit = 0xFFFF; // not set
501 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
502 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
503 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
504 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
505 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
506 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
507 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
508 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
509 if (Demod.syncBit != 0xFFFF) {
510 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
511 Demod.startTime -= Demod.syncBit;
512 Demod.bitCount = offset; // number of decoded data bits
513 Demod.state = DEMOD_MANCHESTER_DATA;
514 }
515 }
516
517 } else {
518
519 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
520 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
521 if (!Demod.collisionPos) {
522 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
523 }
524 } // modulation in first half only - Sequence D = 1
525 Demod.bitCount++;
526 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
527 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
528 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
529 Demod.parityBits <<= 1; // make room for the parity bit
530 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
531 Demod.bitCount = 0;
532 Demod.shiftReg = 0;
533 if((Demod.len&0x0007) == 0) { // every 8 data bytes
534 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
535 Demod.parityBits = 0;
536 }
537 }
538 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
539 } else { // no modulation in first half
540 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
541 Demod.bitCount++;
542 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
543 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
544 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
545 Demod.parityBits <<= 1; // make room for the new parity bit
546 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
547 Demod.bitCount = 0;
548 Demod.shiftReg = 0;
549 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
550 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
551 Demod.parityBits = 0;
552 }
553 }
554 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
555 } else { // no modulation in both halves - End of communication
556 if(Demod.bitCount > 0) { // there are some remaining data bits
557 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
558 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
559 Demod.parityBits <<= 1; // add a (void) parity bit
560 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
561 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
562 return TRUE;
563 } else if (Demod.len & 0x0007) { // there are some parity bits to store
564 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
565 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
566 }
567 if (Demod.len) {
568 return TRUE; // we are finished with decoding the raw data sequence
569 } else { // nothing received. Start over
570 DemodReset();
571 }
572 }
573 }
574
575 }
576
577 return FALSE; // not finished yet, need more data
578 }
579
580 //=============================================================================
581 // Finally, a `sniffer' for ISO 14443 Type A
582 // Both sides of communication!
583 //=============================================================================
584
585 //-----------------------------------------------------------------------------
586 // Record the sequence of commands sent by the reader to the tag, with
587 // triggering so that we start recording at the point that the tag is moved
588 // near the reader.
589 //-----------------------------------------------------------------------------
590 void RAMFUNC SnoopIso14443a(uint8_t param) {
591 // param:
592 // bit 0 - trigger from first card answer
593 // bit 1 - trigger from first reader 7-bit request
594
595 LEDsoff();
596
597 // We won't start recording the frames that we acquire until we trigger;
598 // a good trigger condition to get started is probably when we see a
599 // response from the tag.
600 // triggered == FALSE -- to wait first for card
601 bool triggered = !(param & 0x03);
602
603 // Allocate memory from BigBuf for some buffers
604 // free all previous allocations first
605 BigBuf_free();
606
607 // The command (reader -> tag) that we're receiving.
608 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
609 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
610
611 // The response (tag -> reader) that we're receiving.
612 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
613 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
614
615 // The DMA buffer, used to stream samples from the FPGA
616 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
617
618 // init trace buffer
619 iso14a_clear_trace();
620 iso14a_set_tracing(TRUE);
621
622 uint8_t *data = dmaBuf;
623 uint8_t previous_data = 0;
624 int maxDataLen = 0;
625 int dataLen = 0;
626 bool TagIsActive = FALSE;
627 bool ReaderIsActive = FALSE;
628
629 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
630
631 // Set up the demodulator for tag -> reader responses.
632 DemodInit(receivedResponse, receivedResponsePar);
633
634 // Set up the demodulator for the reader -> tag commands
635 UartInit(receivedCmd, receivedCmdPar);
636
637 // Setup and start DMA.
638 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
639
640 // And now we loop, receiving samples.
641 for(uint32_t rsamples = 0; TRUE; ) {
642
643 if(BUTTON_PRESS()) {
644 DbpString("cancelled by button");
645 break;
646 }
647
648 LED_A_ON();
649 WDT_HIT();
650
651 int register readBufDataP = data - dmaBuf;
652 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
653 if (readBufDataP <= dmaBufDataP){
654 dataLen = dmaBufDataP - readBufDataP;
655 } else {
656 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
657 }
658 // test for length of buffer
659 if(dataLen > maxDataLen) {
660 maxDataLen = dataLen;
661 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
662 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
663 break;
664 }
665 }
666 if(dataLen < 1) continue;
667
668 // primary buffer was stopped( <-- we lost data!
669 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
670 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
671 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
672 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
673 }
674 // secondary buffer sets as primary, secondary buffer was stopped
675 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
676 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
677 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
678 }
679
680 LED_A_OFF();
681
682 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
683
684 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
685 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
686 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
687 LED_C_ON();
688
689 // check - if there is a short 7bit request from reader
690 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
691
692 if(triggered) {
693 if (!LogTrace(receivedCmd,
694 Uart.len,
695 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
696 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
697 Uart.parity,
698 TRUE)) break;
699 }
700 /* And ready to receive another command. */
701 UartReset();
702 /* And also reset the demod code, which might have been */
703 /* false-triggered by the commands from the reader. */
704 DemodReset();
705 LED_B_OFF();
706 }
707 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
708 }
709
710 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
711 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
712 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
713 LED_B_ON();
714
715 if (!LogTrace(receivedResponse,
716 Demod.len,
717 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
718 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
719 Demod.parity,
720 FALSE)) break;
721
722 if ((!triggered) && (param & 0x01)) triggered = TRUE;
723
724 // And ready to receive another response.
725 DemodReset();
726 LED_C_OFF();
727 }
728 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
729 }
730 }
731
732 previous_data = *data;
733 rsamples++;
734 data++;
735 if(data == dmaBuf + DMA_BUFFER_SIZE) {
736 data = dmaBuf;
737 }
738 } // main cycle
739
740 DbpString("COMMAND FINISHED");
741
742 FpgaDisableSscDma();
743 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
744 Dbprintf("traceLen=%d, Uart.output[0]=%08x", traceLen, (uint32_t)Uart.output[0]);
745 LEDsoff();
746 }
747
748 //-----------------------------------------------------------------------------
749 // Prepare tag messages
750 //-----------------------------------------------------------------------------
751 static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
752 {
753 ToSendReset();
754
755 // Correction bit, might be removed when not needed
756 ToSendStuffBit(0);
757 ToSendStuffBit(0);
758 ToSendStuffBit(0);
759 ToSendStuffBit(0);
760 ToSendStuffBit(1); // 1
761 ToSendStuffBit(0);
762 ToSendStuffBit(0);
763 ToSendStuffBit(0);
764
765 // Send startbit
766 ToSend[++ToSendMax] = SEC_D;
767 LastProxToAirDuration = 8 * ToSendMax - 4;
768
769 for(uint16_t i = 0; i < len; i++) {
770 uint8_t b = cmd[i];
771
772 // Data bits
773 for(uint16_t j = 0; j < 8; j++) {
774 if(b & 1) {
775 ToSend[++ToSendMax] = SEC_D;
776 } else {
777 ToSend[++ToSendMax] = SEC_E;
778 }
779 b >>= 1;
780 }
781
782 // Get the parity bit
783 if (parity[i>>3] & (0x80>>(i&0x0007))) {
784 ToSend[++ToSendMax] = SEC_D;
785 LastProxToAirDuration = 8 * ToSendMax - 4;
786 } else {
787 ToSend[++ToSendMax] = SEC_E;
788 LastProxToAirDuration = 8 * ToSendMax;
789 }
790 }
791
792 // Send stopbit
793 ToSend[++ToSendMax] = SEC_F;
794
795 // Convert from last byte pos to length
796 ToSendMax++;
797 }
798
799 static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
800 {
801 uint8_t par[MAX_PARITY_SIZE];
802
803 GetParity(cmd, len, par);
804 CodeIso14443aAsTagPar(cmd, len, par);
805 }
806
807
808 static void Code4bitAnswerAsTag(uint8_t cmd)
809 {
810 int i;
811
812 ToSendReset();
813
814 // Correction bit, might be removed when not needed
815 ToSendStuffBit(0);
816 ToSendStuffBit(0);
817 ToSendStuffBit(0);
818 ToSendStuffBit(0);
819 ToSendStuffBit(1); // 1
820 ToSendStuffBit(0);
821 ToSendStuffBit(0);
822 ToSendStuffBit(0);
823
824 // Send startbit
825 ToSend[++ToSendMax] = SEC_D;
826
827 uint8_t b = cmd;
828 for(i = 0; i < 4; i++) {
829 if(b & 1) {
830 ToSend[++ToSendMax] = SEC_D;
831 LastProxToAirDuration = 8 * ToSendMax - 4;
832 } else {
833 ToSend[++ToSendMax] = SEC_E;
834 LastProxToAirDuration = 8 * ToSendMax;
835 }
836 b >>= 1;
837 }
838
839 // Send stopbit
840 ToSend[++ToSendMax] = SEC_F;
841
842 // Convert from last byte pos to length
843 ToSendMax++;
844 }
845
846 //-----------------------------------------------------------------------------
847 // Wait for commands from reader
848 // Stop when button is pressed
849 // Or return TRUE when command is captured
850 //-----------------------------------------------------------------------------
851 static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
852 {
853 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
854 // only, since we are receiving, not transmitting).
855 // Signal field is off with the appropriate LED
856 LED_D_OFF();
857 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
858
859 // Now run a `software UART' on the stream of incoming samples.
860 UartInit(received, parity);
861
862 // clear RXRDY:
863 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
864
865 for(;;) {
866 WDT_HIT();
867
868 if(BUTTON_PRESS()) return FALSE;
869
870 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
871 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
872 if(MillerDecoding(b, 0)) {
873 *len = Uart.len;
874 return TRUE;
875 }
876 }
877 }
878 }
879
880 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
881 int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
882 int EmSend4bit(uint8_t resp);
883 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
884 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
885 int EmSendCmd(uint8_t *resp, uint16_t respLen);
886 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
887 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
888 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
889
890 static uint8_t* free_buffer_pointer;
891
892 typedef struct {
893 uint8_t* response;
894 size_t response_n;
895 uint8_t* modulation;
896 size_t modulation_n;
897 uint32_t ProxToAirDuration;
898 } tag_response_info_t;
899
900 bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
901 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
902 // This will need the following byte array for a modulation sequence
903 // 144 data bits (18 * 8)
904 // 18 parity bits
905 // 2 Start and stop
906 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
907 // 1 just for the case
908 // ----------- +
909 // 166 bytes, since every bit that needs to be send costs us a byte
910 //
911
912
913 // Prepare the tag modulation bits from the message
914 CodeIso14443aAsTag(response_info->response,response_info->response_n);
915
916 // Make sure we do not exceed the free buffer space
917 if (ToSendMax > max_buffer_size) {
918 Dbprintf("Out of memory, when modulating bits for tag answer:");
919 Dbhexdump(response_info->response_n,response_info->response,false);
920 return false;
921 }
922
923 // Copy the byte array, used for this modulation to the buffer position
924 memcpy(response_info->modulation,ToSend,ToSendMax);
925
926 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
927 response_info->modulation_n = ToSendMax;
928 response_info->ProxToAirDuration = LastProxToAirDuration;
929
930 return true;
931 }
932
933
934 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
935 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
936 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
937 // -> need 273 bytes buffer
938 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
939
940 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
941 // Retrieve and store the current buffer index
942 response_info->modulation = free_buffer_pointer;
943
944 // Determine the maximum size we can use from our buffer
945 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
946
947 // Forward the prepare tag modulation function to the inner function
948 if (prepare_tag_modulation(response_info, max_buffer_size)) {
949 // Update the free buffer offset
950 free_buffer_pointer += ToSendMax;
951 return true;
952 } else {
953 return false;
954 }
955 }
956
957 //-----------------------------------------------------------------------------
958 // Main loop of simulated tag: receive commands from reader, decide what
959 // response to send, and send it.
960 //-----------------------------------------------------------------------------
961 void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
962 {
963 uint8_t sak;
964
965 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
966 uint8_t response1[2];
967
968 switch (tagType) {
969 case 1: { // MIFARE Classic
970 // Says: I am Mifare 1k - original line
971 response1[0] = 0x04;
972 response1[1] = 0x00;
973 sak = 0x08;
974 } break;
975 case 2: { // MIFARE Ultralight
976 // Says: I am a stupid memory tag, no crypto
977 response1[0] = 0x04;
978 response1[1] = 0x00;
979 sak = 0x00;
980 } break;
981 case 3: { // MIFARE DESFire
982 // Says: I am a DESFire tag, ph33r me
983 response1[0] = 0x04;
984 response1[1] = 0x03;
985 sak = 0x20;
986 } break;
987 case 4: { // ISO/IEC 14443-4
988 // Says: I am a javacard (JCOP)
989 response1[0] = 0x04;
990 response1[1] = 0x00;
991 sak = 0x28;
992 } break;
993 case 5: { // MIFARE TNP3XXX
994 // Says: I am a toy
995 response1[0] = 0x01;
996 response1[1] = 0x0f;
997 sak = 0x01;
998 } break;
999 default: {
1000 Dbprintf("Error: unkown tagtype (%d)",tagType);
1001 return;
1002 } break;
1003 }
1004
1005 // The second response contains the (mandatory) first 24 bits of the UID
1006 uint8_t response2[5] = {0x00};
1007
1008 // Check if the uid uses the (optional) part
1009 uint8_t response2a[5] = {0x00};
1010
1011 if (uid_2nd) {
1012 response2[0] = 0x88;
1013 num_to_bytes(uid_1st,3,response2+1);
1014 num_to_bytes(uid_2nd,4,response2a);
1015 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
1016
1017 // Configure the ATQA and SAK accordingly
1018 response1[0] |= 0x40;
1019 sak |= 0x04;
1020 } else {
1021 num_to_bytes(uid_1st,4,response2);
1022 // Configure the ATQA and SAK accordingly
1023 response1[0] &= 0xBF;
1024 sak &= 0xFB;
1025 }
1026
1027 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
1028 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
1029
1030 // Prepare the mandatory SAK (for 4 and 7 byte UID)
1031 uint8_t response3[3] = {0x00};
1032 response3[0] = sak;
1033 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
1034
1035 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
1036 uint8_t response3a[3] = {0x00};
1037 response3a[0] = sak & 0xFB;
1038 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
1039
1040 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
1041 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1042 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1043 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1044 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1045 // TC(1) = 0x02: CID supported, NAD not supported
1046 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1047
1048 #define TAG_RESPONSE_COUNT 7
1049 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1050 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1051 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1052 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1053 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1054 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1055 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1056 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1057 };
1058
1059 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1060 // Such a response is less time critical, so we can prepare them on the fly
1061 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1062 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1063 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1064 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1065 tag_response_info_t dynamic_response_info = {
1066 .response = dynamic_response_buffer,
1067 .response_n = 0,
1068 .modulation = dynamic_modulation_buffer,
1069 .modulation_n = 0
1070 };
1071
1072 BigBuf_free_keep_EM();
1073
1074 // allocate buffers:
1075 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1076 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1077 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1078
1079 // clear trace
1080 iso14a_clear_trace();
1081 iso14a_set_tracing(TRUE);
1082
1083 // Prepare the responses of the anticollision phase
1084 // there will be not enough time to do this at the moment the reader sends it REQA
1085 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1086 prepare_allocated_tag_modulation(&responses[i]);
1087 }
1088
1089 int len = 0;
1090
1091 // To control where we are in the protocol
1092 int order = 0;
1093 int lastorder;
1094
1095 // Just to allow some checks
1096 int happened = 0;
1097 int happened2 = 0;
1098 int cmdsRecvd = 0;
1099
1100 // We need to listen to the high-frequency, peak-detected path.
1101 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1102
1103 cmdsRecvd = 0;
1104 tag_response_info_t* p_response;
1105
1106 LED_A_ON();
1107 for(;;) {
1108 // Clean receive command buffer
1109
1110 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
1111 DbpString("Button press");
1112 break;
1113 }
1114
1115 p_response = NULL;
1116
1117 // Okay, look at the command now.
1118 lastorder = order;
1119 if(receivedCmd[0] == 0x26) { // Received a REQUEST
1120 p_response = &responses[0]; order = 1;
1121 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
1122 p_response = &responses[0]; order = 6;
1123 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
1124 p_response = &responses[1]; order = 2;
1125 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
1126 p_response = &responses[2]; order = 20;
1127 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
1128 p_response = &responses[3]; order = 3;
1129 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
1130 p_response = &responses[4]; order = 30;
1131 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
1132 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
1133 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1134 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1135 p_response = NULL;
1136 } else if(receivedCmd[0] == 0x50) { // Received a HALT
1137
1138 if (tracing) {
1139 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1140 }
1141 p_response = NULL;
1142 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
1143 p_response = &responses[5]; order = 7;
1144 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
1145 if (tagType == 1 || tagType == 2) { // RATS not supported
1146 EmSend4bit(CARD_NACK_NA);
1147 p_response = NULL;
1148 } else {
1149 p_response = &responses[6]; order = 70;
1150 }
1151 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
1152 if (tracing) {
1153 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1154 }
1155 uint32_t nr = bytes_to_num(receivedCmd,4);
1156 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1157 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1158 } else {
1159 // Check for ISO 14443A-4 compliant commands, look at left nibble
1160 switch (receivedCmd[0]) {
1161
1162 case 0x0B:
1163 case 0x0A: { // IBlock (command)
1164 dynamic_response_info.response[0] = receivedCmd[0];
1165 dynamic_response_info.response[1] = 0x00;
1166 dynamic_response_info.response[2] = 0x90;
1167 dynamic_response_info.response[3] = 0x00;
1168 dynamic_response_info.response_n = 4;
1169 } break;
1170
1171 case 0x1A:
1172 case 0x1B: { // Chaining command
1173 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1174 dynamic_response_info.response_n = 2;
1175 } break;
1176
1177 case 0xaa:
1178 case 0xbb: {
1179 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1180 dynamic_response_info.response_n = 2;
1181 } break;
1182
1183 case 0xBA: { //
1184 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1185 dynamic_response_info.response_n = 2;
1186 } break;
1187
1188 case 0xCA:
1189 case 0xC2: { // Readers sends deselect command
1190 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1191 dynamic_response_info.response_n = 2;
1192 } break;
1193
1194 default: {
1195 // Never seen this command before
1196 if (tracing) {
1197 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1198 }
1199 Dbprintf("Received unknown command (len=%d):",len);
1200 Dbhexdump(len,receivedCmd,false);
1201 // Do not respond
1202 dynamic_response_info.response_n = 0;
1203 } break;
1204 }
1205
1206 if (dynamic_response_info.response_n > 0) {
1207 // Copy the CID from the reader query
1208 dynamic_response_info.response[1] = receivedCmd[1];
1209
1210 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1211 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1212 dynamic_response_info.response_n += 2;
1213
1214 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1215 Dbprintf("Error preparing tag response");
1216 if (tracing) {
1217 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1218 }
1219 break;
1220 }
1221 p_response = &dynamic_response_info;
1222 }
1223 }
1224
1225 // Count number of wakeups received after a halt
1226 if(order == 6 && lastorder == 5) { happened++; }
1227
1228 // Count number of other messages after a halt
1229 if(order != 6 && lastorder == 5) { happened2++; }
1230
1231 if(cmdsRecvd > 999) {
1232 DbpString("1000 commands later...");
1233 break;
1234 }
1235 cmdsRecvd++;
1236
1237 if (p_response != NULL) {
1238 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1239 // do the tracing for the previous reader request and this tag answer:
1240 uint8_t par[MAX_PARITY_SIZE];
1241 GetParity(p_response->response, p_response->response_n, par);
1242
1243 EmLogTrace(Uart.output,
1244 Uart.len,
1245 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1246 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1247 Uart.parity,
1248 p_response->response,
1249 p_response->response_n,
1250 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1251 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1252 par);
1253 }
1254
1255 if (!tracing) {
1256 Dbprintf("Trace Full. Simulation stopped.");
1257 break;
1258 }
1259 }
1260
1261 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1262 LED_A_OFF();
1263 BigBuf_free_keep_EM();
1264 }
1265
1266
1267 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1268 // of bits specified in the delay parameter.
1269 void PrepareDelayedTransfer(uint16_t delay)
1270 {
1271 uint8_t bitmask = 0;
1272 uint8_t bits_to_shift = 0;
1273 uint8_t bits_shifted = 0;
1274
1275 delay &= 0x07;
1276 if (delay) {
1277 for (uint16_t i = 0; i < delay; i++) {
1278 bitmask |= (0x01 << i);
1279 }
1280 ToSend[ToSendMax++] = 0x00;
1281 for (uint16_t i = 0; i < ToSendMax; i++) {
1282 bits_to_shift = ToSend[i] & bitmask;
1283 ToSend[i] = ToSend[i] >> delay;
1284 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1285 bits_shifted = bits_to_shift;
1286 }
1287 }
1288 }
1289
1290
1291 //-------------------------------------------------------------------------------------
1292 // Transmit the command (to the tag) that was placed in ToSend[].
1293 // Parameter timing:
1294 // if NULL: transfer at next possible time, taking into account
1295 // request guard time and frame delay time
1296 // if == 0: transfer immediately and return time of transfer
1297 // if != 0: delay transfer until time specified
1298 //-------------------------------------------------------------------------------------
1299 static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
1300 {
1301
1302 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1303
1304 uint32_t ThisTransferTime = 0;
1305
1306 if (timing) {
1307 if(*timing == 0) { // Measure time
1308 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1309 } else {
1310 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1311 }
1312 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1313 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1314 LastTimeProxToAirStart = *timing;
1315 } else {
1316 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1317 while(GetCountSspClk() < ThisTransferTime);
1318 LastTimeProxToAirStart = ThisTransferTime;
1319 }
1320
1321 // clear TXRDY
1322 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1323
1324 uint16_t c = 0;
1325 for(;;) {
1326 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1327 AT91C_BASE_SSC->SSC_THR = cmd[c];
1328 c++;
1329 if(c >= len) {
1330 break;
1331 }
1332 }
1333 }
1334
1335 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1336 }
1337
1338
1339 //-----------------------------------------------------------------------------
1340 // Prepare reader command (in bits, support short frames) to send to FPGA
1341 //-----------------------------------------------------------------------------
1342 void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
1343 {
1344 int i, j;
1345 int last;
1346 uint8_t b;
1347
1348 ToSendReset();
1349
1350 // Start of Communication (Seq. Z)
1351 ToSend[++ToSendMax] = SEC_Z;
1352 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1353 last = 0;
1354
1355 size_t bytecount = nbytes(bits);
1356 // Generate send structure for the data bits
1357 for (i = 0; i < bytecount; i++) {
1358 // Get the current byte to send
1359 b = cmd[i];
1360 size_t bitsleft = MIN((bits-(i*8)),8);
1361
1362 for (j = 0; j < bitsleft; j++) {
1363 if (b & 1) {
1364 // Sequence X
1365 ToSend[++ToSendMax] = SEC_X;
1366 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1367 last = 1;
1368 } else {
1369 if (last == 0) {
1370 // Sequence Z
1371 ToSend[++ToSendMax] = SEC_Z;
1372 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1373 } else {
1374 // Sequence Y
1375 ToSend[++ToSendMax] = SEC_Y;
1376 last = 0;
1377 }
1378 }
1379 b >>= 1;
1380 }
1381
1382 // Only transmit parity bit if we transmitted a complete byte
1383 if (j == 8) {
1384 // Get the parity bit
1385 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
1386 // Sequence X
1387 ToSend[++ToSendMax] = SEC_X;
1388 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1389 last = 1;
1390 } else {
1391 if (last == 0) {
1392 // Sequence Z
1393 ToSend[++ToSendMax] = SEC_Z;
1394 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1395 } else {
1396 // Sequence Y
1397 ToSend[++ToSendMax] = SEC_Y;
1398 last = 0;
1399 }
1400 }
1401 }
1402 }
1403
1404 // End of Communication: Logic 0 followed by Sequence Y
1405 if (last == 0) {
1406 // Sequence Z
1407 ToSend[++ToSendMax] = SEC_Z;
1408 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1409 } else {
1410 // Sequence Y
1411 ToSend[++ToSendMax] = SEC_Y;
1412 last = 0;
1413 }
1414 ToSend[++ToSendMax] = SEC_Y;
1415
1416 // Convert to length of command:
1417 ToSendMax++;
1418 }
1419
1420 //-----------------------------------------------------------------------------
1421 // Prepare reader command to send to FPGA
1422 //-----------------------------------------------------------------------------
1423 void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
1424 {
1425 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
1426 }
1427
1428
1429 //-----------------------------------------------------------------------------
1430 // Wait for commands from reader
1431 // Stop when button is pressed (return 1) or field was gone (return 2)
1432 // Or return 0 when command is captured
1433 //-----------------------------------------------------------------------------
1434 static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
1435 {
1436 *len = 0;
1437
1438 uint32_t timer = 0, vtime = 0;
1439 int analogCnt = 0;
1440 int analogAVG = 0;
1441
1442 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1443 // only, since we are receiving, not transmitting).
1444 // Signal field is off with the appropriate LED
1445 LED_D_OFF();
1446 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1447
1448 // Set ADC to read field strength
1449 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1450 AT91C_BASE_ADC->ADC_MR =
1451 ADC_MODE_PRESCALE(63) |
1452 ADC_MODE_STARTUP_TIME(1) |
1453 ADC_MODE_SAMPLE_HOLD_TIME(15);
1454 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1455 // start ADC
1456 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1457
1458 // Now run a 'software UART' on the stream of incoming samples.
1459 UartInit(received, parity);
1460
1461 // Clear RXRDY:
1462 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1463
1464 for(;;) {
1465 WDT_HIT();
1466
1467 if (BUTTON_PRESS()) return 1;
1468
1469 // test if the field exists
1470 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1471 analogCnt++;
1472 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1473 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1474 if (analogCnt >= 32) {
1475 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1476 vtime = GetTickCount();
1477 if (!timer) timer = vtime;
1478 // 50ms no field --> card to idle state
1479 if (vtime - timer > 50) return 2;
1480 } else
1481 if (timer) timer = 0;
1482 analogCnt = 0;
1483 analogAVG = 0;
1484 }
1485 }
1486
1487 // receive and test the miller decoding
1488 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1489 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1490 if(MillerDecoding(b, 0)) {
1491 *len = Uart.len;
1492 return 0;
1493 }
1494 }
1495
1496 }
1497 }
1498
1499
1500 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
1501 {
1502 uint8_t b;
1503 uint16_t i = 0;
1504 uint32_t ThisTransferTime;
1505
1506 // Modulate Manchester
1507 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1508
1509 // include correction bit if necessary
1510 if (Uart.parityBits & 0x01) {
1511 correctionNeeded = TRUE;
1512 }
1513 if(correctionNeeded) {
1514 // 1236, so correction bit needed
1515 i = 0;
1516 } else {
1517 i = 1;
1518 }
1519
1520 // clear receiving shift register and holding register
1521 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1522 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1523 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1524 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1525
1526 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1527 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1528 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1529 if (AT91C_BASE_SSC->SSC_RHR) break;
1530 }
1531
1532 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1533
1534 // Clear TXRDY:
1535 AT91C_BASE_SSC->SSC_THR = SEC_F;
1536
1537 // send cycle
1538 for(; i < respLen; ) {
1539 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1540 AT91C_BASE_SSC->SSC_THR = resp[i++];
1541 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1542 }
1543
1544 if(BUTTON_PRESS()) {
1545 break;
1546 }
1547 }
1548
1549 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1550 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
1551 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
1552 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1553 AT91C_BASE_SSC->SSC_THR = SEC_F;
1554 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1555 i++;
1556 }
1557 }
1558
1559 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1560
1561 return 0;
1562 }
1563
1564 int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1565 Code4bitAnswerAsTag(resp);
1566 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1567 // do the tracing for the previous reader request and this tag answer:
1568 uint8_t par[1];
1569 GetParity(&resp, 1, par);
1570 EmLogTrace(Uart.output,
1571 Uart.len,
1572 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1573 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1574 Uart.parity,
1575 &resp,
1576 1,
1577 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1578 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1579 par);
1580 return res;
1581 }
1582
1583 int EmSend4bit(uint8_t resp){
1584 return EmSend4bitEx(resp, false);
1585 }
1586
1587 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
1588 CodeIso14443aAsTagPar(resp, respLen, par);
1589 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1590 // do the tracing for the previous reader request and this tag answer:
1591 EmLogTrace(Uart.output,
1592 Uart.len,
1593 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1594 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1595 Uart.parity,
1596 resp,
1597 respLen,
1598 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1599 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1600 par);
1601 return res;
1602 }
1603
1604 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1605 uint8_t par[MAX_PARITY_SIZE];
1606 GetParity(resp, respLen, par);
1607 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
1608 }
1609
1610 int EmSendCmd(uint8_t *resp, uint16_t respLen){
1611 uint8_t par[MAX_PARITY_SIZE];
1612 GetParity(resp, respLen, par);
1613 return EmSendCmdExPar(resp, respLen, false, par);
1614 }
1615
1616 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
1617 return EmSendCmdExPar(resp, respLen, false, par);
1618 }
1619
1620 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1621 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
1622 {
1623 if (tracing) {
1624 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1625 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1626 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1627 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1628 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1629 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1630 reader_EndTime = tag_StartTime - exact_fdt;
1631 reader_StartTime = reader_EndTime - reader_modlen;
1632 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE)) {
1633 return FALSE;
1634 } else return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1635 } else {
1636 return TRUE;
1637 }
1638 }
1639
1640 //-----------------------------------------------------------------------------
1641 // Wait a certain time for tag response
1642 // If a response is captured return TRUE
1643 // If it takes too long return FALSE
1644 //-----------------------------------------------------------------------------
1645 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
1646 {
1647 uint32_t c;
1648
1649 // Set FPGA mode to "reader listen mode", no modulation (listen
1650 // only, since we are receiving, not transmitting).
1651 // Signal field is on with the appropriate LED
1652 LED_D_ON();
1653 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1654
1655 // Now get the answer from the card
1656 DemodInit(receivedResponse, receivedResponsePar);
1657
1658 // clear RXRDY:
1659 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1660
1661 c = 0;
1662 for(;;) {
1663 WDT_HIT();
1664
1665 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1666 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1667 if(ManchesterDecoding(b, offset, 0)) {
1668 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1669 return TRUE;
1670 } else if (c++ > iso14a_timeout) {
1671 return FALSE;
1672 }
1673 }
1674 }
1675 }
1676
1677 void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
1678 {
1679 CodeIso14443aBitsAsReaderPar(frame, bits, par);
1680
1681 // Send command to tag
1682 TransmitFor14443a(ToSend, ToSendMax, timing);
1683 if(trigger)
1684 LED_A_ON();
1685
1686 // Log reader command in trace buffer
1687 if (tracing) {
1688 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
1689 }
1690 }
1691
1692 void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
1693 {
1694 ReaderTransmitBitsPar(frame, len*8, par, timing);
1695 }
1696
1697 void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
1698 {
1699 // Generate parity and redirect
1700 uint8_t par[MAX_PARITY_SIZE];
1701 GetParity(frame, len/8, par);
1702 ReaderTransmitBitsPar(frame, len, par, timing);
1703 }
1704
1705 void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
1706 {
1707 // Generate parity and redirect
1708 uint8_t par[MAX_PARITY_SIZE];
1709 GetParity(frame, len, par);
1710 ReaderTransmitBitsPar(frame, len*8, par, timing);
1711 }
1712
1713 int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
1714 {
1715 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return FALSE;
1716 if (tracing) {
1717 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1718 }
1719 return Demod.len;
1720 }
1721
1722 int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
1723 {
1724 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
1725 if (tracing) {
1726 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1727 }
1728 return Demod.len;
1729 }
1730
1731 /* performs iso14443a anticollision procedure
1732 * fills the uid pointer unless NULL
1733 * fills resp_data unless NULL */
1734 int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr) {
1735 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1736 uint8_t sel_all[] = { 0x93,0x20 };
1737 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1738 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1739 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1740 uint8_t resp_par[MAX_PARITY_SIZE];
1741 byte_t uid_resp[4];
1742 size_t uid_resp_len;
1743
1744 uint8_t sak = 0x04; // cascade uid
1745 int cascade_level = 0;
1746 int len;
1747
1748 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1749 ReaderTransmitBitsPar(wupa,7,0, NULL);
1750
1751 // Receive the ATQA
1752 if(!ReaderReceive(resp, resp_par)) return 0;
1753
1754 if(p_hi14a_card) {
1755 memcpy(p_hi14a_card->atqa, resp, 2);
1756 p_hi14a_card->uidlen = 0;
1757 memset(p_hi14a_card->uid,0,10);
1758 }
1759
1760 // clear uid
1761 if (uid_ptr) {
1762 memset(uid_ptr,0,10);
1763 }
1764
1765 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1766 // which case we need to make a cascade 2 request and select - this is a long UID
1767 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1768 for(; sak & 0x04; cascade_level++) {
1769 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1770 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1771
1772 // SELECT_ALL
1773 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1774 if (!ReaderReceive(resp, resp_par)) return 0;
1775
1776 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1777 memset(uid_resp, 0, 4);
1778 uint16_t uid_resp_bits = 0;
1779 uint16_t collision_answer_offset = 0;
1780 // anti-collision-loop:
1781 while (Demod.collisionPos) {
1782 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1783 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1784 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1785 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1786 }
1787 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1788 uid_resp_bits++;
1789 // construct anticollosion command:
1790 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1791 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1792 sel_uid[2+i] = uid_resp[i];
1793 }
1794 collision_answer_offset = uid_resp_bits%8;
1795 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1796 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
1797 }
1798 // finally, add the last bits and BCC of the UID
1799 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1800 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1801 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1802 }
1803
1804 } else { // no collision, use the response to SELECT_ALL as current uid
1805 memcpy(uid_resp, resp, 4);
1806 }
1807 uid_resp_len = 4;
1808
1809 // calculate crypto UID. Always use last 4 Bytes.
1810 if(cuid_ptr) {
1811 *cuid_ptr = bytes_to_num(uid_resp, 4);
1812 }
1813
1814 // Construct SELECT UID command
1815 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1816 memcpy(sel_uid+2, uid_resp, 4); // the UID
1817 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1818 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1819 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1820
1821 // Receive the SAK
1822 if (!ReaderReceive(resp, resp_par)) return 0;
1823 sak = resp[0];
1824
1825 // Test if more parts of the uid are coming
1826 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1827 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1828 // http://www.nxp.com/documents/application_note/AN10927.pdf
1829 uid_resp[0] = uid_resp[1];
1830 uid_resp[1] = uid_resp[2];
1831 uid_resp[2] = uid_resp[3];
1832
1833 uid_resp_len = 3;
1834 }
1835
1836 if(uid_ptr) {
1837 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1838 }
1839
1840 if(p_hi14a_card) {
1841 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1842 p_hi14a_card->uidlen += uid_resp_len;
1843 }
1844 }
1845
1846 if(p_hi14a_card) {
1847 p_hi14a_card->sak = sak;
1848 p_hi14a_card->ats_len = 0;
1849 }
1850
1851 // non iso14443a compliant tag
1852 if( (sak & 0x20) == 0) return 2;
1853
1854 // Request for answer to select
1855 AppendCrc14443a(rats, 2);
1856 ReaderTransmit(rats, sizeof(rats), NULL);
1857
1858 if (!(len = ReaderReceive(resp, resp_par))) return 0;
1859
1860
1861 if(p_hi14a_card) {
1862 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1863 p_hi14a_card->ats_len = len;
1864 }
1865
1866 // reset the PCB block number
1867 iso14_pcb_blocknum = 0;
1868 return 1;
1869 }
1870
1871 void iso14443a_setup(uint8_t fpga_minor_mode) {
1872 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1873 // Set up the synchronous serial port
1874 FpgaSetupSsc();
1875 // connect Demodulated Signal to ADC:
1876 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1877
1878 // Signal field is on with the appropriate LED
1879 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1880 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1881 LED_D_ON();
1882 } else {
1883 LED_D_OFF();
1884 }
1885 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
1886
1887 // Start the timer
1888 StartCountSspClk();
1889
1890 DemodReset();
1891 UartReset();
1892 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1893 iso14a_set_timeout(1050); // 10ms default
1894 }
1895
1896 int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1897 uint8_t parity[MAX_PARITY_SIZE];
1898 uint8_t real_cmd[cmd_len+4];
1899 real_cmd[0] = 0x0a; //I-Block
1900 // put block number into the PCB
1901 real_cmd[0] |= iso14_pcb_blocknum;
1902 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1903 memcpy(real_cmd+2, cmd, cmd_len);
1904 AppendCrc14443a(real_cmd,cmd_len+2);
1905
1906 ReaderTransmit(real_cmd, cmd_len+4, NULL);
1907 size_t len = ReaderReceive(data, parity);
1908 uint8_t *data_bytes = (uint8_t *) data;
1909 if (!len)
1910 return 0; //DATA LINK ERROR
1911 // if we received an I- or R(ACK)-Block with a block number equal to the
1912 // current block number, toggle the current block number
1913 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1914 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1915 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1916 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1917 {
1918 iso14_pcb_blocknum ^= 1;
1919 }
1920
1921 return len;
1922 }
1923
1924 //-----------------------------------------------------------------------------
1925 // Read an ISO 14443a tag. Send out commands and store answers.
1926 //
1927 //-----------------------------------------------------------------------------
1928 void ReaderIso14443a(UsbCommand *c)
1929 {
1930 iso14a_command_t param = c->arg[0];
1931 uint8_t *cmd = c->d.asBytes;
1932 size_t len = c->arg[1];
1933 size_t lenbits = c->arg[2];
1934 uint32_t arg0 = 0;
1935 byte_t buf[USB_CMD_DATA_SIZE];
1936 uint8_t par[MAX_PARITY_SIZE];
1937
1938 if(param & ISO14A_CONNECT) {
1939 iso14a_clear_trace();
1940 }
1941
1942 iso14a_set_tracing(TRUE);
1943
1944 if(param & ISO14A_REQUEST_TRIGGER) {
1945 iso14a_set_trigger(TRUE);
1946 }
1947
1948 if(param & ISO14A_CONNECT) {
1949 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
1950 if(!(param & ISO14A_NO_SELECT)) {
1951 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1952 arg0 = iso14443a_select_card(NULL,card,NULL);
1953 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1954 }
1955 }
1956
1957 if(param & ISO14A_SET_TIMEOUT) {
1958 iso14a_set_timeout(c->arg[2]);
1959 }
1960
1961 if(param & ISO14A_APDU) {
1962 arg0 = iso14_apdu(cmd, len, buf);
1963 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1964 }
1965
1966 if(param & ISO14A_RAW) {
1967 if(param & ISO14A_APPEND_CRC) {
1968 AppendCrc14443a(cmd,len);
1969 len += 2;
1970 if (lenbits) lenbits += 16;
1971 }
1972 if(lenbits>0) {
1973 GetParity(cmd, lenbits/8, par);
1974 ReaderTransmitBitsPar(cmd, lenbits, par, NULL);
1975 } else {
1976 ReaderTransmit(cmd,len, NULL);
1977 }
1978 arg0 = ReaderReceive(buf, par);
1979 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1980 }
1981
1982 if(param & ISO14A_REQUEST_TRIGGER) {
1983 iso14a_set_trigger(FALSE);
1984 }
1985
1986 if(param & ISO14A_NO_DISCONNECT) {
1987 return;
1988 }
1989
1990 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1991 LEDsoff();
1992 }
1993
1994
1995 // Determine the distance between two nonces.
1996 // Assume that the difference is small, but we don't know which is first.
1997 // Therefore try in alternating directions.
1998 int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
1999
2000 uint16_t i;
2001 uint32_t nttmp1, nttmp2;
2002
2003 if (nt1 == nt2) return 0;
2004
2005 nttmp1 = nt1;
2006 nttmp2 = nt2;
2007
2008 for (i = 1; i < 32768; i++) {
2009 nttmp1 = prng_successor(nttmp1, 1);
2010 if (nttmp1 == nt2) return i;
2011 nttmp2 = prng_successor(nttmp2, 1);
2012 if (nttmp2 == nt1) return -i;
2013 }
2014
2015 return(-99999); // either nt1 or nt2 are invalid nonces
2016 }
2017
2018
2019 //-----------------------------------------------------------------------------
2020 // Recover several bits of the cypher stream. This implements (first stages of)
2021 // the algorithm described in "The Dark Side of Security by Obscurity and
2022 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2023 // (article by Nicolas T. Courtois, 2009)
2024 //-----------------------------------------------------------------------------
2025 void ReaderMifare(bool first_try)
2026 {
2027 // Mifare AUTH
2028 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2029 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2030 static uint8_t mf_nr_ar3;
2031
2032 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE];
2033 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE];
2034
2035 // free eventually allocated BigBuf memory. We want all for tracing.
2036 BigBuf_free();
2037
2038 iso14a_clear_trace();
2039 iso14a_set_tracing(TRUE);
2040
2041 byte_t nt_diff = 0;
2042 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2043 static byte_t par_low = 0;
2044 bool led_on = TRUE;
2045 uint8_t uid[10] ={0};
2046 uint32_t cuid;
2047
2048 uint32_t nt = 0;
2049 uint32_t previous_nt = 0;
2050 static uint32_t nt_attacked = 0;
2051 byte_t par_list[8] = {0x00};
2052 byte_t ks_list[8] = {0x00};
2053
2054 static uint32_t sync_time;
2055 static uint32_t sync_cycles;
2056 int catch_up_cycles = 0;
2057 int last_catch_up = 0;
2058 uint16_t consecutive_resyncs = 0;
2059 int isOK = 0;
2060
2061 if (first_try) {
2062 mf_nr_ar3 = 0;
2063 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2064 sync_time = GetCountSspClk() & 0xfffffff8;
2065 sync_cycles = 65536; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
2066 nt_attacked = 0;
2067 nt = 0;
2068 par[0] = 0;
2069 }
2070 else {
2071 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
2072 mf_nr_ar3++;
2073 mf_nr_ar[3] = mf_nr_ar3;
2074 par[0] = par_low;
2075 }
2076
2077 LED_A_ON();
2078 LED_B_OFF();
2079 LED_C_OFF();
2080
2081
2082 for(uint16_t i = 0; TRUE; i++) {
2083
2084 WDT_HIT();
2085
2086 // Test if the action was cancelled
2087 if(BUTTON_PRESS()) {
2088 break;
2089 }
2090
2091 LED_C_ON();
2092
2093 if(!iso14443a_select_card(uid, NULL, &cuid)) {
2094 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
2095 continue;
2096 }
2097
2098 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
2099 catch_up_cycles = 0;
2100
2101 // if we missed the sync time already, advance to the next nonce repeat
2102 while(GetCountSspClk() > sync_time) {
2103 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2104 }
2105
2106 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2107 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2108
2109 // Receive the (4 Byte) "random" nonce
2110 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2111 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2112 continue;
2113 }
2114
2115 previous_nt = nt;
2116 nt = bytes_to_num(receivedAnswer, 4);
2117
2118 // Transmit reader nonce with fake par
2119 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2120
2121 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2122 int nt_distance = dist_nt(previous_nt, nt);
2123 if (nt_distance == 0) {
2124 nt_attacked = nt;
2125 }
2126 else {
2127 if (nt_distance == -99999) { // invalid nonce received, try again
2128 continue;
2129 }
2130 sync_cycles = (sync_cycles - nt_distance);
2131 if (MF_DBGLEVEL >= 3) Dbprintf("calibrating in cycle %d. nt_distance=%d, Sync_cycles: %d\n", i, nt_distance, sync_cycles);
2132 continue;
2133 }
2134 }
2135
2136 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2137 catch_up_cycles = -dist_nt(nt_attacked, nt);
2138 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2139 catch_up_cycles = 0;
2140 continue;
2141 }
2142 if (catch_up_cycles == last_catch_up) {
2143 consecutive_resyncs++;
2144 }
2145 else {
2146 last_catch_up = catch_up_cycles;
2147 consecutive_resyncs = 0;
2148 }
2149 if (consecutive_resyncs < 3) {
2150 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
2151 }
2152 else {
2153 sync_cycles = sync_cycles + catch_up_cycles;
2154 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
2155 }
2156 continue;
2157 }
2158
2159 consecutive_resyncs = 0;
2160
2161 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2162 if (ReaderReceive(receivedAnswer, receivedAnswerPar))
2163 {
2164 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2165
2166 if (nt_diff == 0)
2167 {
2168 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2169 }
2170
2171 led_on = !led_on;
2172 if(led_on) LED_B_ON(); else LED_B_OFF();
2173
2174 par_list[nt_diff] = SwapBits(par[0], 8);
2175 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2176
2177 // Test if the information is complete
2178 if (nt_diff == 0x07) {
2179 isOK = 1;
2180 break;
2181 }
2182
2183 nt_diff = (nt_diff + 1) & 0x07;
2184 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2185 par[0] = par_low;
2186 } else {
2187 if (nt_diff == 0 && first_try)
2188 {
2189 par[0]++;
2190 } else {
2191 par[0] = ((par[0] & 0x1F) + 1) | par_low;
2192 }
2193 }
2194 }
2195
2196
2197 mf_nr_ar[3] &= 0x1F;
2198
2199 byte_t buf[28];
2200 memcpy(buf + 0, uid, 4);
2201 num_to_bytes(nt, 4, buf + 4);
2202 memcpy(buf + 8, par_list, 8);
2203 memcpy(buf + 16, ks_list, 8);
2204 memcpy(buf + 24, mf_nr_ar, 4);
2205
2206 cmd_send(CMD_ACK,isOK,0,0,buf,28);
2207
2208 // Thats it...
2209 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2210 LEDsoff();
2211
2212 iso14a_set_tracing(FALSE);
2213 }
2214
2215 /**
2216 *MIFARE 1K simulate.
2217 *
2218 *@param flags :
2219 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2220 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2221 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2222 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2223 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2224 */
2225 void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
2226 {
2227 int cardSTATE = MFEMUL_NOFIELD;
2228 int _7BUID = 0;
2229 int vHf = 0; // in mV
2230 int res;
2231 uint32_t selTimer = 0;
2232 uint32_t authTimer = 0;
2233 uint16_t len = 0;
2234 uint8_t cardWRBL = 0;
2235 uint8_t cardAUTHSC = 0;
2236 uint8_t cardAUTHKEY = 0xff; // no authentication
2237 uint32_t cardRr = 0;
2238 uint32_t cuid = 0;
2239 //uint32_t rn_enc = 0;
2240 uint32_t ans = 0;
2241 uint32_t cardINTREG = 0;
2242 uint8_t cardINTBLOCK = 0;
2243 struct Crypto1State mpcs = {0, 0};
2244 struct Crypto1State *pcs;
2245 pcs = &mpcs;
2246 uint32_t numReads = 0;//Counts numer of times reader read a block
2247 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2248 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE];
2249 uint8_t response[MAX_MIFARE_FRAME_SIZE];
2250 uint8_t response_par[MAX_MIFARE_PARITY_SIZE];
2251
2252 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2253 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2254 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2255 uint8_t rSAK[] = {0x08, 0xb6, 0xdd};
2256 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
2257
2258 uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};
2259 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
2260
2261 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
2262 // This can be used in a reader-only attack.
2263 // (it can also be retrieved via 'hf 14a list', but hey...
2264 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0};
2265 uint8_t ar_nr_collected = 0;
2266
2267 // free eventually allocated BigBuf memory but keep Emulator Memory
2268 BigBuf_free_keep_EM();
2269
2270 // clear trace
2271 iso14a_clear_trace();
2272 iso14a_set_tracing(TRUE);
2273
2274 // Authenticate response - nonce
2275 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
2276
2277 //-- Determine the UID
2278 // Can be set from emulator memory, incoming data
2279 // and can be 7 or 4 bytes long
2280 if (flags & FLAG_4B_UID_IN_DATA)
2281 {
2282 // 4B uid comes from data-portion of packet
2283 memcpy(rUIDBCC1,datain,4);
2284 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2285
2286 } else if (flags & FLAG_7B_UID_IN_DATA) {
2287 // 7B uid comes from data-portion of packet
2288 memcpy(&rUIDBCC1[1],datain,3);
2289 memcpy(rUIDBCC2, datain+3, 4);
2290 _7BUID = true;
2291 } else {
2292 // get UID from emul memory
2293 emlGetMemBt(receivedCmd, 7, 1);
2294 _7BUID = !(receivedCmd[0] == 0x00);
2295 if (!_7BUID) { // ---------- 4BUID
2296 emlGetMemBt(rUIDBCC1, 0, 4);
2297 } else { // ---------- 7BUID
2298 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2299 emlGetMemBt(rUIDBCC2, 3, 4);
2300 }
2301 }
2302
2303 /*
2304 * Regardless of what method was used to set the UID, set fifth byte and modify
2305 * the ATQA for 4 or 7-byte UID
2306 */
2307 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2308 if (_7BUID) {
2309 rATQA[0] = 0x44;
2310 rUIDBCC1[0] = 0x88;
2311 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2312 }
2313
2314 // We need to listen to the high-frequency, peak-detected path.
2315 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2316
2317
2318 if (MF_DBGLEVEL >= 1) {
2319 if (!_7BUID) {
2320 Dbprintf("4B UID: %02x%02x%02x%02x",
2321 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
2322 } else {
2323 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2324 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2325 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
2326 }
2327 }
2328
2329 bool finished = FALSE;
2330 while (!BUTTON_PRESS() && !finished) {
2331 WDT_HIT();
2332
2333 // find reader field
2334 if (cardSTATE == MFEMUL_NOFIELD) {
2335 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
2336 if (vHf > MF_MINFIELDV) {
2337 cardSTATE_TO_IDLE();
2338 LED_A_ON();
2339 }
2340 }
2341 if(cardSTATE == MFEMUL_NOFIELD) continue;
2342
2343 //Now, get data
2344
2345 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
2346 if (res == 2) { //Field is off!
2347 cardSTATE = MFEMUL_NOFIELD;
2348 LEDsoff();
2349 continue;
2350 } else if (res == 1) {
2351 break; //return value 1 means button press
2352 }
2353
2354 // REQ or WUP request in ANY state and WUP in HALTED state
2355 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2356 selTimer = GetTickCount();
2357 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2358 cardSTATE = MFEMUL_SELECT1;
2359
2360 // init crypto block
2361 LED_B_OFF();
2362 LED_C_OFF();
2363 crypto1_destroy(pcs);
2364 cardAUTHKEY = 0xff;
2365 continue;
2366 }
2367
2368 switch (cardSTATE) {
2369 case MFEMUL_NOFIELD:
2370 case MFEMUL_HALTED:
2371 case MFEMUL_IDLE:{
2372 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2373 break;
2374 }
2375 case MFEMUL_SELECT1:{
2376 // select all
2377 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
2378 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
2379 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
2380 break;
2381 }
2382
2383 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2384 {
2385 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2386 }
2387 // select card
2388 if (len == 9 &&
2389 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2390 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
2391 cuid = bytes_to_num(rUIDBCC1, 4);
2392 if (!_7BUID) {
2393 cardSTATE = MFEMUL_WORK;
2394 LED_B_ON();
2395 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2396 break;
2397 } else {
2398 cardSTATE = MFEMUL_SELECT2;
2399 }
2400 }
2401 break;
2402 }
2403 case MFEMUL_AUTH1:{
2404 if( len != 8)
2405 {
2406 cardSTATE_TO_IDLE();
2407 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2408 break;
2409 }
2410
2411 uint32_t ar = bytes_to_num(receivedCmd, 4);
2412 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
2413
2414 //Collect AR/NR
2415 if(ar_nr_collected < 2){
2416 if(ar_nr_responses[2] != ar)
2417 {// Avoid duplicates... probably not necessary, ar should vary.
2418 ar_nr_responses[ar_nr_collected*4] = cuid;
2419 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2420 ar_nr_responses[ar_nr_collected*4+2] = ar;
2421 ar_nr_responses[ar_nr_collected*4+3] = nr;
2422 ar_nr_collected++;
2423 }
2424 }
2425
2426 // --- crypto
2427 crypto1_word(pcs, ar , 1);
2428 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2429
2430 // test if auth OK
2431 if (cardRr != prng_successor(nonce, 64)){
2432 if (MF_DBGLEVEL >= 2) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2433 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2434 cardRr, prng_successor(nonce, 64));
2435 // Shouldn't we respond anything here?
2436 // Right now, we don't nack or anything, which causes the
2437 // reader to do a WUPA after a while. /Martin
2438 // -- which is the correct response. /piwi
2439 cardSTATE_TO_IDLE();
2440 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2441 break;
2442 }
2443
2444 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2445
2446 num_to_bytes(ans, 4, rAUTH_AT);
2447 // --- crypto
2448 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2449 LED_C_ON();
2450 cardSTATE = MFEMUL_WORK;
2451 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2452 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2453 GetTickCount() - authTimer);
2454 break;
2455 }
2456 case MFEMUL_SELECT2:{
2457 if (!len) {
2458 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2459 break;
2460 }
2461 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
2462 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2463 break;
2464 }
2465
2466 // select 2 card
2467 if (len == 9 &&
2468 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2469 EmSendCmd(rSAK, sizeof(rSAK));
2470 cuid = bytes_to_num(rUIDBCC2, 4);
2471 cardSTATE = MFEMUL_WORK;
2472 LED_B_ON();
2473 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2474 break;
2475 }
2476
2477 // i guess there is a command). go into the work state.
2478 if (len != 4) {
2479 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2480 break;
2481 }
2482 cardSTATE = MFEMUL_WORK;
2483 //goto lbWORK;
2484 //intentional fall-through to the next case-stmt
2485 }
2486
2487 case MFEMUL_WORK:{
2488 if (len == 0) {
2489 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2490 break;
2491 }
2492
2493 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2494
2495 if(encrypted_data) {
2496 // decrypt seqence
2497 mf_crypto1_decrypt(pcs, receivedCmd, len);
2498 }
2499
2500 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2501 authTimer = GetTickCount();
2502 cardAUTHSC = receivedCmd[1] / 4; // received block num
2503 cardAUTHKEY = receivedCmd[0] - 0x60;
2504 crypto1_destroy(pcs);//Added by martin
2505 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
2506
2507 if (!encrypted_data) { // first authentication
2508 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2509
2510 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2511 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
2512 } else { // nested authentication
2513 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2514 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
2515 num_to_bytes(ans, 4, rAUTH_AT);
2516 }
2517
2518 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2519 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2520 cardSTATE = MFEMUL_AUTH1;
2521 break;
2522 }
2523
2524 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2525 // BUT... ACK --> NACK
2526 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2527 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2528 break;
2529 }
2530
2531 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2532 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2533 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2534 break;
2535 }
2536
2537 if(len != 4) {
2538 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2539 break;
2540 }
2541
2542 if(receivedCmd[0] == 0x30 // read block
2543 || receivedCmd[0] == 0xA0 // write block
2544 || receivedCmd[0] == 0xC0 // inc
2545 || receivedCmd[0] == 0xC1 // dec
2546 || receivedCmd[0] == 0xC2 // restore
2547 || receivedCmd[0] == 0xB0) { // transfer
2548 if (receivedCmd[1] >= 16 * 4) {
2549 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2550 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2551 break;
2552 }
2553
2554 if (receivedCmd[1] / 4 != cardAUTHSC) {
2555 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2556 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
2557 break;
2558 }
2559 }
2560 // read block
2561 if (receivedCmd[0] == 0x30) {
2562 if (MF_DBGLEVEL >= 4) {
2563 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2564 }
2565 emlGetMem(response, receivedCmd[1], 1);
2566 AppendCrc14443a(response, 16);
2567 mf_crypto1_encrypt(pcs, response, 18, response_par);
2568 EmSendCmdPar(response, 18, response_par);
2569 numReads++;
2570 if(exitAfterNReads > 0 && numReads == exitAfterNReads) {
2571 Dbprintf("%d reads done, exiting", numReads);
2572 finished = true;
2573 }
2574 break;
2575 }
2576 // write block
2577 if (receivedCmd[0] == 0xA0) {
2578 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
2579 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2580 cardSTATE = MFEMUL_WRITEBL2;
2581 cardWRBL = receivedCmd[1];
2582 break;
2583 }
2584 // increment, decrement, restore
2585 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
2586 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2587 if (emlCheckValBl(receivedCmd[1])) {
2588 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
2589 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2590 break;
2591 }
2592 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2593 if (receivedCmd[0] == 0xC1)
2594 cardSTATE = MFEMUL_INTREG_INC;
2595 if (receivedCmd[0] == 0xC0)
2596 cardSTATE = MFEMUL_INTREG_DEC;
2597 if (receivedCmd[0] == 0xC2)
2598 cardSTATE = MFEMUL_INTREG_REST;
2599 cardWRBL = receivedCmd[1];
2600 break;
2601 }
2602 // transfer
2603 if (receivedCmd[0] == 0xB0) {
2604 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2605 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2606 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2607 else
2608 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2609 break;
2610 }
2611 // halt
2612 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
2613 LED_B_OFF();
2614 LED_C_OFF();
2615 cardSTATE = MFEMUL_HALTED;
2616 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
2617 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2618 break;
2619 }
2620 // RATS
2621 if (receivedCmd[0] == 0xe0) {//RATS
2622 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2623 break;
2624 }
2625 // command not allowed
2626 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2627 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2628 break;
2629 }
2630 case MFEMUL_WRITEBL2:{
2631 if (len == 18){
2632 mf_crypto1_decrypt(pcs, receivedCmd, len);
2633 emlSetMem(receivedCmd, cardWRBL, 1);
2634 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2635 cardSTATE = MFEMUL_WORK;
2636 } else {
2637 cardSTATE_TO_IDLE();
2638 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2639 }
2640 break;
2641 }
2642
2643 case MFEMUL_INTREG_INC:{
2644 mf_crypto1_decrypt(pcs, receivedCmd, len);
2645 memcpy(&ans, receivedCmd, 4);
2646 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2647 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2648 cardSTATE_TO_IDLE();
2649 break;
2650 }
2651 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2652 cardINTREG = cardINTREG + ans;
2653 cardSTATE = MFEMUL_WORK;
2654 break;
2655 }
2656 case MFEMUL_INTREG_DEC:{
2657 mf_crypto1_decrypt(pcs, receivedCmd, len);
2658 memcpy(&ans, receivedCmd, 4);
2659 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2660 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2661 cardSTATE_TO_IDLE();
2662 break;
2663 }
2664 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2665 cardINTREG = cardINTREG - ans;
2666 cardSTATE = MFEMUL_WORK;
2667 break;
2668 }
2669 case MFEMUL_INTREG_REST:{
2670 mf_crypto1_decrypt(pcs, receivedCmd, len);
2671 memcpy(&ans, receivedCmd, 4);
2672 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2673 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2674 cardSTATE_TO_IDLE();
2675 break;
2676 }
2677 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2678 cardSTATE = MFEMUL_WORK;
2679 break;
2680 }
2681 }
2682 }
2683
2684 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2685 LEDsoff();
2686
2687 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2688 {
2689 //May just aswell send the collected ar_nr in the response aswell
2690 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,0,0,&ar_nr_responses,ar_nr_collected*4*4);
2691 }
2692
2693 if(flags & FLAG_NR_AR_ATTACK)
2694 {
2695 if(ar_nr_collected > 1) {
2696 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
2697 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
2698 ar_nr_responses[0], // UID
2699 ar_nr_responses[1], //NT
2700 ar_nr_responses[2], //AR1
2701 ar_nr_responses[3], //NR1
2702 ar_nr_responses[6], //AR2
2703 ar_nr_responses[7] //NR2
2704 );
2705 } else {
2706 Dbprintf("Failed to obtain two AR/NR pairs!");
2707 if(ar_nr_collected >0) {
2708 Dbprintf("Only got these: UID=%08x, nonce=%08x, AR1=%08x, NR1=%08x",
2709 ar_nr_responses[0], // UID
2710 ar_nr_responses[1], //NT
2711 ar_nr_responses[2], //AR1
2712 ar_nr_responses[3] //NR1
2713 );
2714 }
2715 }
2716 }
2717 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, traceLen);
2718
2719 }
2720
2721
2722
2723 //-----------------------------------------------------------------------------
2724 // MIFARE sniffer.
2725 //
2726 //-----------------------------------------------------------------------------
2727 void RAMFUNC SniffMifare(uint8_t param) {
2728 // param:
2729 // bit 0 - trigger from first card answer
2730 // bit 1 - trigger from first reader 7-bit request
2731
2732 // C(red) A(yellow) B(green)
2733 LEDsoff();
2734 // init trace buffer
2735 iso14a_clear_trace();
2736 iso14a_set_tracing(TRUE);
2737
2738 // The command (reader -> tag) that we're receiving.
2739 // The length of a received command will in most cases be no more than 18 bytes.
2740 // So 32 should be enough!
2741 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2742 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
2743 // The response (tag -> reader) that we're receiving.
2744 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
2745 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
2746
2747 // As we receive stuff, we copy it from receivedCmd or receivedResponse
2748 // into trace, along with its length and other annotations.
2749 //uint8_t *trace = (uint8_t *)BigBuf;
2750
2751 // free eventually allocated BigBuf memory
2752 BigBuf_free();
2753 // allocate the DMA buffer, used to stream samples from the FPGA
2754 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
2755 uint8_t *data = dmaBuf;
2756 uint8_t previous_data = 0;
2757 int maxDataLen = 0;
2758 int dataLen = 0;
2759 bool ReaderIsActive = FALSE;
2760 bool TagIsActive = FALSE;
2761
2762 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2763
2764 // Set up the demodulator for tag -> reader responses.
2765 DemodInit(receivedResponse, receivedResponsePar);
2766
2767 // Set up the demodulator for the reader -> tag commands
2768 UartInit(receivedCmd, receivedCmdPar);
2769
2770 // Setup for the DMA.
2771 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2772
2773 LED_D_OFF();
2774
2775 // init sniffer
2776 MfSniffInit();
2777
2778 // And now we loop, receiving samples.
2779 for(uint32_t sniffCounter = 0; TRUE; ) {
2780
2781 if(BUTTON_PRESS()) {
2782 DbpString("cancelled by button");
2783 break;
2784 }
2785
2786 LED_A_ON();
2787 WDT_HIT();
2788
2789 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2790 // check if a transaction is completed (timeout after 2000ms).
2791 // if yes, stop the DMA transfer and send what we have so far to the client
2792 if (MfSniffSend(2000)) {
2793 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2794 sniffCounter = 0;
2795 data = dmaBuf;
2796 maxDataLen = 0;
2797 ReaderIsActive = FALSE;
2798 TagIsActive = FALSE;
2799 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2800 }
2801 }
2802
2803 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2804 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2805 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2806 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2807 } else {
2808 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
2809 }
2810 // test for length of buffer
2811 if(dataLen > maxDataLen) { // we are more behind than ever...
2812 maxDataLen = dataLen;
2813 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
2814 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
2815 break;
2816 }
2817 }
2818 if(dataLen < 1) continue;
2819
2820 // primary buffer was stopped ( <-- we lost data!
2821 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2822 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2823 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
2824 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
2825 }
2826 // secondary buffer sets as primary, secondary buffer was stopped
2827 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2828 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
2829 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2830 }
2831
2832 LED_A_OFF();
2833
2834 if (sniffCounter & 0x01) {
2835
2836 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2837 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2838 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2839 LED_C_INV();
2840 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
2841
2842 /* And ready to receive another command. */
2843 UartReset();
2844
2845 /* And also reset the demod code */
2846 DemodReset();
2847 }
2848 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2849 }
2850
2851 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2852 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2853 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2854 LED_C_INV();
2855
2856 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
2857
2858 // And ready to receive another response.
2859 DemodReset();
2860 }
2861 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2862 }
2863 }
2864
2865 previous_data = *data;
2866 sniffCounter++;
2867 data++;
2868 if(data == dmaBuf + DMA_BUFFER_SIZE) {
2869 data = dmaBuf;
2870 }
2871
2872 } // main cycle
2873
2874 DbpString("COMMAND FINISHED");
2875
2876 FpgaDisableSscDma();
2877 MfSniffEnd();
2878
2879 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
2880 LEDsoff();
2881 }
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