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[proxmark3-svn] / armsrc / iso14443a.c
1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12
13 #include "../include/proxmark3.h"
14 #include "apps.h"
15 #include "util.h"
16 #include "string.h"
17 #include "../common/cmd.h"
18 #include "../common/iso14443crc.h"
19 #include "iso14443a.h"
20 #include "crapto1.h"
21 #include "mifareutil.h"
22
23 static uint32_t iso14a_timeout;
24 uint8_t *trace = (uint8_t *) BigBuf+TRACE_OFFSET;
25 int rsamples = 0;
26 int traceLen = 0;
27 int tracing = TRUE;
28 uint8_t trigger = 0;
29 // the block number for the ISO14443-4 PCB
30 static uint8_t iso14_pcb_blocknum = 0;
31
32 //
33 // ISO14443 timing:
34 //
35 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
36 #define REQUEST_GUARD_TIME (7000/16 + 1)
37 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
38 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
39 // bool LastCommandWasRequest = FALSE;
40
41 //
42 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
43 //
44 // When the PM acts as reader and is receiving tag data, it takes
45 // 3 ticks delay in the AD converter
46 // 16 ticks until the modulation detector completes and sets curbit
47 // 8 ticks until bit_to_arm is assigned from curbit
48 // 8*16 ticks for the transfer from FPGA to ARM
49 // 4*16 ticks until we measure the time
50 // - 8*16 ticks because we measure the time of the previous transfer
51 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
52
53 // When the PM acts as a reader and is sending, it takes
54 // 4*16 ticks until we can write data to the sending hold register
55 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
56 // 8 ticks until the first transfer starts
57 // 8 ticks later the FPGA samples the data
58 // 1 tick to assign mod_sig_coil
59 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
60
61 // When the PM acts as tag and is receiving it takes
62 // 2 ticks delay in the RF part (for the first falling edge),
63 // 3 ticks for the A/D conversion,
64 // 8 ticks on average until the start of the SSC transfer,
65 // 8 ticks until the SSC samples the first data
66 // 7*16 ticks to complete the transfer from FPGA to ARM
67 // 8 ticks until the next ssp_clk rising edge
68 // 4*16 ticks until we measure the time
69 // - 8*16 ticks because we measure the time of the previous transfer
70 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
71
72 // The FPGA will report its internal sending delay in
73 uint16_t FpgaSendQueueDelay;
74 // the 5 first bits are the number of bits buffered in mod_sig_buf
75 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
76 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
77
78 // When the PM acts as tag and is sending, it takes
79 // 4*16 ticks until we can write data to the sending hold register
80 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
81 // 8 ticks until the first transfer starts
82 // 8 ticks later the FPGA samples the data
83 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
84 // + 1 tick to assign mod_sig_coil
85 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
86
87 // When the PM acts as sniffer and is receiving tag data, it takes
88 // 3 ticks A/D conversion
89 // 14 ticks to complete the modulation detection
90 // 8 ticks (on average) until the result is stored in to_arm
91 // + the delays in transferring data - which is the same for
92 // sniffing reader and tag data and therefore not relevant
93 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
94
95 // When the PM acts as sniffer and is receiving reader data, it takes
96 // 2 ticks delay in analogue RF receiver (for the falling edge of the
97 // start bit, which marks the start of the communication)
98 // 3 ticks A/D conversion
99 // 8 ticks on average until the data is stored in to_arm.
100 // + the delays in transferring data - which is the same for
101 // sniffing reader and tag data and therefore not relevant
102 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
103
104 //variables used for timing purposes:
105 //these are in ssp_clk cycles:
106 uint32_t NextTransferTime;
107 uint32_t LastTimeProxToAirStart;
108 uint32_t LastProxToAirDuration;
109
110
111
112 // CARD TO READER - manchester
113 // Sequence D: 11110000 modulation with subcarrier during first half
114 // Sequence E: 00001111 modulation with subcarrier during second half
115 // Sequence F: 00000000 no modulation with subcarrier
116 // READER TO CARD - miller
117 // Sequence X: 00001100 drop after half a period
118 // Sequence Y: 00000000 no drop
119 // Sequence Z: 11000000 drop at start
120 #define SEC_D 0xf0
121 #define SEC_E 0x0f
122 #define SEC_F 0x00
123 #define SEC_X 0x0c
124 #define SEC_Y 0x00
125 #define SEC_Z 0xc0
126
127 const uint8_t OddByteParity[256] = {
128 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
129 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
130 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
131 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
132 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
133 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
134 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
135 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
136 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
137 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
138 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
139 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
140 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
141 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
142 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
143 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
144 };
145
146
147 void iso14a_set_trigger(bool enable) {
148 trigger = enable;
149 }
150
151 void iso14a_clear_trace() {
152 memset(trace, 0x44, TRACE_SIZE);
153 traceLen = 0;
154 }
155
156 void iso14a_set_tracing(bool enable) {
157 tracing = enable;
158 }
159
160 void iso14a_set_timeout(uint32_t timeout) {
161 iso14a_timeout = timeout;
162 }
163
164 //-----------------------------------------------------------------------------
165 // Generate the parity value for a byte sequence
166 //
167 //-----------------------------------------------------------------------------
168 byte_t oddparity (const byte_t bt)
169 {
170 return OddByteParity[bt];
171 }
172
173 uint32_t GetParity(const uint8_t * pbtCmd, int iLen)
174 {
175 int i;
176 uint32_t dwPar = 0;
177
178 // Generate the parity bits
179 for (i = 0; i < iLen; i++) {
180 // and save them to a 32Bit word
181 dwPar |= ((OddByteParity[pbtCmd[i]]) << i);
182 }
183 return dwPar;
184 }
185
186 void AppendCrc14443a(uint8_t* data, int len)
187 {
188 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
189 }
190
191 // The function LogTrace() is also used by the iClass implementation in iClass.c
192 bool RAMFUNC LogTrace(const uint8_t * btBytes, uint8_t iLen, uint32_t timestamp, uint32_t dwParity, bool readerToTag)
193 {
194 if (!tracing) return FALSE;
195 // Return when trace is full
196 if (traceLen + sizeof(timestamp) + sizeof(dwParity) + iLen >= TRACE_SIZE) {
197 tracing = FALSE; // don't trace any more
198 return FALSE;
199 }
200
201 // Trace the random, i'm curious
202 trace[traceLen++] = ((timestamp >> 0) & 0xff);
203 trace[traceLen++] = ((timestamp >> 8) & 0xff);
204 trace[traceLen++] = ((timestamp >> 16) & 0xff);
205 trace[traceLen++] = ((timestamp >> 24) & 0xff);
206
207 if (!readerToTag) {
208 trace[traceLen - 1] |= 0x80;
209 }
210 trace[traceLen++] = ((dwParity >> 0) & 0xff);
211 trace[traceLen++] = ((dwParity >> 8) & 0xff);
212 trace[traceLen++] = ((dwParity >> 16) & 0xff);
213 trace[traceLen++] = ((dwParity >> 24) & 0xff);
214 trace[traceLen++] = iLen;
215 if (btBytes != NULL && iLen != 0) {
216 memcpy(trace + traceLen, btBytes, iLen);
217 }
218 traceLen += iLen;
219 return TRUE;
220 }
221
222 //=============================================================================
223 // ISO 14443 Type A - Miller decoder
224 //=============================================================================
225 // Basics:
226 // This decoder is used when the PM3 acts as a tag.
227 // The reader will generate "pauses" by temporarily switching of the field.
228 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
229 // The FPGA does a comparison with a threshold and would deliver e.g.:
230 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
231 // The Miller decoder needs to identify the following sequences:
232 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
233 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
234 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
235 // Note 1: the bitstream may start at any time. We therefore need to sync.
236 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
237 //-----------------------------------------------------------------------------
238 static tUart Uart;
239
240 // Lookup-Table to decide if 4 raw bits are a modulation.
241 // We accept two or three consecutive "0" in any position with the rest "1"
242 const bool Mod_Miller_LUT[] = {
243 TRUE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE,
244 TRUE, TRUE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE
245 };
246 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x00F0) >> 4])
247 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x000F)])
248
249 void UartReset()
250 {
251 Uart.state = STATE_UNSYNCD;
252 Uart.bitCount = 0;
253 Uart.len = 0; // number of decoded data bytes
254 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
255 Uart.parityBits = 0; //
256 Uart.twoBits = 0x0000; // buffer for 2 Bits
257 Uart.highCnt = 0;
258 Uart.startTime = 0;
259 Uart.endTime = 0;
260 }
261
262
263 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
264 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
265 {
266
267 Uart.twoBits = (Uart.twoBits << 8) | bit;
268
269 if (Uart.state == STATE_UNSYNCD) { // not yet synced
270 if (Uart.highCnt < 7) { // wait for a stable unmodulated signal
271 if (Uart.twoBits == 0xffff) {
272 Uart.highCnt++;
273 } else {
274 Uart.highCnt = 0;
275 }
276 } else {
277 Uart.syncBit = 0xFFFF; // not set
278 // look for 00xx1111 (the start bit)
279 if ((Uart.twoBits & 0x6780) == 0x0780) Uart.syncBit = 7;
280 else if ((Uart.twoBits & 0x33C0) == 0x03C0) Uart.syncBit = 6;
281 else if ((Uart.twoBits & 0x19E0) == 0x01E0) Uart.syncBit = 5;
282 else if ((Uart.twoBits & 0x0CF0) == 0x00F0) Uart.syncBit = 4;
283 else if ((Uart.twoBits & 0x0678) == 0x0078) Uart.syncBit = 3;
284 else if ((Uart.twoBits & 0x033C) == 0x003C) Uart.syncBit = 2;
285 else if ((Uart.twoBits & 0x019E) == 0x001E) Uart.syncBit = 1;
286 else if ((Uart.twoBits & 0x00CF) == 0x000F) Uart.syncBit = 0;
287 if (Uart.syncBit != 0xFFFF) {
288 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
289 Uart.startTime -= Uart.syncBit;
290 Uart.endTime = Uart.startTime;
291 Uart.state = STATE_START_OF_COMMUNICATION;
292 }
293 }
294
295 } else {
296
297 if (IsMillerModulationNibble1(Uart.twoBits >> Uart.syncBit)) {
298 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation in both halves - error
299 UartReset();
300 Uart.highCnt = 6;
301 } else { // Modulation in first half = Sequence Z = logic "0"
302 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
303 UartReset();
304 Uart.highCnt = 6;
305 } else {
306 Uart.bitCount++;
307 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
308 Uart.state = STATE_MILLER_Z;
309 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
310 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
311 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
312 Uart.parityBits <<= 1; // make room for the parity bit
313 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
314 Uart.bitCount = 0;
315 Uart.shiftReg = 0;
316 }
317 }
318 }
319 } else {
320 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
321 Uart.bitCount++;
322 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
323 Uart.state = STATE_MILLER_X;
324 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
325 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
326 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
327 Uart.parityBits <<= 1; // make room for the new parity bit
328 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
329 Uart.bitCount = 0;
330 Uart.shiftReg = 0;
331 }
332 } else { // no modulation in both halves - Sequence Y
333 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
334 Uart.state = STATE_UNSYNCD;
335 if(Uart.len == 0 && Uart.bitCount > 0) { // if we decoded some bits
336 Uart.shiftReg >>= (9 - Uart.bitCount); // add them to the output
337 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
338 Uart.parityBits <<= 1; // no parity bit - add "0"
339 Uart.bitCount--; // last "0" was part of the EOC sequence
340 }
341 return TRUE;
342 }
343 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
344 UartReset();
345 Uart.highCnt = 6;
346 } else { // a logic "0"
347 Uart.bitCount++;
348 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
349 Uart.state = STATE_MILLER_Y;
350 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
351 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
352 Uart.parityBits <<= 1; // make room for the parity bit
353 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
354 Uart.bitCount = 0;
355 Uart.shiftReg = 0;
356 }
357 }
358 }
359 }
360
361 }
362
363 return FALSE; // not finished yet, need more data
364 }
365
366
367
368 //=============================================================================
369 // ISO 14443 Type A - Manchester decoder
370 //=============================================================================
371 // Basics:
372 // This decoder is used when the PM3 acts as a reader.
373 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
374 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
375 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
376 // The Manchester decoder needs to identify the following sequences:
377 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
378 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
379 // 8 ticks unmodulated: Sequence F = end of communication
380 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
381 // Note 1: the bitstream may start at any time. We therefore need to sync.
382 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
383 static tDemod Demod;
384
385 // Lookup-Table to decide if 4 raw bits are a modulation.
386 // We accept three or four "1" in any position
387 const bool Mod_Manchester_LUT[] = {
388 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
389 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
390 };
391
392 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
393 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
394
395
396 void DemodReset()
397 {
398 Demod.state = DEMOD_UNSYNCD;
399 Demod.len = 0; // number of decoded data bytes
400 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
401 Demod.parityBits = 0; //
402 Demod.collisionPos = 0; // Position of collision bit
403 Demod.twoBits = 0xffff; // buffer for 2 Bits
404 Demod.highCnt = 0;
405 Demod.startTime = 0;
406 Demod.endTime = 0;
407 }
408
409 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
410 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
411 {
412
413 Demod.twoBits = (Demod.twoBits << 8) | bit;
414
415 if (Demod.state == DEMOD_UNSYNCD) {
416
417 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
418 if (Demod.twoBits == 0x0000) {
419 Demod.highCnt++;
420 } else {
421 Demod.highCnt = 0;
422 }
423 } else {
424 Demod.syncBit = 0xFFFF; // not set
425 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
426 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
427 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
428 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
429 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
430 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
431 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
432 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
433 if (Demod.syncBit != 0xFFFF) {
434 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
435 Demod.startTime -= Demod.syncBit;
436 Demod.bitCount = offset; // number of decoded data bits
437 Demod.state = DEMOD_MANCHESTER_DATA;
438 }
439 }
440
441 } else {
442
443 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
444 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
445 if (!Demod.collisionPos) {
446 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
447 }
448 } // modulation in first half only - Sequence D = 1
449 Demod.bitCount++;
450 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
451 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
452 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
453 Demod.parityBits <<= 1; // make room for the parity bit
454 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
455 Demod.bitCount = 0;
456 Demod.shiftReg = 0;
457 }
458 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
459 } else { // no modulation in first half
460 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
461 Demod.bitCount++;
462 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
463 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
464 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
465 Demod.parityBits <<= 1; // make room for the new parity bit
466 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
467 Demod.bitCount = 0;
468 Demod.shiftReg = 0;
469 }
470 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
471 } else { // no modulation in both halves - End of communication
472 if (Demod.len > 0 || Demod.bitCount > 0) { // received something
473 if(Demod.bitCount > 0) { // if we decoded bits
474 Demod.shiftReg >>= (9 - Demod.bitCount); // add the remaining decoded bits to the output
475 Demod.output[Demod.len++] = Demod.shiftReg & 0xff;
476 // No parity bit, so just shift a 0
477 Demod.parityBits <<= 1;
478 }
479 return TRUE; // we are finished with decoding the raw data sequence
480 } else { // nothing received. Start over
481 DemodReset();
482 }
483 }
484 }
485
486 }
487
488 return FALSE; // not finished yet, need more data
489 }
490
491 //=============================================================================
492 // Finally, a `sniffer' for ISO 14443 Type A
493 // Both sides of communication!
494 //=============================================================================
495
496 //-----------------------------------------------------------------------------
497 // Record the sequence of commands sent by the reader to the tag, with
498 // triggering so that we start recording at the point that the tag is moved
499 // near the reader.
500 //-----------------------------------------------------------------------------
501 void RAMFUNC SnoopIso14443a(uint8_t param) {
502 // param:
503 // bit 0 - trigger from first card answer
504 // bit 1 - trigger from first reader 7-bit request
505
506 LEDsoff();
507 // init trace buffer
508 iso14a_clear_trace();
509 iso14a_set_tracing(TRUE);
510
511 // We won't start recording the frames that we acquire until we trigger;
512 // a good trigger condition to get started is probably when we see a
513 // response from the tag.
514 // triggered == FALSE -- to wait first for card
515 bool triggered = !(param & 0x03);
516
517 // The command (reader -> tag) that we're receiving.
518 // The length of a received command will in most cases be no more than 18 bytes.
519 // So 32 should be enough!
520 uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);
521 // The response (tag -> reader) that we're receiving.
522 uint8_t *receivedResponse = (((uint8_t *)BigBuf) + RECV_RES_OFFSET);
523
524 // As we receive stuff, we copy it from receivedCmd or receivedResponse
525 // into trace, along with its length and other annotations.
526 //uint8_t *trace = (uint8_t *)BigBuf;
527
528 // The DMA buffer, used to stream samples from the FPGA
529 uint8_t *dmaBuf = ((uint8_t *)BigBuf) + DMA_BUFFER_OFFSET;
530 uint8_t *data = dmaBuf;
531 uint8_t previous_data = 0;
532 int maxDataLen = 0;
533 int dataLen = 0;
534 bool TagIsActive = FALSE;
535 bool ReaderIsActive = FALSE;
536
537 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
538
539 // Set up the demodulator for tag -> reader responses.
540 Demod.output = receivedResponse;
541
542 // Set up the demodulator for the reader -> tag commands
543 Uart.output = receivedCmd;
544
545 // Setup and start DMA.
546 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
547
548 // And now we loop, receiving samples.
549 for(uint32_t rsamples = 0; TRUE; ) {
550
551 if(BUTTON_PRESS()) {
552 DbpString("cancelled by button");
553 break;
554 }
555
556 LED_A_ON();
557 WDT_HIT();
558
559 int register readBufDataP = data - dmaBuf;
560 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
561 if (readBufDataP <= dmaBufDataP){
562 dataLen = dmaBufDataP - readBufDataP;
563 } else {
564 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
565 }
566 // test for length of buffer
567 if(dataLen > maxDataLen) {
568 maxDataLen = dataLen;
569 if(dataLen > 400) {
570 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
571 break;
572 }
573 }
574 if(dataLen < 1) continue;
575
576 // primary buffer was stopped( <-- we lost data!
577 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
578 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
579 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
580 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
581 }
582 // secondary buffer sets as primary, secondary buffer was stopped
583 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
584 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
585 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
586 }
587
588 LED_A_OFF();
589
590 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
591
592 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
593 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
594 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
595 LED_C_ON();
596
597 // check - if there is a short 7bit request from reader
598 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
599
600 if(triggered) {
601 if (!LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, Uart.parityBits, TRUE)) break;
602 if (!LogTrace(NULL, 0, Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, 0, TRUE)) break;
603 }
604 /* And ready to receive another command. */
605 UartReset();
606 /* And also reset the demod code, which might have been */
607 /* false-triggered by the commands from the reader. */
608 DemodReset();
609 LED_B_OFF();
610 }
611 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
612 }
613
614 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
615 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
616 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
617 LED_B_ON();
618
619 if (!LogTrace(receivedResponse, Demod.len, Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER, Demod.parityBits, FALSE)) break;
620 if (!LogTrace(NULL, 0, Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER, 0, FALSE)) break;
621
622 if ((!triggered) && (param & 0x01)) triggered = TRUE;
623
624 // And ready to receive another response.
625 DemodReset();
626 LED_C_OFF();
627 }
628 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
629 }
630 }
631
632 previous_data = *data;
633 rsamples++;
634 data++;
635 if(data == dmaBuf + DMA_BUFFER_SIZE) {
636 data = dmaBuf;
637 }
638 } // main cycle
639
640 DbpString("COMMAND FINISHED");
641
642 FpgaDisableSscDma();
643 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
644 Dbprintf("traceLen=%d, Uart.output[0]=%08x", traceLen, (uint32_t)Uart.output[0]);
645 LEDsoff();
646 }
647
648 //-----------------------------------------------------------------------------
649 // Prepare tag messages
650 //-----------------------------------------------------------------------------
651 static void CodeIso14443aAsTagPar(const uint8_t *cmd, int len, uint32_t dwParity)
652 {
653 int i;
654
655 ToSendReset();
656
657 // Correction bit, might be removed when not needed
658 ToSendStuffBit(0);
659 ToSendStuffBit(0);
660 ToSendStuffBit(0);
661 ToSendStuffBit(0);
662 ToSendStuffBit(1); // 1
663 ToSendStuffBit(0);
664 ToSendStuffBit(0);
665 ToSendStuffBit(0);
666
667 // Send startbit
668 ToSend[++ToSendMax] = SEC_D;
669 LastProxToAirDuration = 8 * ToSendMax - 4;
670
671 for(i = 0; i < len; i++) {
672 int j;
673 uint8_t b = cmd[i];
674
675 // Data bits
676 for(j = 0; j < 8; j++) {
677 if(b & 1) {
678 ToSend[++ToSendMax] = SEC_D;
679 } else {
680 ToSend[++ToSendMax] = SEC_E;
681 }
682 b >>= 1;
683 }
684
685 // Get the parity bit
686 if ((dwParity >> i) & 0x01) {
687 ToSend[++ToSendMax] = SEC_D;
688 LastProxToAirDuration = 8 * ToSendMax - 4;
689 } else {
690 ToSend[++ToSendMax] = SEC_E;
691 LastProxToAirDuration = 8 * ToSendMax;
692 }
693 }
694
695 // Send stopbit
696 ToSend[++ToSendMax] = SEC_F;
697
698 // Convert from last byte pos to length
699 ToSendMax++;
700 }
701
702 static void CodeIso14443aAsTag(const uint8_t *cmd, int len){
703 CodeIso14443aAsTagPar(cmd, len, GetParity(cmd, len));
704 }
705
706
707 static void Code4bitAnswerAsTag(uint8_t cmd)
708 {
709 int i;
710
711 ToSendReset();
712
713 // Correction bit, might be removed when not needed
714 ToSendStuffBit(0);
715 ToSendStuffBit(0);
716 ToSendStuffBit(0);
717 ToSendStuffBit(0);
718 ToSendStuffBit(1); // 1
719 ToSendStuffBit(0);
720 ToSendStuffBit(0);
721 ToSendStuffBit(0);
722
723 // Send startbit
724 ToSend[++ToSendMax] = SEC_D;
725
726 uint8_t b = cmd;
727 for(i = 0; i < 4; i++) {
728 if(b & 1) {
729 ToSend[++ToSendMax] = SEC_D;
730 LastProxToAirDuration = 8 * ToSendMax - 4;
731 } else {
732 ToSend[++ToSendMax] = SEC_E;
733 LastProxToAirDuration = 8 * ToSendMax;
734 }
735 b >>= 1;
736 }
737
738 // Send stopbit
739 ToSend[++ToSendMax] = SEC_F;
740
741 // Convert from last byte pos to length
742 ToSendMax++;
743 }
744
745 //-----------------------------------------------------------------------------
746 // Wait for commands from reader
747 // Stop when button is pressed
748 // Or return TRUE when command is captured
749 //-----------------------------------------------------------------------------
750 static int GetIso14443aCommandFromReader(uint8_t *received, int *len, int maxLen)
751 {
752 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
753 // only, since we are receiving, not transmitting).
754 // Signal field is off with the appropriate LED
755 LED_D_OFF();
756 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
757
758 // Now run a `software UART' on the stream of incoming samples.
759 UartReset();
760 Uart.output = received;
761
762 // clear RXRDY:
763 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
764
765 for(;;) {
766 WDT_HIT();
767
768 if(BUTTON_PRESS()) return FALSE;
769
770 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
771 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
772 if(MillerDecoding(b, 0)) {
773 *len = Uart.len;
774 return TRUE;
775 }
776 }
777 }
778 }
779
780 static int EmSendCmd14443aRaw(uint8_t *resp, int respLen, bool correctionNeeded);
781 int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
782 int EmSend4bit(uint8_t resp);
783 int EmSendCmdExPar(uint8_t *resp, int respLen, bool correctionNeeded, uint32_t par);
784 int EmSendCmdExPar(uint8_t *resp, int respLen, bool correctionNeeded, uint32_t par);
785 int EmSendCmdEx(uint8_t *resp, int respLen, bool correctionNeeded);
786 int EmSendCmd(uint8_t *resp, int respLen);
787 int EmSendCmdPar(uint8_t *resp, int respLen, uint32_t par);
788 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint32_t reader_Parity,
789 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint32_t tag_Parity);
790
791 static uint8_t* free_buffer_pointer = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);
792
793 typedef struct {
794 uint8_t* response;
795 size_t response_n;
796 uint8_t* modulation;
797 size_t modulation_n;
798 uint32_t ProxToAirDuration;
799 } tag_response_info_t;
800
801 void reset_free_buffer() {
802 free_buffer_pointer = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);
803 }
804
805 bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
806 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
807 // This will need the following byte array for a modulation sequence
808 // 144 data bits (18 * 8)
809 // 18 parity bits
810 // 2 Start and stop
811 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
812 // 1 just for the case
813 // ----------- +
814 // 166 bytes, since every bit that needs to be send costs us a byte
815 //
816
817 // Prepare the tag modulation bits from the message
818 CodeIso14443aAsTag(response_info->response,response_info->response_n);
819
820 // Make sure we do not exceed the free buffer space
821 if (ToSendMax > max_buffer_size) {
822 Dbprintf("Out of memory, when modulating bits for tag answer:");
823 Dbhexdump(response_info->response_n,response_info->response,false);
824 return false;
825 }
826
827 // Copy the byte array, used for this modulation to the buffer position
828 memcpy(response_info->modulation,ToSend,ToSendMax);
829
830 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
831 response_info->modulation_n = ToSendMax;
832 response_info->ProxToAirDuration = LastProxToAirDuration;
833
834 return true;
835 }
836
837 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
838 // Retrieve and store the current buffer index
839 response_info->modulation = free_buffer_pointer;
840
841 // Determine the maximum size we can use from our buffer
842 size_t max_buffer_size = (((uint8_t *)BigBuf)+FREE_BUFFER_OFFSET+FREE_BUFFER_SIZE)-free_buffer_pointer;
843
844 // Forward the prepare tag modulation function to the inner function
845 if (prepare_tag_modulation(response_info,max_buffer_size)) {
846 // Update the free buffer offset
847 free_buffer_pointer += ToSendMax;
848 return true;
849 } else {
850 return false;
851 }
852 }
853
854 //-----------------------------------------------------------------------------
855 // Main loop of simulated tag: receive commands from reader, decide what
856 // response to send, and send it.
857 //-----------------------------------------------------------------------------
858 void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
859 {
860 // Enable and clear the trace
861 iso14a_clear_trace();
862 iso14a_set_tracing(TRUE);
863
864 uint8_t sak;
865
866 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
867 uint8_t response1[2];
868
869 switch (tagType) {
870 case 1: { // MIFARE Classic
871 // Says: I am Mifare 1k - original line
872 response1[0] = 0x04;
873 response1[1] = 0x00;
874 sak = 0x08;
875 } break;
876 case 2: { // MIFARE Ultralight
877 // Says: I am a stupid memory tag, no crypto
878 response1[0] = 0x04;
879 response1[1] = 0x00;
880 sak = 0x00;
881 } break;
882 case 3: { // MIFARE DESFire
883 // Says: I am a DESFire tag, ph33r me
884 response1[0] = 0x04;
885 response1[1] = 0x03;
886 sak = 0x20;
887 } break;
888 case 4: { // ISO/IEC 14443-4
889 // Says: I am a javacard (JCOP)
890 response1[0] = 0x04;
891 response1[1] = 0x00;
892 sak = 0x28;
893 } break;
894 default: {
895 Dbprintf("Error: unkown tagtype (%d)",tagType);
896 return;
897 } break;
898 }
899
900 // The second response contains the (mandatory) first 24 bits of the UID
901 uint8_t response2[5];
902
903 // Check if the uid uses the (optional) part
904 uint8_t response2a[5];
905 if (uid_2nd) {
906 response2[0] = 0x88;
907 num_to_bytes(uid_1st,3,response2+1);
908 num_to_bytes(uid_2nd,4,response2a);
909 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
910
911 // Configure the ATQA and SAK accordingly
912 response1[0] |= 0x40;
913 sak |= 0x04;
914 } else {
915 num_to_bytes(uid_1st,4,response2);
916 // Configure the ATQA and SAK accordingly
917 response1[0] &= 0xBF;
918 sak &= 0xFB;
919 }
920
921 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
922 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
923
924 // Prepare the mandatory SAK (for 4 and 7 byte UID)
925 uint8_t response3[3];
926 response3[0] = sak;
927 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
928
929 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
930 uint8_t response3a[3];
931 response3a[0] = sak & 0xFB;
932 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
933
934 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
935 uint8_t response6[] = { 0x04, 0x58, 0x00, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS
936 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
937
938 #define TAG_RESPONSE_COUNT 7
939 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
940 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
941 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
942 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
943 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
944 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
945 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
946 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
947 };
948
949 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
950 // Such a response is less time critical, so we can prepare them on the fly
951 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
952 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
953 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
954 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
955 tag_response_info_t dynamic_response_info = {
956 .response = dynamic_response_buffer,
957 .response_n = 0,
958 .modulation = dynamic_modulation_buffer,
959 .modulation_n = 0
960 };
961
962 // Reset the offset pointer of the free buffer
963 reset_free_buffer();
964
965 // Prepare the responses of the anticollision phase
966 // there will be not enough time to do this at the moment the reader sends it REQA
967 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
968 prepare_allocated_tag_modulation(&responses[i]);
969 }
970
971 uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);
972 int len = 0;
973
974 // To control where we are in the protocol
975 int order = 0;
976 int lastorder;
977
978 // Just to allow some checks
979 int happened = 0;
980 int happened2 = 0;
981 int cmdsRecvd = 0;
982
983 // We need to listen to the high-frequency, peak-detected path.
984 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
985
986 cmdsRecvd = 0;
987 tag_response_info_t* p_response;
988
989 LED_A_ON();
990 for(;;) {
991 // Clean receive command buffer
992
993 if(!GetIso14443aCommandFromReader(receivedCmd, &len, RECV_CMD_SIZE)) {
994 DbpString("Button press");
995 break;
996 }
997
998 p_response = NULL;
999
1000 // doob - added loads of debug strings so we can see what the reader is saying to us during the sim as hi14alist is not populated
1001 // Okay, look at the command now.
1002 lastorder = order;
1003 if(receivedCmd[0] == 0x26) { // Received a REQUEST
1004 p_response = &responses[0]; order = 1;
1005 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
1006 p_response = &responses[0]; order = 6;
1007 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
1008 p_response = &responses[1]; order = 2;
1009 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
1010 p_response = &responses[2]; order = 20;
1011 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
1012 p_response = &responses[3]; order = 3;
1013 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
1014 p_response = &responses[4]; order = 30;
1015 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
1016 EmSendCmdEx(data+(4*receivedCmd[0]),16,false);
1017 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1018 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1019 p_response = NULL;
1020 } else if(receivedCmd[0] == 0x50) { // Received a HALT
1021 // DbpString("Reader requested we HALT!:");
1022 if (tracing) {
1023 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
1024 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
1025 }
1026 p_response = NULL;
1027 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
1028 p_response = &responses[5]; order = 7;
1029 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
1030 if (tagType == 1 || tagType == 2) { // RATS not supported
1031 EmSend4bit(CARD_NACK_NA);
1032 p_response = NULL;
1033 } else {
1034 p_response = &responses[6]; order = 70;
1035 }
1036 } else if (order == 7 && len == 8) { // Received authentication request
1037 if (tracing) {
1038 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
1039 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
1040 }
1041 uint32_t nr = bytes_to_num(receivedCmd,4);
1042 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1043 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1044 } else {
1045 // Check for ISO 14443A-4 compliant commands, look at left nibble
1046 switch (receivedCmd[0]) {
1047
1048 case 0x0B:
1049 case 0x0A: { // IBlock (command)
1050 dynamic_response_info.response[0] = receivedCmd[0];
1051 dynamic_response_info.response[1] = 0x00;
1052 dynamic_response_info.response[2] = 0x90;
1053 dynamic_response_info.response[3] = 0x00;
1054 dynamic_response_info.response_n = 4;
1055 } break;
1056
1057 case 0x1A:
1058 case 0x1B: { // Chaining command
1059 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1060 dynamic_response_info.response_n = 2;
1061 } break;
1062
1063 case 0xaa:
1064 case 0xbb: {
1065 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1066 dynamic_response_info.response_n = 2;
1067 } break;
1068
1069 case 0xBA: { //
1070 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1071 dynamic_response_info.response_n = 2;
1072 } break;
1073
1074 case 0xCA:
1075 case 0xC2: { // Readers sends deselect command
1076 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1077 dynamic_response_info.response_n = 2;
1078 } break;
1079
1080 default: {
1081 // Never seen this command before
1082 if (tracing) {
1083 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
1084 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
1085 }
1086 Dbprintf("Received unknown command (len=%d):",len);
1087 Dbhexdump(len,receivedCmd,false);
1088 // Do not respond
1089 dynamic_response_info.response_n = 0;
1090 } break;
1091 }
1092
1093 if (dynamic_response_info.response_n > 0) {
1094 // Copy the CID from the reader query
1095 dynamic_response_info.response[1] = receivedCmd[1];
1096
1097 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1098 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1099 dynamic_response_info.response_n += 2;
1100
1101 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1102 Dbprintf("Error preparing tag response");
1103 if (tracing) {
1104 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
1105 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
1106 }
1107 break;
1108 }
1109 p_response = &dynamic_response_info;
1110 }
1111 }
1112
1113 // Count number of wakeups received after a halt
1114 if(order == 6 && lastorder == 5) { happened++; }
1115
1116 // Count number of other messages after a halt
1117 if(order != 6 && lastorder == 5) { happened2++; }
1118
1119 if(cmdsRecvd > 999) {
1120 DbpString("1000 commands later...");
1121 break;
1122 }
1123 cmdsRecvd++;
1124
1125 if (p_response != NULL) {
1126 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1127 // do the tracing for the previous reader request and this tag answer:
1128 EmLogTrace(Uart.output,
1129 Uart.len,
1130 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1131 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1132 Uart.parityBits,
1133 p_response->response,
1134 p_response->response_n,
1135 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1136 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1137 SwapBits(GetParity(p_response->response, p_response->response_n), p_response->response_n));
1138 }
1139
1140 if (!tracing) {
1141 Dbprintf("Trace Full. Simulation stopped.");
1142 break;
1143 }
1144 }
1145
1146 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1147 LED_A_OFF();
1148 }
1149
1150
1151 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1152 // of bits specified in the delay parameter.
1153 void PrepareDelayedTransfer(uint16_t delay)
1154 {
1155 uint8_t bitmask = 0;
1156 uint8_t bits_to_shift = 0;
1157 uint8_t bits_shifted = 0;
1158
1159 delay &= 0x07;
1160 if (delay) {
1161 for (uint16_t i = 0; i < delay; i++) {
1162 bitmask |= (0x01 << i);
1163 }
1164 ToSend[ToSendMax++] = 0x00;
1165 for (uint16_t i = 0; i < ToSendMax; i++) {
1166 bits_to_shift = ToSend[i] & bitmask;
1167 ToSend[i] = ToSend[i] >> delay;
1168 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1169 bits_shifted = bits_to_shift;
1170 }
1171 }
1172 }
1173
1174
1175 //-------------------------------------------------------------------------------------
1176 // Transmit the command (to the tag) that was placed in ToSend[].
1177 // Parameter timing:
1178 // if NULL: transfer at next possible time, taking into account
1179 // request guard time and frame delay time
1180 // if == 0: transfer immediately and return time of transfer
1181 // if != 0: delay transfer until time specified
1182 //-------------------------------------------------------------------------------------
1183 static void TransmitFor14443a(const uint8_t *cmd, int len, uint32_t *timing)
1184 {
1185
1186 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1187
1188 uint32_t ThisTransferTime = 0;
1189
1190 if (timing) {
1191 if(*timing == 0) { // Measure time
1192 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1193 } else {
1194 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1195 }
1196 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1197 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1198 LastTimeProxToAirStart = *timing;
1199 } else {
1200 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1201 while(GetCountSspClk() < ThisTransferTime);
1202 LastTimeProxToAirStart = ThisTransferTime;
1203 }
1204
1205 // clear TXRDY
1206 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1207
1208 // for(uint16_t c = 0; c < 10;) { // standard delay for each transfer (allow tag to be ready after last transmission)
1209 // if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1210 // AT91C_BASE_SSC->SSC_THR = SEC_Y;
1211 // c++;
1212 // }
1213 // }
1214
1215 uint16_t c = 0;
1216 for(;;) {
1217 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1218 AT91C_BASE_SSC->SSC_THR = cmd[c];
1219 c++;
1220 if(c >= len) {
1221 break;
1222 }
1223 }
1224 }
1225
1226 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1227
1228 }
1229
1230
1231 //-----------------------------------------------------------------------------
1232 // Prepare reader command (in bits, support short frames) to send to FPGA
1233 //-----------------------------------------------------------------------------
1234 void CodeIso14443aBitsAsReaderPar(const uint8_t * cmd, int bits, uint32_t dwParity)
1235 {
1236 int i, j;
1237 int last;
1238 uint8_t b;
1239
1240 ToSendReset();
1241
1242 // Start of Communication (Seq. Z)
1243 ToSend[++ToSendMax] = SEC_Z;
1244 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1245 last = 0;
1246
1247 size_t bytecount = nbytes(bits);
1248 // Generate send structure for the data bits
1249 for (i = 0; i < bytecount; i++) {
1250 // Get the current byte to send
1251 b = cmd[i];
1252 size_t bitsleft = MIN((bits-(i*8)),8);
1253
1254 for (j = 0; j < bitsleft; j++) {
1255 if (b & 1) {
1256 // Sequence X
1257 ToSend[++ToSendMax] = SEC_X;
1258 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1259 last = 1;
1260 } else {
1261 if (last == 0) {
1262 // Sequence Z
1263 ToSend[++ToSendMax] = SEC_Z;
1264 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1265 } else {
1266 // Sequence Y
1267 ToSend[++ToSendMax] = SEC_Y;
1268 last = 0;
1269 }
1270 }
1271 b >>= 1;
1272 }
1273
1274 // Only transmit (last) parity bit if we transmitted a complete byte
1275 if (j == 8) {
1276 // Get the parity bit
1277 if ((dwParity >> i) & 0x01) {
1278 // Sequence X
1279 ToSend[++ToSendMax] = SEC_X;
1280 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1281 last = 1;
1282 } else {
1283 if (last == 0) {
1284 // Sequence Z
1285 ToSend[++ToSendMax] = SEC_Z;
1286 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1287 } else {
1288 // Sequence Y
1289 ToSend[++ToSendMax] = SEC_Y;
1290 last = 0;
1291 }
1292 }
1293 }
1294 }
1295
1296 // End of Communication: Logic 0 followed by Sequence Y
1297 if (last == 0) {
1298 // Sequence Z
1299 ToSend[++ToSendMax] = SEC_Z;
1300 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1301 } else {
1302 // Sequence Y
1303 ToSend[++ToSendMax] = SEC_Y;
1304 last = 0;
1305 }
1306 ToSend[++ToSendMax] = SEC_Y;
1307
1308 // Convert to length of command:
1309 ToSendMax++;
1310 }
1311
1312 //-----------------------------------------------------------------------------
1313 // Prepare reader command to send to FPGA
1314 //-----------------------------------------------------------------------------
1315 void CodeIso14443aAsReaderPar(const uint8_t * cmd, int len, uint32_t dwParity)
1316 {
1317 CodeIso14443aBitsAsReaderPar(cmd,len*8,dwParity);
1318 }
1319
1320 //-----------------------------------------------------------------------------
1321 // Wait for commands from reader
1322 // Stop when button is pressed (return 1) or field was gone (return 2)
1323 // Or return 0 when command is captured
1324 //-----------------------------------------------------------------------------
1325 static int EmGetCmd(uint8_t *received, int *len)
1326 {
1327 *len = 0;
1328
1329 uint32_t timer = 0, vtime = 0;
1330 int analogCnt = 0;
1331 int analogAVG = 0;
1332
1333 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1334 // only, since we are receiving, not transmitting).
1335 // Signal field is off with the appropriate LED
1336 LED_D_OFF();
1337 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1338
1339 // Set ADC to read field strength
1340 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1341 AT91C_BASE_ADC->ADC_MR =
1342 ADC_MODE_PRESCALE(32) |
1343 ADC_MODE_STARTUP_TIME(16) |
1344 ADC_MODE_SAMPLE_HOLD_TIME(8);
1345 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1346 // start ADC
1347 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1348
1349 // Now run a 'software UART' on the stream of incoming samples.
1350 UartReset();
1351 Uart.output = received;
1352
1353 // Clear RXRDY:
1354 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1355
1356 for(;;) {
1357 WDT_HIT();
1358
1359 if (BUTTON_PRESS()) return 1;
1360
1361 // test if the field exists
1362 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1363 analogCnt++;
1364 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1365 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1366 if (analogCnt >= 32) {
1367 if ((33000 * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1368 vtime = GetTickCount();
1369 if (!timer) timer = vtime;
1370 // 50ms no field --> card to idle state
1371 if (vtime - timer > 50) return 2;
1372 } else
1373 if (timer) timer = 0;
1374 analogCnt = 0;
1375 analogAVG = 0;
1376 }
1377 }
1378
1379 // receive and test the miller decoding
1380 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1381 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1382 if(MillerDecoding(b, 0)) {
1383 *len = Uart.len;
1384 return 0;
1385 }
1386 }
1387
1388 }
1389 }
1390
1391
1392 static int EmSendCmd14443aRaw(uint8_t *resp, int respLen, bool correctionNeeded)
1393 {
1394 uint8_t b;
1395 uint16_t i = 0;
1396 uint32_t ThisTransferTime;
1397
1398 // Modulate Manchester
1399 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1400
1401 // include correction bit if necessary
1402 if (Uart.parityBits & 0x01) {
1403 correctionNeeded = TRUE;
1404 }
1405 if(correctionNeeded) {
1406 // 1236, so correction bit needed
1407 i = 0;
1408 } else {
1409 i = 1;
1410 }
1411
1412 // clear receiving shift register and holding register
1413 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1414 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1415 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1416 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1417
1418 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1419 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1420 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1421 if (AT91C_BASE_SSC->SSC_RHR) break;
1422 }
1423
1424 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1425
1426 // Clear TXRDY:
1427 AT91C_BASE_SSC->SSC_THR = SEC_F;
1428
1429 // send cycle
1430 for(; i <= respLen; ) {
1431 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1432 AT91C_BASE_SSC->SSC_THR = resp[i++];
1433 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1434 }
1435
1436 if(BUTTON_PRESS()) {
1437 break;
1438 }
1439 }
1440
1441 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1442 for (i = 0; i < 2 ; ) {
1443 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1444 AT91C_BASE_SSC->SSC_THR = SEC_F;
1445 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1446 i++;
1447 }
1448 }
1449
1450 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1451
1452 return 0;
1453 }
1454
1455 int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1456 Code4bitAnswerAsTag(resp);
1457 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1458 // do the tracing for the previous reader request and this tag answer:
1459 EmLogTrace(Uart.output,
1460 Uart.len,
1461 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1462 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1463 Uart.parityBits,
1464 &resp,
1465 1,
1466 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1467 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1468 SwapBits(GetParity(&resp, 1), 1));
1469 return res;
1470 }
1471
1472 int EmSend4bit(uint8_t resp){
1473 return EmSend4bitEx(resp, false);
1474 }
1475
1476 int EmSendCmdExPar(uint8_t *resp, int respLen, bool correctionNeeded, uint32_t par){
1477 CodeIso14443aAsTagPar(resp, respLen, par);
1478 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1479 // do the tracing for the previous reader request and this tag answer:
1480 EmLogTrace(Uart.output,
1481 Uart.len,
1482 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1483 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1484 Uart.parityBits,
1485 resp,
1486 respLen,
1487 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1488 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1489 SwapBits(GetParity(resp, respLen), respLen));
1490 return res;
1491 }
1492
1493 int EmSendCmdEx(uint8_t *resp, int respLen, bool correctionNeeded){
1494 return EmSendCmdExPar(resp, respLen, correctionNeeded, GetParity(resp, respLen));
1495 }
1496
1497 int EmSendCmd(uint8_t *resp, int respLen){
1498 return EmSendCmdExPar(resp, respLen, false, GetParity(resp, respLen));
1499 }
1500
1501 int EmSendCmdPar(uint8_t *resp, int respLen, uint32_t par){
1502 return EmSendCmdExPar(resp, respLen, false, par);
1503 }
1504
1505 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint32_t reader_Parity,
1506 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint32_t tag_Parity)
1507 {
1508 if (tracing) {
1509 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1510 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1511 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1512 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1513 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1514 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1515 reader_EndTime = tag_StartTime - exact_fdt;
1516 reader_StartTime = reader_EndTime - reader_modlen;
1517 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_Parity, TRUE)) {
1518 return FALSE;
1519 } else if (!LogTrace(NULL, 0, reader_EndTime, 0, TRUE)) {
1520 return FALSE;
1521 } else if (!LogTrace(tag_data, tag_len, tag_StartTime, tag_Parity, FALSE)) {
1522 return FALSE;
1523 } else {
1524 return (!LogTrace(NULL, 0, tag_EndTime, 0, FALSE));
1525 }
1526 } else {
1527 return TRUE;
1528 }
1529 }
1530
1531 //-----------------------------------------------------------------------------
1532 // Wait a certain time for tag response
1533 // If a response is captured return TRUE
1534 // If it takes too long return FALSE
1535 //-----------------------------------------------------------------------------
1536 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint16_t offset, int maxLen)
1537 {
1538 uint16_t c;
1539
1540 // Set FPGA mode to "reader listen mode", no modulation (listen
1541 // only, since we are receiving, not transmitting).
1542 // Signal field is on with the appropriate LED
1543 LED_D_ON();
1544 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1545
1546 // Now get the answer from the card
1547 DemodReset();
1548 Demod.output = receivedResponse;
1549
1550 // clear RXRDY:
1551 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1552
1553 c = 0;
1554 for(;;) {
1555 WDT_HIT();
1556
1557 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1558 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1559 if(ManchesterDecoding(b, offset, 0)) {
1560 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1561 return TRUE;
1562 } else if(c++ > iso14a_timeout) {
1563 return FALSE;
1564 }
1565 }
1566 }
1567 }
1568
1569 void ReaderTransmitBitsPar(uint8_t* frame, int bits, uint32_t par, uint32_t *timing)
1570 {
1571
1572 CodeIso14443aBitsAsReaderPar(frame,bits,par);
1573
1574 // Send command to tag
1575 TransmitFor14443a(ToSend, ToSendMax, timing);
1576 if(trigger)
1577 LED_A_ON();
1578
1579 // Log reader command in trace buffer
1580 if (tracing) {
1581 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
1582 LogTrace(NULL, 0, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, 0, TRUE);
1583 }
1584 }
1585
1586 void ReaderTransmitPar(uint8_t* frame, int len, uint32_t par, uint32_t *timing)
1587 {
1588 ReaderTransmitBitsPar(frame,len*8,par, timing);
1589 }
1590
1591 void ReaderTransmitBits(uint8_t* frame, int len, uint32_t *timing)
1592 {
1593 // Generate parity and redirect
1594 ReaderTransmitBitsPar(frame,len,GetParity(frame,len/8), timing);
1595 }
1596
1597 void ReaderTransmit(uint8_t* frame, int len, uint32_t *timing)
1598 {
1599 // Generate parity and redirect
1600 ReaderTransmitBitsPar(frame,len*8,GetParity(frame,len), timing);
1601 }
1602
1603 int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset)
1604 {
1605 if (!GetIso14443aAnswerFromTag(receivedAnswer,offset,160)) return FALSE;
1606 if (tracing) {
1607 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.parityBits, FALSE);
1608 LogTrace(NULL, 0, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, 0, FALSE);
1609 }
1610 return Demod.len;
1611 }
1612
1613 int ReaderReceive(uint8_t* receivedAnswer)
1614 {
1615 return ReaderReceiveOffset(receivedAnswer, 0);
1616 }
1617
1618 int ReaderReceiveDesfiresAuthTiming(uint8_t *receivedAnswer, uint32_t *elapsedTime)
1619 {
1620 int len = ReaderReceiveOffset(receivedAnswer, 0);
1621 *elapsedTime = (Demod.endTime*16 - DELAY_AIR2ARM_AS_READER) - (Demod.startTime*16 - DELAY_AIR2ARM_AS_READER);
1622 return len;
1623 }
1624
1625 int ReaderReceivePar(uint8_t *receivedAnswer, uint32_t *parptr)
1626 {
1627 if (!GetIso14443aAnswerFromTag(receivedAnswer,0,160)) return FALSE;
1628 if (tracing) {
1629 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.parityBits, FALSE);
1630 LogTrace(NULL, 0, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, 0, FALSE);
1631 }
1632 *parptr = Demod.parityBits;
1633 return Demod.len;
1634 }
1635
1636 /* performs iso14443a anticollision procedure
1637 * fills the uid pointer unless NULL
1638 * fills resp_data unless NULL */
1639 int iso14443a_select_card(byte_t* uid_ptr, iso14a_card_select_t* p_hi14a_card, uint32_t* cuid_ptr) {
1640 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1641 uint8_t sel_all[] = { 0x93,0x20 };
1642 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1643 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1644 uint8_t* resp = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET); // was 3560 - tied to other size changes
1645 byte_t uid_resp[4];
1646 size_t uid_resp_len;
1647
1648 uint8_t sak = 0x04; // cascade uid
1649 int cascade_level = 0;
1650 int len;
1651
1652 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1653 ReaderTransmitBitsPar(wupa,7,0, NULL);
1654
1655 // Receive the ATQA
1656 if(!ReaderReceive(resp)) return 0;
1657 // Dbprintf("atqa: %02x %02x",resp[0],resp[1]);
1658
1659 if(p_hi14a_card) {
1660 memcpy(p_hi14a_card->atqa, resp, 2);
1661 p_hi14a_card->uidlen = 0;
1662 memset(p_hi14a_card->uid,0,10);
1663 }
1664
1665 // clear uid
1666 if (uid_ptr) {
1667 memset(uid_ptr,0,10);
1668 }
1669
1670 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1671 // which case we need to make a cascade 2 request and select - this is a long UID
1672 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1673 for(; sak & 0x04; cascade_level++) {
1674 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1675 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1676
1677 // SELECT_ALL
1678 ReaderTransmit(sel_all,sizeof(sel_all), NULL);
1679 if (!ReaderReceive(resp)) return 0;
1680
1681 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1682 memset(uid_resp, 0, 4);
1683 uint16_t uid_resp_bits = 0;
1684 uint16_t collision_answer_offset = 0;
1685 // anti-collision-loop:
1686 while (Demod.collisionPos) {
1687 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1688 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1689 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1690 uid_resp[uid_resp_bits & 0xf8] |= UIDbit << (uid_resp_bits % 8);
1691 }
1692 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1693 uid_resp_bits++;
1694 // construct anticollosion command:
1695 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1696 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1697 sel_uid[2+i] = uid_resp[i];
1698 }
1699 collision_answer_offset = uid_resp_bits%8;
1700 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1701 if (!ReaderReceiveOffset(resp, collision_answer_offset)) return 0;
1702 }
1703 // finally, add the last bits and BCC of the UID
1704 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1705 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1706 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1707 }
1708
1709 } else { // no collision, use the response to SELECT_ALL as current uid
1710 memcpy(uid_resp,resp,4);
1711 }
1712 uid_resp_len = 4;
1713 // Dbprintf("uid: %02x %02x %02x %02x",uid_resp[0],uid_resp[1],uid_resp[2],uid_resp[3]);
1714
1715 // calculate crypto UID. Always use last 4 Bytes.
1716 if(cuid_ptr) {
1717 *cuid_ptr = bytes_to_num(uid_resp, 4);
1718 }
1719
1720 // Construct SELECT UID command
1721 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1722 memcpy(sel_uid+2,uid_resp,4); // the UID
1723 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1724 AppendCrc14443a(sel_uid,7); // calculate and add CRC
1725 ReaderTransmit(sel_uid,sizeof(sel_uid), NULL);
1726
1727 // Receive the SAK
1728 if (!ReaderReceive(resp)) return 0;
1729 sak = resp[0];
1730
1731 // Test if more parts of the uid are comming
1732 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1733 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1734 // http://www.nxp.com/documents/application_note/AN10927.pdf
1735 memcpy(uid_resp, uid_resp + 1, 3);
1736 uid_resp_len = 3;
1737 }
1738
1739 if(uid_ptr) {
1740 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1741 }
1742
1743 if(p_hi14a_card) {
1744 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1745 p_hi14a_card->uidlen += uid_resp_len;
1746 }
1747 }
1748
1749 if(p_hi14a_card) {
1750 p_hi14a_card->sak = sak;
1751 p_hi14a_card->ats_len = 0;
1752 }
1753
1754 if( (sak & 0x20) == 0) {
1755 return 2; // non iso14443a compliant tag
1756 }
1757
1758 // Request for answer to select
1759 AppendCrc14443a(rats, 2);
1760 ReaderTransmit(rats, sizeof(rats), NULL);
1761
1762 if (!(len = ReaderReceive(resp))) return 0;
1763
1764 if(p_hi14a_card) {
1765 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1766 p_hi14a_card->ats_len = len;
1767 }
1768
1769 // reset the PCB block number
1770 iso14_pcb_blocknum = 0;
1771 return 1;
1772 }
1773
1774 void iso14443a_setup(uint8_t fpga_minor_mode) {
1775 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1776 // Set up the synchronous serial port
1777 FpgaSetupSsc();
1778 // connect Demodulated Signal to ADC:
1779 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1780
1781 // Signal field is on with the appropriate LED
1782 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1783 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1784 LED_D_ON();
1785 } else {
1786 LED_D_OFF();
1787 }
1788 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
1789
1790 // Start the timer
1791 StartCountSspClk();
1792
1793 DemodReset();
1794 UartReset();
1795 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1796 iso14a_set_timeout(1050); // 10ms default 10*105 =
1797 }
1798
1799 int iso14_apdu(uint8_t * cmd, size_t cmd_len, void * data) {
1800 uint8_t real_cmd[cmd_len+4];
1801 real_cmd[0] = 0x0a; //I-Block
1802 // put block number into the PCB
1803 real_cmd[0] |= iso14_pcb_blocknum;
1804 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1805 memcpy(real_cmd+2, cmd, cmd_len);
1806 AppendCrc14443a(real_cmd,cmd_len+2);
1807
1808 ReaderTransmit(real_cmd, cmd_len+4, NULL);
1809 size_t len = ReaderReceive(data);
1810 uint8_t * data_bytes = (uint8_t *) data;
1811 if (!len)
1812 return 0; //DATA LINK ERROR
1813 // if we received an I- or R(ACK)-Block with a block number equal to the
1814 // current block number, toggle the current block number
1815 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1816 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1817 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1818 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1819 {
1820 iso14_pcb_blocknum ^= 1;
1821 }
1822
1823 return len;
1824 }
1825
1826 //-----------------------------------------------------------------------------
1827 // Read an ISO 14443a tag. Send out commands and store answers.
1828 //
1829 //-----------------------------------------------------------------------------
1830 void ReaderIso14443a(UsbCommand *c)
1831 {
1832 iso14a_command_t param = c->arg[0];
1833 uint8_t *cmd = c->d.asBytes;
1834 size_t len = c->arg[1] & 0xFFFF;
1835 size_t lenbits = c->arg[1] >> 16;
1836 uint32_t arg0 = 0;
1837 byte_t buf[USB_CMD_DATA_SIZE];
1838
1839 if(param & ISO14A_CONNECT) {
1840 iso14a_clear_trace();
1841 }
1842
1843 iso14a_set_tracing(TRUE);
1844
1845 if(param & ISO14A_REQUEST_TRIGGER) {
1846 iso14a_set_trigger(TRUE);
1847 }
1848
1849 if(param & ISO14A_CONNECT) {
1850 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
1851 if(!(param & ISO14A_NO_SELECT)) {
1852 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1853 arg0 = iso14443a_select_card(NULL,card,NULL);
1854 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1855 }
1856 }
1857
1858 if(param & ISO14A_SET_TIMEOUT) {
1859 iso14a_timeout = c->arg[2];
1860 }
1861
1862 if(param & ISO14A_APDU) {
1863 arg0 = iso14_apdu(cmd, len, buf);
1864 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1865 }
1866
1867 if(param & ISO14A_RAW) {
1868 if(param & ISO14A_APPEND_CRC) {
1869 AppendCrc14443a(cmd,len);
1870 len += 2;
1871 lenbits += 16;
1872 }
1873 if(lenbits>0) {
1874
1875 ReaderTransmitBitsPar(cmd,lenbits,GetParity(cmd,lenbits/8), NULL);
1876 } else {
1877 ReaderTransmit(cmd,len, NULL);
1878 }
1879 arg0 = ReaderReceive(buf);
1880 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1881 }
1882
1883 if(param & ISO14A_REQUEST_TRIGGER) {
1884 iso14a_set_trigger(FALSE);
1885 }
1886
1887 if(param & ISO14A_NO_DISCONNECT) {
1888 return;
1889 }
1890
1891 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1892 LEDsoff();
1893 }
1894
1895
1896 // Determine the distance between two nonces.
1897 // Assume that the difference is small, but we don't know which is first.
1898 // Therefore try in alternating directions.
1899 int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
1900
1901 uint16_t i;
1902 uint32_t nttmp1, nttmp2;
1903
1904 if (nt1 == nt2) return 0;
1905
1906 nttmp1 = nt1;
1907 nttmp2 = nt2;
1908
1909 for (i = 1; i < 32768; i++) {
1910 nttmp1 = prng_successor(nttmp1, 1);
1911 if (nttmp1 == nt2) return i;
1912 nttmp2 = prng_successor(nttmp2, 1);
1913 if (nttmp2 == nt1) return -i;
1914 }
1915
1916 return(-99999); // either nt1 or nt2 are invalid nonces
1917 }
1918
1919
1920 //-----------------------------------------------------------------------------
1921 // Recover several bits of the cypher stream. This implements (first stages of)
1922 // the algorithm described in "The Dark Side of Security by Obscurity and
1923 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
1924 // (article by Nicolas T. Courtois, 2009)
1925 //-----------------------------------------------------------------------------
1926 void ReaderMifare(bool first_try)
1927 {
1928 // Mifare AUTH
1929 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
1930 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
1931 static uint8_t mf_nr_ar3;
1932
1933 uint8_t* receivedAnswer = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);
1934
1935 iso14a_clear_trace();
1936 iso14a_set_tracing(TRUE);
1937
1938 byte_t nt_diff = 0;
1939 byte_t par = 0;
1940 //byte_t par_mask = 0xff;
1941 static byte_t par_low = 0;
1942 bool led_on = TRUE;
1943 uint8_t uid[10];
1944 uint32_t cuid;
1945
1946 uint32_t nt, previous_nt;
1947 static uint32_t nt_attacked = 0;
1948 byte_t par_list[8] = {0,0,0,0,0,0,0,0};
1949 byte_t ks_list[8] = {0,0,0,0,0,0,0,0};
1950
1951 static uint32_t sync_time;
1952 static uint32_t sync_cycles;
1953 int catch_up_cycles = 0;
1954 int last_catch_up = 0;
1955 uint16_t consecutive_resyncs = 0;
1956 int isOK = 0;
1957
1958
1959
1960 if (first_try) {
1961 mf_nr_ar3 = 0;
1962 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
1963 sync_time = GetCountSspClk() & 0xfffffff8;
1964 sync_cycles = 65536; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
1965 nt_attacked = 0;
1966 nt = 0;
1967 par = 0;
1968 }
1969 else {
1970 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
1971 // nt_attacked = prng_successor(nt_attacked, 1);
1972 mf_nr_ar3++;
1973 mf_nr_ar[3] = mf_nr_ar3;
1974 par = par_low;
1975 }
1976
1977 LED_A_ON();
1978 LED_B_OFF();
1979 LED_C_OFF();
1980
1981
1982 for(uint16_t i = 0; TRUE; i++) {
1983
1984 WDT_HIT();
1985
1986 // Test if the action was cancelled
1987 if(BUTTON_PRESS()) {
1988 break;
1989 }
1990
1991 LED_C_ON();
1992
1993 if(!iso14443a_select_card(uid, NULL, &cuid)) {
1994 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
1995 continue;
1996 }
1997
1998 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
1999 catch_up_cycles = 0;
2000
2001 // if we missed the sync time already, advance to the next nonce repeat
2002 while(GetCountSspClk() > sync_time) {
2003 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2004 }
2005
2006 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2007 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2008
2009 // Receive the (4 Byte) "random" nonce
2010 if (!ReaderReceive(receivedAnswer)) {
2011 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2012 continue;
2013 }
2014
2015 previous_nt = nt;
2016 nt = bytes_to_num(receivedAnswer, 4);
2017
2018 // Transmit reader nonce with fake par
2019 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2020
2021 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2022 int nt_distance = dist_nt(previous_nt, nt);
2023 if (nt_distance == 0) {
2024 nt_attacked = nt;
2025 }
2026 else {
2027 if (nt_distance == -99999) { // invalid nonce received, try again
2028 continue;
2029 }
2030 sync_cycles = (sync_cycles - nt_distance);
2031 if (MF_DBGLEVEL >= 3) Dbprintf("calibrating in cycle %d. nt_distance=%d, Sync_cycles: %d\n", i, nt_distance, sync_cycles);
2032 continue;
2033 }
2034 }
2035
2036 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2037 catch_up_cycles = -dist_nt(nt_attacked, nt);
2038 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2039 catch_up_cycles = 0;
2040 continue;
2041 }
2042 if (catch_up_cycles == last_catch_up) {
2043 consecutive_resyncs++;
2044 }
2045 else {
2046 last_catch_up = catch_up_cycles;
2047 consecutive_resyncs = 0;
2048 }
2049 if (consecutive_resyncs < 3) {
2050 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
2051 }
2052 else {
2053 sync_cycles = sync_cycles + catch_up_cycles;
2054 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
2055 }
2056 continue;
2057 }
2058
2059 consecutive_resyncs = 0;
2060
2061 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2062 if (ReaderReceive(receivedAnswer))
2063 {
2064 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2065
2066 if (nt_diff == 0)
2067 {
2068 par_low = par & 0x07; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2069 }
2070
2071 led_on = !led_on;
2072 if(led_on) LED_B_ON(); else LED_B_OFF();
2073
2074 par_list[nt_diff] = par;
2075 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2076
2077 // Test if the information is complete
2078 if (nt_diff == 0x07) {
2079 isOK = 1;
2080 break;
2081 }
2082
2083 nt_diff = (nt_diff + 1) & 0x07;
2084 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2085 par = par_low;
2086 } else {
2087 if (nt_diff == 0 && first_try)
2088 {
2089 par++;
2090 } else {
2091 par = (((par >> 3) + 1) << 3) | par_low;
2092 }
2093 }
2094 }
2095
2096
2097 mf_nr_ar[3] &= 0x1F;
2098
2099 byte_t buf[28];
2100 memcpy(buf + 0, uid, 4);
2101 num_to_bytes(nt, 4, buf + 4);
2102 memcpy(buf + 8, par_list, 8);
2103 memcpy(buf + 16, ks_list, 8);
2104 memcpy(buf + 24, mf_nr_ar, 4);
2105
2106 cmd_send(CMD_ACK,isOK,0,0,buf,28);
2107
2108 // Thats it...
2109 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2110 LEDsoff();
2111
2112 iso14a_set_tracing(FALSE);
2113 }
2114
2115 /**
2116 *MIFARE 1K simulate.
2117 *
2118 *@param flags :
2119 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2120 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2121 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2122 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2123 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2124 */
2125 void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
2126 {
2127 int cardSTATE = MFEMUL_NOFIELD;
2128 int _7BUID = 0;
2129 int vHf = 0; // in mV
2130 int res;
2131 uint32_t selTimer = 0;
2132 uint32_t authTimer = 0;
2133 uint32_t par = 0;
2134 int len = 0;
2135 uint8_t cardWRBL = 0;
2136 uint8_t cardAUTHSC = 0;
2137 uint8_t cardAUTHKEY = 0xff; // no authentication
2138 uint32_t cardRr = 0;
2139 uint32_t cuid = 0;
2140 //uint32_t rn_enc = 0;
2141 uint32_t ans = 0;
2142 uint32_t cardINTREG = 0;
2143 uint8_t cardINTBLOCK = 0;
2144 struct Crypto1State mpcs = {0, 0};
2145 struct Crypto1State *pcs;
2146 pcs = &mpcs;
2147 uint32_t numReads = 0;//Counts numer of times reader read a block
2148 uint8_t* receivedCmd = eml_get_bigbufptr_recbuf();
2149 uint8_t *response = eml_get_bigbufptr_sendbuf();
2150
2151 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2152 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2153 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2154 uint8_t rSAK[] = {0x08, 0xb6, 0xdd};
2155 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
2156
2157 uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};
2158 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
2159
2160 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
2161 // This can be used in a reader-only attack.
2162 // (it can also be retrieved via 'hf 14a list', but hey...
2163 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0};
2164 uint8_t ar_nr_collected = 0;
2165
2166 // clear trace
2167 iso14a_clear_trace();
2168 iso14a_set_tracing(TRUE);
2169
2170 // Authenticate response - nonce
2171 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
2172
2173 //-- Determine the UID
2174 // Can be set from emulator memory, incoming data
2175 // and can be 7 or 4 bytes long
2176 if (flags & FLAG_4B_UID_IN_DATA)
2177 {
2178 // 4B uid comes from data-portion of packet
2179 memcpy(rUIDBCC1,datain,4);
2180 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2181
2182 } else if (flags & FLAG_7B_UID_IN_DATA) {
2183 // 7B uid comes from data-portion of packet
2184 memcpy(&rUIDBCC1[1],datain,3);
2185 memcpy(rUIDBCC2, datain+3, 4);
2186 _7BUID = true;
2187 } else {
2188 // get UID from emul memory
2189 emlGetMemBt(receivedCmd, 7, 1);
2190 _7BUID = !(receivedCmd[0] == 0x00);
2191 if (!_7BUID) { // ---------- 4BUID
2192 emlGetMemBt(rUIDBCC1, 0, 4);
2193 } else { // ---------- 7BUID
2194 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2195 emlGetMemBt(rUIDBCC2, 3, 4);
2196 }
2197 }
2198
2199 /*
2200 * Regardless of what method was used to set the UID, set fifth byte and modify
2201 * the ATQA for 4 or 7-byte UID
2202 */
2203 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2204 if (_7BUID) {
2205 rATQA[0] = 0x44;
2206 rUIDBCC1[0] = 0x88;
2207 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2208 }
2209
2210 // We need to listen to the high-frequency, peak-detected path.
2211 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2212
2213
2214 if (MF_DBGLEVEL >= 1) {
2215 if (!_7BUID) {
2216 Dbprintf("4B UID: %02x%02x%02x%02x",rUIDBCC1[0] , rUIDBCC1[1] , rUIDBCC1[2] , rUIDBCC1[3]);
2217 } else {
2218 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",rUIDBCC1[0] , rUIDBCC1[1] , rUIDBCC1[2] , rUIDBCC1[3],rUIDBCC2[0],rUIDBCC2[1] ,rUIDBCC2[2] , rUIDBCC2[3]);
2219 }
2220 }
2221
2222 bool finished = FALSE;
2223 while (!BUTTON_PRESS() && !finished) {
2224 WDT_HIT();
2225
2226 // find reader field
2227 // Vref = 3300mV, and an 10:1 voltage divider on the input
2228 // can measure voltages up to 33000 mV
2229 if (cardSTATE == MFEMUL_NOFIELD) {
2230 vHf = (33000 * AvgAdc(ADC_CHAN_HF)) >> 10;
2231 if (vHf > MF_MINFIELDV) {
2232 cardSTATE_TO_IDLE();
2233 LED_A_ON();
2234 }
2235 }
2236 if(cardSTATE == MFEMUL_NOFIELD) continue;
2237
2238 //Now, get data
2239
2240 res = EmGetCmd(receivedCmd, &len);
2241 if (res == 2) { //Field is off!
2242 cardSTATE = MFEMUL_NOFIELD;
2243 LEDsoff();
2244 continue;
2245 } else if (res == 1) {
2246 break; //return value 1 means button press
2247 }
2248
2249 // REQ or WUP request in ANY state and WUP in HALTED state
2250 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2251 selTimer = GetTickCount();
2252 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2253 cardSTATE = MFEMUL_SELECT1;
2254
2255 // init crypto block
2256 LED_B_OFF();
2257 LED_C_OFF();
2258 crypto1_destroy(pcs);
2259 cardAUTHKEY = 0xff;
2260 continue;
2261 }
2262
2263 switch (cardSTATE) {
2264 case MFEMUL_NOFIELD:
2265 case MFEMUL_HALTED:
2266 case MFEMUL_IDLE:{
2267 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2268 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2269 break;
2270 }
2271 case MFEMUL_SELECT1:{
2272 // select all
2273 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
2274 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
2275 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
2276 break;
2277 }
2278
2279 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2280 {
2281 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2282 }
2283 // select card
2284 if (len == 9 &&
2285 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2286 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
2287 cuid = bytes_to_num(rUIDBCC1, 4);
2288 if (!_7BUID) {
2289 cardSTATE = MFEMUL_WORK;
2290 LED_B_ON();
2291 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2292 break;
2293 } else {
2294 cardSTATE = MFEMUL_SELECT2;
2295 }
2296 }
2297 break;
2298 }
2299 case MFEMUL_AUTH1:{
2300 if( len != 8)
2301 {
2302 cardSTATE_TO_IDLE();
2303 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2304 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2305 break;
2306 }
2307 uint32_t ar = bytes_to_num(receivedCmd, 4);
2308 uint32_t nr= bytes_to_num(&receivedCmd[4], 4);
2309
2310 //Collect AR/NR
2311 if(ar_nr_collected < 2){
2312 if(ar_nr_responses[2] != ar)
2313 {// Avoid duplicates... probably not necessary, ar should vary.
2314 ar_nr_responses[ar_nr_collected*4] = cuid;
2315 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2316 ar_nr_responses[ar_nr_collected*4+2] = ar;
2317 ar_nr_responses[ar_nr_collected*4+3] = nr;
2318 ar_nr_collected++;
2319 }
2320 }
2321
2322 // --- crypto
2323 crypto1_word(pcs, ar , 1);
2324 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2325
2326 // test if auth OK
2327 if (cardRr != prng_successor(nonce, 64)){
2328 if (MF_DBGLEVEL >= 2) Dbprintf("AUTH FAILED. cardRr=%08x, succ=%08x",cardRr, prng_successor(nonce, 64));
2329 // Shouldn't we respond anything here?
2330 // Right now, we don't nack or anything, which causes the
2331 // reader to do a WUPA after a while. /Martin
2332 // -- which is the correct response. /piwi
2333 cardSTATE_TO_IDLE();
2334 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2335 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2336 break;
2337 }
2338
2339 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2340
2341 num_to_bytes(ans, 4, rAUTH_AT);
2342 // --- crypto
2343 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2344 LED_C_ON();
2345 cardSTATE = MFEMUL_WORK;
2346 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2347 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2348 GetTickCount() - authTimer);
2349 break;
2350 }
2351 case MFEMUL_SELECT2:{
2352 if (!len) {
2353 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2354 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2355 break;
2356 }
2357 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
2358 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2359 break;
2360 }
2361
2362 // select 2 card
2363 if (len == 9 &&
2364 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2365 EmSendCmd(rSAK, sizeof(rSAK));
2366 cuid = bytes_to_num(rUIDBCC2, 4);
2367 cardSTATE = MFEMUL_WORK;
2368 LED_B_ON();
2369 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2370 break;
2371 }
2372
2373 // i guess there is a command). go into the work state.
2374 if (len != 4) {
2375 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2376 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2377 break;
2378 }
2379 cardSTATE = MFEMUL_WORK;
2380 //goto lbWORK;
2381 //intentional fall-through to the next case-stmt
2382 }
2383
2384 case MFEMUL_WORK:{
2385 if (len == 0) {
2386 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2387 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2388 break;
2389 }
2390
2391 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2392
2393 if(encrypted_data) {
2394 // decrypt seqence
2395 mf_crypto1_decrypt(pcs, receivedCmd, len);
2396 }
2397
2398 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2399 authTimer = GetTickCount();
2400 cardAUTHSC = receivedCmd[1] / 4; // received block num
2401 cardAUTHKEY = receivedCmd[0] - 0x60;
2402 crypto1_destroy(pcs);//Added by martin
2403 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
2404
2405 if (!encrypted_data) { // first authentication
2406 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2407
2408 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2409 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
2410 } else { // nested authentication
2411 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2412 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
2413 num_to_bytes(ans, 4, rAUTH_AT);
2414 }
2415 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2416 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2417 cardSTATE = MFEMUL_AUTH1;
2418 break;
2419 }
2420
2421 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2422 // BUT... ACK --> NACK
2423 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2424 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2425 break;
2426 }
2427
2428 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2429 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2430 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2431 break;
2432 }
2433
2434 if(len != 4) {
2435 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2436 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2437 break;
2438 }
2439
2440 if(receivedCmd[0] == 0x30 // read block
2441 || receivedCmd[0] == 0xA0 // write block
2442 || receivedCmd[0] == 0xC0 // inc
2443 || receivedCmd[0] == 0xC1 // dec
2444 || receivedCmd[0] == 0xC2 // restore
2445 || receivedCmd[0] == 0xB0) { // transfer
2446 if (receivedCmd[1] >= 16 * 4) {
2447 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2448 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2449 break;
2450 }
2451
2452 if (receivedCmd[1] / 4 != cardAUTHSC) {
2453 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2454 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
2455 break;
2456 }
2457 }
2458 // read block
2459 if (receivedCmd[0] == 0x30) {
2460 if (MF_DBGLEVEL >= 4) {
2461 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2462 }
2463 emlGetMem(response, receivedCmd[1], 1);
2464 AppendCrc14443a(response, 16);
2465 mf_crypto1_encrypt(pcs, response, 18, &par);
2466 EmSendCmdPar(response, 18, par);
2467 numReads++;
2468 if(exitAfterNReads > 0 && numReads == exitAfterNReads) {
2469 Dbprintf("%d reads done, exiting", numReads);
2470 finished = true;
2471 }
2472 break;
2473 }
2474 // write block
2475 if (receivedCmd[0] == 0xA0) {
2476 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
2477 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2478 cardSTATE = MFEMUL_WRITEBL2;
2479 cardWRBL = receivedCmd[1];
2480 break;
2481 }
2482 // increment, decrement, restore
2483 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
2484 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2485 if (emlCheckValBl(receivedCmd[1])) {
2486 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
2487 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2488 break;
2489 }
2490 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2491 if (receivedCmd[0] == 0xC1)
2492 cardSTATE = MFEMUL_INTREG_INC;
2493 if (receivedCmd[0] == 0xC0)
2494 cardSTATE = MFEMUL_INTREG_DEC;
2495 if (receivedCmd[0] == 0xC2)
2496 cardSTATE = MFEMUL_INTREG_REST;
2497 cardWRBL = receivedCmd[1];
2498 break;
2499 }
2500 // transfer
2501 if (receivedCmd[0] == 0xB0) {
2502 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2503 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2504 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2505 else
2506 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2507 break;
2508 }
2509 // halt
2510 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
2511 LED_B_OFF();
2512 LED_C_OFF();
2513 cardSTATE = MFEMUL_HALTED;
2514 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
2515 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2516 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2517 break;
2518 }
2519 // RATS
2520 if (receivedCmd[0] == 0xe0) {//RATS
2521 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2522 break;
2523 }
2524 // command not allowed
2525 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2526 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2527 break;
2528 }
2529 case MFEMUL_WRITEBL2:{
2530 if (len == 18){
2531 mf_crypto1_decrypt(pcs, receivedCmd, len);
2532 emlSetMem(receivedCmd, cardWRBL, 1);
2533 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2534 cardSTATE = MFEMUL_WORK;
2535 } else {
2536 cardSTATE_TO_IDLE();
2537 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2538 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2539 }
2540 break;
2541 }
2542
2543 case MFEMUL_INTREG_INC:{
2544 mf_crypto1_decrypt(pcs, receivedCmd, len);
2545 memcpy(&ans, receivedCmd, 4);
2546 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2547 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2548 cardSTATE_TO_IDLE();
2549 break;
2550 }
2551 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2552 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2553 cardINTREG = cardINTREG + ans;
2554 cardSTATE = MFEMUL_WORK;
2555 break;
2556 }
2557 case MFEMUL_INTREG_DEC:{
2558 mf_crypto1_decrypt(pcs, receivedCmd, len);
2559 memcpy(&ans, receivedCmd, 4);
2560 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2561 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2562 cardSTATE_TO_IDLE();
2563 break;
2564 }
2565 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2566 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2567 cardINTREG = cardINTREG - ans;
2568 cardSTATE = MFEMUL_WORK;
2569 break;
2570 }
2571 case MFEMUL_INTREG_REST:{
2572 mf_crypto1_decrypt(pcs, receivedCmd, len);
2573 memcpy(&ans, receivedCmd, 4);
2574 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2575 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2576 cardSTATE_TO_IDLE();
2577 break;
2578 }
2579 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parityBits, TRUE);
2580 LogTrace(NULL, 0, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, 0, TRUE);
2581 cardSTATE = MFEMUL_WORK;
2582 break;
2583 }
2584 }
2585 }
2586
2587 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2588 LEDsoff();
2589
2590 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2591 {
2592 //May just aswell send the collected ar_nr in the response aswell
2593 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,0,0,&ar_nr_responses,ar_nr_collected*4*4);
2594 }
2595
2596 if(flags & FLAG_NR_AR_ATTACK)
2597 {
2598 if(ar_nr_collected > 1) {
2599 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
2600 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
2601 ar_nr_responses[0], // UID
2602 ar_nr_responses[1], //NT
2603 ar_nr_responses[2], //AR1
2604 ar_nr_responses[3], //NR1
2605 ar_nr_responses[6], //AR2
2606 ar_nr_responses[7] //NR2
2607 );
2608 } else {
2609 Dbprintf("Failed to obtain two AR/NR pairs!");
2610 if(ar_nr_collected >0) {
2611 Dbprintf("Only got these: UID=%08x, nonce=%08x, AR1=%08x, NR1=%08x",
2612 ar_nr_responses[0], // UID
2613 ar_nr_responses[1], //NT
2614 ar_nr_responses[2], //AR1
2615 ar_nr_responses[3] //NR1
2616 );
2617 }
2618 }
2619 }
2620 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, traceLen);
2621 }
2622
2623
2624
2625 //-----------------------------------------------------------------------------
2626 // MIFARE sniffer.
2627 //
2628 //-----------------------------------------------------------------------------
2629 void RAMFUNC SniffMifare(uint8_t param) {
2630 // param:
2631 // bit 0 - trigger from first card answer
2632 // bit 1 - trigger from first reader 7-bit request
2633
2634 // C(red) A(yellow) B(green)
2635 LEDsoff();
2636 // init trace buffer
2637 iso14a_clear_trace();
2638 iso14a_set_tracing(TRUE);
2639
2640 // The command (reader -> tag) that we're receiving.
2641 // The length of a received command will in most cases be no more than 18 bytes.
2642 // So 32 should be enough!
2643 uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);
2644 // The response (tag -> reader) that we're receiving.
2645 uint8_t *receivedResponse = (((uint8_t *)BigBuf) + RECV_RES_OFFSET);
2646
2647 // As we receive stuff, we copy it from receivedCmd or receivedResponse
2648 // into trace, along with its length and other annotations.
2649 //uint8_t *trace = (uint8_t *)BigBuf;
2650
2651 // The DMA buffer, used to stream samples from the FPGA
2652 uint8_t *dmaBuf = ((uint8_t *)BigBuf) + DMA_BUFFER_OFFSET;
2653 uint8_t *data = dmaBuf;
2654 uint8_t previous_data = 0;
2655 int maxDataLen = 0;
2656 int dataLen = 0;
2657 bool ReaderIsActive = FALSE;
2658 bool TagIsActive = FALSE;
2659
2660 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2661
2662 // Set up the demodulator for tag -> reader responses.
2663 Demod.output = receivedResponse;
2664
2665 // Set up the demodulator for the reader -> tag commands
2666 Uart.output = receivedCmd;
2667
2668 // Setup for the DMA.
2669 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2670
2671 LED_D_OFF();
2672
2673 // init sniffer
2674 MfSniffInit();
2675
2676 // And now we loop, receiving samples.
2677 for(uint32_t sniffCounter = 0; TRUE; ) {
2678
2679 if(BUTTON_PRESS()) {
2680 DbpString("cancelled by button");
2681 break;
2682 }
2683
2684 LED_A_ON();
2685 WDT_HIT();
2686
2687 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2688 // check if a transaction is completed (timeout after 2000ms).
2689 // if yes, stop the DMA transfer and send what we have so far to the client
2690 if (MfSniffSend(2000)) {
2691 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2692 sniffCounter = 0;
2693 data = dmaBuf;
2694 maxDataLen = 0;
2695 ReaderIsActive = FALSE;
2696 TagIsActive = FALSE;
2697 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2698 }
2699 }
2700
2701 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2702 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2703 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2704 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2705 } else {
2706 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
2707 }
2708 // test for length of buffer
2709 if(dataLen > maxDataLen) { // we are more behind than ever...
2710 maxDataLen = dataLen;
2711 if(dataLen > 400) {
2712 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
2713 break;
2714 }
2715 }
2716 if(dataLen < 1) continue;
2717
2718 // primary buffer was stopped ( <-- we lost data!
2719 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2720 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2721 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
2722 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
2723 }
2724 // secondary buffer sets as primary, secondary buffer was stopped
2725 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2726 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
2727 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2728 }
2729
2730 LED_A_OFF();
2731
2732 if (sniffCounter & 0x01) {
2733
2734 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2735 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2736 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2737 LED_C_INV();
2738 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parityBits, Uart.bitCount, TRUE)) break;
2739
2740 /* And ready to receive another command. */
2741 UartReset();
2742
2743 /* And also reset the demod code */
2744 DemodReset();
2745 }
2746 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2747 }
2748
2749 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2750 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2751 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2752 LED_C_INV();
2753
2754 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parityBits, Demod.bitCount, FALSE)) break;
2755
2756 // And ready to receive another response.
2757 DemodReset();
2758 }
2759 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2760 }
2761 }
2762
2763 previous_data = *data;
2764 sniffCounter++;
2765 data++;
2766 if(data == dmaBuf + DMA_BUFFER_SIZE) {
2767 data = dmaBuf;
2768 }
2769
2770 } // main cycle
2771
2772 DbpString("COMMAND FINISHED");
2773
2774 FpgaDisableSscDma();
2775 MfSniffEnd();
2776
2777 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
2778 LEDsoff();
2779 }
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