cleanup clocks
[fpga-games] / galaxian / src / mc_clock.v
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1//---------------------------------------------------------------------\r
2// FPGA MOONCRESTA CLOCK GEN \r
3//\r
4// Version : 1.00\r
5//\r
6// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
7//\r
8// Important !\r
9//\r
10// This program is freeware for non-commercial use. \r
11// An author does no guarantee about this program.\r
12// You can use this under your own risk.\r
13//\r
14//---------------------------------------------------------------------\r
15\r
16\r
17\r
18module mc_clock(\r
19\r
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20I_CLK_36M,\r
21O_CLK_18M,\r
782690d0 22O_CLK_12M,\r
c3bcc38a 23O_CLK_06M\r
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24\r
25);\r
26\r
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27input I_CLK_36M;\r
28output O_CLK_18M;\r
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29output O_CLK_12M;\r
30output O_CLK_06M;\r
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31\r
32// 2/3 clock divider(duty 33%)\r
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33//I_CLK 1010101010101010101\r
34//c_ff10 0011110011110011110\r
35//c_ff11 0011000011000011000\r
36//c_ff20 0000110000110000110\r
37//c_ff21 0110000110000110000\r
38//O_12M 0000110110110110110\r
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39reg [1:0] state;\r
40reg clk_12m;\r
41initial state = 0;\r
42initial clk_12m = 0;\r
43\r
44// 2/3 clock (duty 66%)\r
45always @(negedge I_CLK_36M)\r
782690d0 46begin\r
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47 case (state)\r
48 2'd0: state <= 2'd1;\r
49 2'd1: state <= 2'd2;\r
50 2'd2: state <= 2'd0;\r
51 2'd3: state <= 2'd0;\r
52 endcase\r
53\r
54 if (state == 2'd2)\r
55 clk_12m = 1;\r
56 else\r
57 clk_12m = 0;\r
782690d0 58end\r
782690d0 59\r
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60assign O_CLK_12M = clk_12m;\r
61\r
62reg CLK_18M;\r
63always @(posedge I_CLK_36M)\r
64begin\r
65 CLK_18M <= ~ CLK_18M;\r
66end\r
67assign O_CLK_18M = CLK_18M;\r
68\r
782690d0 69// 1/3 clock divider (duty 50%)\r
c3bcc38a 70reg CLK_6M;\r
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71always @(posedge O_CLK_12M)\r
72begin\r
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73 CLK_6M <= ~CLK_6M;\r
74end\r
75assign O_CLK_06M = CLK_6M;\r
782690d0 76\r
c3bcc38a 77endmodule\r
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