cleanup clocks
[fpga-games] / galaxian / src / mc_clock.v
1 //---------------------------------------------------------------------
2 // FPGA MOONCRESTA CLOCK GEN
3 //
4 // Version : 1.00
5 //
6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
7 //
8 // Important !
9 //
10 // This program is freeware for non-commercial use.
11 // An author does no guarantee about this program.
12 // You can use this under your own risk.
13 //
14 //---------------------------------------------------------------------
15
16
17
18 module mc_clock(
19
20 I_CLK_36M,
21 O_CLK_18M,
22 O_CLK_12M,
23 O_CLK_06M
24
25 );
26
27 input I_CLK_36M;
28 output O_CLK_18M;
29 output O_CLK_12M;
30 output O_CLK_06M;
31
32 // 2/3 clock divider(duty 33%)
33 //I_CLK 1010101010101010101
34 //c_ff10 0011110011110011110
35 //c_ff11 0011000011000011000
36 //c_ff20 0000110000110000110
37 //c_ff21 0110000110000110000
38 //O_12M 0000110110110110110
39 reg [1:0] state;
40 reg clk_12m;
41 initial state = 0;
42 initial clk_12m = 0;
43
44 // 2/3 clock (duty 66%)
45 always @(negedge I_CLK_36M)
46 begin
47 case (state)
48 2'd0: state <= 2'd1;
49 2'd1: state <= 2'd2;
50 2'd2: state <= 2'd0;
51 2'd3: state <= 2'd0;
52 endcase
53
54 if (state == 2'd2)
55 clk_12m = 1;
56 else
57 clk_12m = 0;
58 end
59
60 assign O_CLK_12M = clk_12m;
61
62 reg CLK_18M;
63 always @(posedge I_CLK_36M)
64 begin
65 CLK_18M <= ~ CLK_18M;
66 end
67 assign O_CLK_18M = CLK_18M;
68
69 // 1/3 clock divider (duty 50%)
70 reg CLK_6M;
71 always @(posedge O_CLK_12M)
72 begin
73 CLK_6M <= ~CLK_6M;
74 end
75 assign O_CLK_06M = CLK_6M;
76
77 endmodule
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