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[fpga-games] / galaxian / src / mc_video.v
CommitLineData
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1//===============================================================================\r
2// FPGA GALAXIAN VIDEO\r
3//\r
4// Version : 2.50\r
5//\r
6// Copyright(c) 2004 Katsumi Degawa , All rights reserved\r
7//\r
8// Important !\r
9//\r
10// This program is freeware for non-commercial use. \r
11// An author does no guarantee about this program.\r
12// You can use this under your own risk.\r
13//\r
14// 2004- 4-30 galaxian modify by K.DEGAWA\r
15// 2004- 5- 6 first release.\r
16// 2004- 8-23 Improvement with T80-IP.\r
17// 2004- 9-22 The problem which missile didn't sometimes come out from was improved.\r
18//================================================================================\r
19//-----------------------------------------------------------------------------------------\r
20// H_CNT[0],H_CNT[1],H_CNT[2],H_CNT[3],H_CNT[4],H_CNT[5],H_CNT[6],H_CNT[7],H_CNT[8], \r
21// 1 H 2 H 4H 8H 16 H 32H 64 H 128 H 256 H\r
22//-----------------------------------------------------------------------------------------\r
23// V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7] \r
24// 1 V 2 V 4 V 8 V 16 V 32 V 64 V 128 V \r
25//-----------------------------------------------------------------------------------------\r
26\r
27module mc_video(\r
28\r
29I_CLK_18M,\r
30I_CLK_12M,\r
31I_CLK_6M,\r
4b3ff7d8 32I_CLK_6Mn,\r
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33I_H_CNT,\r
34I_V_CNT,\r
35I_H_FLIP,\r
36I_V_FLIP,\r
37I_V_BLn,\r
38I_C_BLn,\r
39\r
40I_A,\r
41I_OBJ_SUB_A,\r
42I_BD,\r
43I_OBJ_RAM_RQn,\r
44I_OBJ_RAM_RDn,\r
45I_OBJ_RAM_WRn,\r
46I_VID_RAM_RDn,\r
47I_VID_RAM_WRn,\r
48\r
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49O_C_BLnX,\r
50O_8HF,\r
51O_256HnX,\r
52O_1VF,\r
53O_MISSILEn,\r
54O_SHELLn,\r
55O_BD,\r
56O_VID,\r
57O_COL\r
58\r
59);\r
60\r
61input I_CLK_18M;\r
62input I_CLK_12M;\r
63input I_CLK_6M;\r
4b3ff7d8 64input I_CLK_6Mn;\r
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65input [8:0]I_H_CNT;\r
66input [7:0]I_V_CNT;\r
67input I_H_FLIP;\r
68input I_V_FLIP;\r
69input I_V_BLn;\r
70input I_C_BLn;\r
71\r
72input [9:0]I_A;\r
73input [7:0]I_BD;\r
74input [2:0]I_OBJ_SUB_A;\r
75input I_OBJ_RAM_RQn;\r
76input I_OBJ_RAM_RDn;\r
77input I_OBJ_RAM_WRn;\r
78input I_VID_RAM_RDn;\r
79input I_VID_RAM_WRn;\r
80\r
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81output O_C_BLnX;\r
82output O_8HF;\r
83output O_256HnX;\r
84output O_1VF;\r
85output O_MISSILEn;\r
86output O_SHELLn;\r
87\r
88output [7:0]O_BD;\r
89output [1:0]O_VID;\r
90output [2:0]O_COL;\r
91\r
92wire WB_LDn;\r
93wire WB_CNTRLDn;\r
94wire WB_CNTRCLRn;\r
95wire WB_COLLn;\r
96wire WB_VPLn;\r
97wire WB_OBJDATALn;\r
98wire WB_MLDn;\r
99wire WB_SLDn;\r
100wire W_3D;\r
101reg W_LDn;\r
102reg W_CNTRLDn;\r
103reg W_CNTRCLRn;\r
104reg W_COLLn;\r
105reg W_VPLn;\r
106reg W_OBJDATALn;\r
107reg W_MLDn;\r
108reg W_SLDn;\r
109\r
110always@(negedge I_CLK_12M)\r
111begin\r
112 W_LDn <= WB_LDn;\r
113 W_CNTRLDn <= WB_CNTRLDn;\r
114 W_CNTRCLRn <= WB_CNTRCLRn;\r
115 W_COLLn <= WB_COLLn;\r
116 W_VPLn <= WB_VPLn;\r
117 W_OBJDATALn <= WB_OBJDATALn;\r
118 W_MLDn <= WB_MLDn;\r
119 W_SLDn <= WB_SLDn;\r
120end\r
121\r
122mc_ld_pls LD_PLS(\r
123\r
c3bcc38a 124.I_CLK_6M(I_CLK_6M),\r
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125.I_H_CNT(I_H_CNT),\r
126.I_3D_DI(W_3D),\r
127\r
128.O_LDn(WB_LDn),\r
129.O_CNTRLDn(WB_CNTRLDn),\r
130.O_CNTRCLRn(WB_CNTRCLRn),\r
131.O_COLLn(WB_COLLn),\r
132.O_VPLn(WB_VPLn),\r
133.O_OBJDATALn(WB_OBJDATALn),\r
134.O_MLDn(WB_MLDn),\r
135.O_SLDn(WB_SLDn)\r
136\r
137);\r
138\r
139wire W_H_FLIP1 = ~I_H_CNT[8]&I_H_FLIP;\r
140\r
141wire [7:3]W_HF_CNT = I_H_CNT[7:3]^{5{W_H_FLIP1}};\r
142wire [7:0]W_VF_CNT = I_V_CNT[7:0]^{8{I_V_FLIP}};\r
143\r
144assign O_8HF = W_HF_CNT[3];\r
b884ab49 145assign O_1VF = W_VF_CNT[0];\r
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146\r
147reg [7:0]W_OBJ_D;\r
148wire [3:0]W_6J_DA = {I_H_FLIP , W_HF_CNT[7],W_HF_CNT[3],I_H_CNT[2]};\r
149wire [3:0]W_6J_DB = {W_OBJ_D[6],W_HF_CNT[3]&I_H_CNT[1], I_H_CNT[2],I_H_CNT[1]};\r
150wire [3:0]W_6J_Q = I_H_CNT[8] ? W_6J_DB:W_6J_DA;\r
151\r
152wire W_H_FLIP2 = W_6J_Q[3];\r
153// Prats 4F,5F\r
154wire [7:0]W_OBJ_RAM_AB = {1'b0,I_H_CNT[8],W_6J_Q[2],W_HF_CNT[6:4],W_6J_Q[1:0]};\r
155wire [7:0]W_OBJ_RAM_A = I_OBJ_RAM_RQn ? W_OBJ_RAM_AB: I_A[7:0] ;\r
156\r
157wire [7:0]W_OBJ_RAM_DOA,W_OBJ_RAM_DOB;\r
158\r
159reg [7:0]W_H_POSI;\r
deb5ffdc 160always@(posedge I_CLK_12M) W_H_POSI <= W_OBJ_RAM_DOB;\r
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161\r
162mc_obj_ram OBJ_RAM(\r
163\r
164.I_CLKA(I_CLK_12M),\r
165.I_ADDRA(I_A[7:0]),\r
166.I_WEA(~I_OBJ_RAM_WRn),\r
167.I_CEA(~I_OBJ_RAM_RQn),\r
168.I_DA(I_BD),\r
169.O_DA(W_OBJ_RAM_DOA),\r
170\r
171.I_CLKB(I_CLK_12M),\r
172.I_ADDRB(W_OBJ_RAM_AB),\r
173.I_WEB(1'b0),\r
174.I_CEB(1'b1),\r
175.I_DB(8'h00),\r
176.O_DB(W_OBJ_RAM_DOB)\r
177\r
178);\r
179\r
180wire [7:0]W_OBJ_RAM_D = I_OBJ_RAM_RDn ? 8'h00: W_OBJ_RAM_DOA;\r
181// Prats 4L\r
182always@(posedge W_OBJDATALn) W_OBJ_D <= W_H_POSI; \r
183// Prats 4,5N\r
184\r
185wire [8:0]W_45N_Q = W_VF_CNT[7:0] + W_H_POSI ;\r
186assign W_3D = ~(&W_45N_Q[7:0]); \r
187\r
188reg [7:0]W_2M_Q;\r
189always@(posedge W_VPLn or negedge I_V_BLn)\r
190begin\r
191 if(I_V_BLn==1'b0)\r
192 W_2M_Q <= 0;\r
193 else\r
194 W_2M_Q <= W_45N_Q[7:0];\r
195end\r
196\r
197wire W_2N = I_H_CNT[8]&W_OBJ_D[7];\r
198wire [3:0]W_1M = W_2M_Q[3:0]^{W_2N,W_2N,W_2N,W_2N};\r
199\r
200wire W_VID_RAM_CSn = I_VID_RAM_RDn & I_VID_RAM_WRn;\r
201\r
202wire [7:0]W_VID_RAM_DI = I_VID_RAM_WRn ? 8'h00 : I_BD ;\r
203wire [7:0]W_VID_RAM_DOA;\r
204\r
205wire [11:0]W_VID_RAM_AA = {~(&W_2M_Q[7:4]),W_VID_RAM_CSn, 10'h00 /*I_A[9:0]*/};\r
206wire [11:0]W_VID_RAM_AB = { 1'b0, 1'b0,W_2M_Q[7:4],W_1M[3],W_HF_CNT[7:3]};\r
207\r
208wire [11:0]W_VID_RAM_A = I_C_BLn ? W_VID_RAM_AB:W_VID_RAM_AA;\r
209\r
210wire [7:0]W_VID_RAM_D = I_VID_RAM_RDn ? 8'h00 :W_VID_RAM_DOA;\r
211\r
212wire [7:0]W_VID_RAM_DOB;\r
213\r
214mc_vid_ram VID_RAM(\r
215\r
216.I_CLKA(I_CLK_12M),\r
217.I_ADDRA(I_A[9:0]),\r
218.I_DA(W_VID_RAM_DI),\r
219.I_WEA(~I_VID_RAM_WRn),\r
220.I_CEA(~W_VID_RAM_CSn),\r
221.O_DA(W_VID_RAM_DOA),\r
222\r
223.I_CLKB(I_CLK_12M),\r
224.I_ADDRB(W_VID_RAM_A[9:0]),\r
225.I_DB(8'h00),\r
226.I_WEB(1'b0),\r
227.I_CEB(1'b1),\r
228.O_DB(W_VID_RAM_DOB)\r
229\r
230);\r
231//-- VIDEO DATA OUTPUT --------------\r
232assign O_BD = W_OBJ_RAM_D | W_VID_RAM_D;\r
233\r
234wire W_SRLD = ~(W_LDn | W_VID_RAM_A[11]);\r
235\r
236wire [7:0]W_OBJ_ROM_AB = {W_OBJ_D[5:0],W_1M[3],W_OBJ_D[6]^I_H_CNT[3]};\r
237\r
238wire [7:0]W_OBJ_ROM_A = I_H_CNT[8] ? W_OBJ_ROM_AB: W_VID_RAM_DOB;\r
239\r
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240wire [10:0]W_O_OBJ_ROM_A = {W_OBJ_ROM_A,W_1M[2:0]};\r
241\r
242wire [7:0]W_1K_D;\r
243wire [7:0]W_1H_D;\r
244\r
245//1K VID-Rom\r
246GALAXIAN_1K K_ROM(\r
247.CLK(I_CLK_12M),\r
248.ADDR(W_O_OBJ_ROM_A),\r
249.DATA(W_1K_D),\r
250.ENA(1'b1)\r
251);\r
252\r
253//1H VID-Rom\r
254GALAXIAN_1H H_ROM(\r
255.CLK(I_CLK_12M),\r
256.ADDR(W_O_OBJ_ROM_A),\r
257.DATA(W_1H_D),\r
258.ENA(1'b1)\r
259);\r
782690d0 260\r
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261\r
262//---------------------------------------------------------------------------------\r
263wire W_2L_Qa,W_2K_Qd;\r
264wire W_2J_Qa,W_2H_Qd;\r
265wire W_H_FLIP2X;\r
266\r
267wire [3:0]W_3L_A = {W_2J_Qa,W_2L_Qa, 1'b1,W_SRLD};\r
268wire [3:0]W_3L_B = {W_2H_Qd,W_2K_Qd,W_SRLD, 1'b1}; \r
269wire [3:0]W_3L_Y = W_H_FLIP2X ? W_3L_B: W_3L_A; // [3]=RAW1,[2]=RAW0\r
270\r
271wire W_RAW0 = W_3L_Y[2];\r
272wire W_RAW1 = W_3L_Y[3];\r
273\r
274wire W_SRCLK = I_CLK_6M;\r
275//------ PARTS 2KL ---------------------------------------------- \r
276wire [1:0]C_2KL = W_3L_Y[1:0];\r
277wire [7:0]I_2KL = W_1K_D;\r
278reg [7:0]reg_2KL;\r
279\r
280assign W_2L_Qa = reg_2KL[7];\r
281assign W_2K_Qd = reg_2KL[0];\r
282always@(posedge W_SRCLK)\r
283begin\r
284 case(C_2KL)\r
285 2'b00: reg_2KL <= reg_2KL;\r
286 2'b10: reg_2KL <= {reg_2KL[6:0],1'b0};\r
287 2'b01: reg_2KL <= {1'b0,reg_2KL[7:1]};\r
288 2'b11: reg_2KL <= I_2KL;\r
289 endcase\r
290end\r
291//------ PARTS 2HJ ---------------------------------------------- \r
292wire [1:0]C_2HJ = W_3L_Y[1:0];\r
293wire [7:0]I_2HJ = W_1H_D;\r
294reg [7:0]reg_2HJ;\r
295\r
296assign W_2J_Qa = reg_2HJ[7];\r
297assign W_2H_Qd = reg_2HJ[0];\r
298always@(posedge W_SRCLK)\r
299begin\r
300 case(C_2HJ)\r
301 2'b00: reg_2HJ <= reg_2HJ;\r
302 2'b10: reg_2HJ <= {reg_2HJ[6:0],1'b0};\r
303 2'b01: reg_2HJ <= {1'b0,reg_2HJ[7:1]};\r
304 2'b11: reg_2HJ <= I_2HJ;\r
305 endcase\r
306end\r
307\r
308//----- SHT2 -----------------------------------------------------\r
309// Prats 6K\r
310reg [2:0]W_6K_Q;\r
311always@(posedge W_COLLn) W_6K_Q <= W_H_POSI[2:0];\r
312\r
313// Prats 6P\r
314reg [6:0]W_6P_Q;\r
315always@(posedge I_CLK_6M)\r
316begin\r
317 if(W_LDn==1'b0) W_6P_Q <= {W_H_FLIP2,W_H_FLIP1,I_C_BLn,~I_H_CNT[8],W_6K_Q[2:0]};\r
318 else W_6P_Q <= W_6P_Q;\r
319end\r
320\r
321assign W_H_FLIP2X = W_6P_Q[6];\r
322wire W_H_FLIP1X = W_6P_Q[5];\r
323wire W_C_BLnX = W_6P_Q[4];\r
324wire W_256HnX = W_6P_Q[3];\r
325wire [2:0]W_CD = W_6P_Q[2:0];\r
326\r
327assign O_256HnX = W_256HnX;\r
328assign O_C_BLnX = W_C_BLnX;\r
329\r
330wire W_45T_CLR = W_CNTRCLRn | W_256HnX ;\r
331reg [7:0]W_45T_Q;\r
332\r
333always@(posedge I_CLK_6M)\r
334begin\r
335 if(W_45T_CLR==1'b0)\r
336 W_45T_Q <= 0;\r
337 else if(W_CNTRLDn==1'b0)\r
338 W_45T_Q <= W_H_POSI;\r
339 else\r
340 W_45T_Q <= W_45T_Q + 1;\r
341end\r
342\r
343wire [7:0]W_LRAM_A = W_45T_Q^{8{W_H_FLIP1X}};\r
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344\r
345wire [4:0]W_LRAM_DI;\r
346wire [4:0]W_LRAM_DO;\r
347\r
348reg [1:0]W_RV;\r
349reg [2:0]W_RC;\r
782690d0 350\r
c3bcc38a 351always@(negedge I_CLK_6M)\r
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352begin\r
353 W_RV <= W_LRAM_DO[1:0]; \r
354 W_RC <= W_LRAM_DO[4:2];\r
355end\r
356\r
357wire W_LRAM_AND = ~(~((W_LRAM_A[4]|W_LRAM_A[5])|(W_LRAM_A[6]|W_LRAM_A[7]))|W_256HnX );\r
358wire W_RAW_OR = W_RAW0 | W_RAW1 ;\r
359\r
360wire [1:0]W_VID;\r
361wire [2:0]W_COL;\r
362\r
363assign W_VID[0] = ~(~(W_RAW0&W_RV[1])&W_RV[0]);\r
364assign W_VID[1] = ~(~(W_RAW1&W_RV[0])&W_RV[1]);\r
365assign W_COL[0] = ~(~(W_RAW_OR&W_CD[0]&W_RC[1]&W_RC[2])&W_RC[0]);\r
366assign W_COL[1] = ~(~(W_RAW_OR&W_CD[1]&W_RC[2]&W_RC[0])&W_RC[1]);\r
367assign W_COL[2] = ~(~(W_RAW_OR&W_CD[2]&W_RC[0]&W_RC[1])&W_RC[2]);\r
368\r
369assign O_VID = W_VID;\r
370assign O_COL = W_COL;\r
371\r
372assign W_LRAM_DI[0] = W_LRAM_AND&W_VID[0];\r
373assign W_LRAM_DI[1] = W_LRAM_AND&W_VID[1]; \r
374assign W_LRAM_DI[2] = W_LRAM_AND&W_COL[0];\r
375assign W_LRAM_DI[3] = W_LRAM_AND&W_COL[1];\r
376assign W_LRAM_DI[4] = W_LRAM_AND&W_COL[2];\r
377\r
378mc_lram LRAM(\r
379\r
380.I_CLK(I_CLK_18M),\r
381.I_ADDR(W_LRAM_A),\r
4b3ff7d8 382.I_WE(I_CLK_6Mn),\r
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383.I_D(W_LRAM_DI),\r
384.O_Dn(W_LRAM_DO)\r
385\r
386);\r
387\r
388mc_missile MISSILE(\r
389\r
390.I_CLK_18M(I_CLK_18M),\r
391.I_CLK_6M(I_CLK_6M),\r
392.I_C_BLn_X(W_C_BLnX),\r
393.I_MLDn(W_MLDn),\r
394.I_SLDn(W_SLDn),\r
395.I_HPOS(W_H_POSI),\r
396\r
397.O_MISSILEn(O_MISSILEn),\r
398.O_SHELLn(O_SHELLn)\r
399\r
400);\r
401\r
402endmodule\r
403\r
404\r
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