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   1 // megafunction wizard: %RAM: 1-PORT%
   2 // GENERATION: STANDARD
   3 // VERSION: WM1.0
   4 // MODULE: altsyncram
   5
   6 // ============================================================
   7 // File Name: alt_ram_256_5.v
   8 // Megafunction Name(s):
   9 //                      altsyncram
  10 // ============================================================
  11 // ************************************************************
  12 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
  13 // ************************************************************
  14
  15
  16 //Copyright (C) 1991-2003 Altera Corporation
  17 //Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
  18 //support information,  device programming or simulation file,  and any other
  19 //associated  documentation or information  provided by  Altera  or a partner
  20 //under  Altera's   Megafunction   Partnership   Program  may  be  used  only
  21 //to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
  22 //other  use  of such  megafunction  design,  netlist,  support  information,
  23 //device programming or simulation file,  or any other  related documentation
  24 //or information  is prohibited  for  any  other purpose,  including, but not
  25 //limited to  modification,  reverse engineering,  de-compiling, or use  with
  26 //any other  silicon devices,  unless such use is  explicitly  licensed under
  27 //a separate agreement with  Altera  or a megafunction partner.  Title to the
  28 //intellectual property,  including patents,  copyrights,  trademarks,  trade
  29 //secrets,  or maskworks,  embodied in any such megafunction design, netlist,
  30 //support  information,  device programming or simulation file,  or any other
  31 //related documentation or information provided by  Altera  or a megafunction
  32 //partner, remains with Altera, the megafunction partner, or their respective
  33 //licensors. No other licenses, including any licenses needed under any third
  34 //party's intellectual property, are provided herein.
  35
  36
  37 module alt_ram_256_5 (
  38         address,
  39         inclock,
  40         outclock,
  41         data,
  42         wren,
  43         q);
  44
  45         input   [7:0]  address;
  46         input     inclock;
  47         input     outclock;
  48         input   [4:0]  data;
  49         input     wren;
  50         output  [4:0]  q;
  51
  52         wire [4:0] sub_wire0;
  53         wire [4:0] q = sub_wire0[4:0];
  54
  55         altsyncram      altsyncram_component (
  56                                 .wren_a (wren),
  57                                 .clock0 (inclock),
  58                                 .clock1 (outclock),
  59                                 .address_a (address),
  60                                 .data_a (data),
  61                                 .q_a (sub_wire0));
  62         defparam
  63                 altsyncram_component.intended_device_family = "Cyclone",
  64                 altsyncram_component.width_a = 5,
  65                 altsyncram_component.widthad_a = 8,
  66                 altsyncram_component.numwords_a = 256,
  67                 altsyncram_component.operation_mode = "SINGLE_PORT",
  68                 altsyncram_component.outdata_reg_a = "CLOCK1",
  69                 altsyncram_component.indata_aclr_a = "NONE",
  70                 altsyncram_component.wrcontrol_aclr_a = "NONE",
  71                 altsyncram_component.address_aclr_a = "NONE",
  72                 altsyncram_component.outdata_aclr_a = "NONE",
  73                 altsyncram_component.width_byteena_a = 1,
  74                 altsyncram_component.ram_block_type = "AUTO",
  75                 altsyncram_component.use_eab = "ON",
  76                 altsyncram_component.lpm_type = "altsyncram";
  77
  78
  79 endmodule
  80
  81 // ============================================================
  82 // CNX file retrieval info
  83 // ============================================================
  84 // Retrieval info: PRIVATE: WidthData NUMERIC "5"
  85 // Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
  86 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
  87 // Retrieval info: PRIVATE: SingleClock NUMERIC "0"
  88 // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
  89 // Retrieval info: PRIVATE: RegData NUMERIC "1"
  90 // Retrieval info: PRIVATE: RegAddr NUMERIC "1"
  91 // Retrieval info: PRIVATE: RegOutput NUMERIC "1"
  92 // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
  93 // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
  94 // Retrieval info: PRIVATE: AclrByte NUMERIC "0"
  95 // Retrieval info: PRIVATE: AclrData NUMERIC "0"
  96 // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
  97 // Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
  98 // Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
  99 // Retrieval info: PRIVATE: Clken NUMERIC "0"
 100 // Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
 101 // Retrieval info: PRIVATE: MIFfilename STRING ""
 102 // Retrieval info: PRIVATE: UseLCs NUMERIC "0"
 103 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 104 // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
 105 // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
 106 // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
 107 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
 108 // Retrieval info: CONSTANT: WIDTH_A NUMERIC "5"
 109 // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
 110 // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
 111 // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
 112 // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK1"
 113 // Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
 114 // Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
 115 // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
 116 // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
 117 // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
 118 // Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"
 119 // Retrieval info: CONSTANT: USE_EAB STRING "ON"
 120 // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
 121 // Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
 122 // Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0]
 123 // Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT NODEFVAL inclock
 124 // Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT NODEFVAL outclock
 125 // Retrieval info: USED_PORT: data 0 0 5 0 INPUT NODEFVAL data[4..0]
 126 // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
 127 // Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
 128 // Retrieval info: CONNECT: q 0 0 5 0 @q_a 0 0 5 0
 129 // Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0
 130 // Retrieval info: CONNECT: @clock1 0 0 0 0 outclock 0 0 0 0
 131 // Retrieval info: CONNECT: @data_a 0 0 5 0 data 0 0 5 0
 132 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
 133 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all