galaxians
[fpga-games] / galaxian / src / mc_col_pal.v
1 //===============================================================================
2 // FPGA MOONCRESTA COLOR-PALETTE
3 //
4 // Version : 2.00
5 //
6 // Copyright(c) 2004 Katsumi Degawa , All rights reserved
7 //
8 // Important !
9 //
10 // This program is freeware for non-commercial use.
11 // An author does no guarantee about this program.
12 // You can use this under your own risk.
13 //
14 // 2004- 9-18 added Xilinx Device. K.Degawa
15 //================================================================================
16 `include "src/mc_conf.v"
17
18 module mc_col_pal(
19
20 I_CLK_12M,
21 I_CLK_6M,
22 I_VID,
23 I_COL,
24 I_C_BLnX,
25
26 O_C_BLX,
27 O_STARS_OFFn,
28 O_R,
29 O_G,
30 O_B
31
32 );
33
34 input I_CLK_12M;
35 input I_CLK_6M;
36 input [1:0]I_VID;
37 input [2:0]I_COL;
38 input I_C_BLnX;
39
40 output O_C_BLX;
41 output O_STARS_OFFn;
42 output [2:0]O_R;
43 output [2:0]O_G;
44 output [1:0]O_B;
45
46 //--- Parts 6M --------------------------------------------------------
47 wire [6:0]W_6M_DI = {I_COL[2:0],I_VID[1:0],~(I_VID[0]|I_VID[1]),I_C_BLnX};
48 reg [6:0]W_6M_DO;
49
50 wire W_6M_CLR = W_6M_DI[0]|W_6M_DO[0];
51 assign O_C_BLX = ~(W_6M_DI[0]|W_6M_DO[0]);
52 assign O_STARS_OFFn = W_6M_DO[1];
53
54 always@(posedge I_CLK_6M or negedge W_6M_CLR)
55 begin
56 if(W_6M_CLR==1'b0)
57 W_6M_DO <= 7'h00;
58 else
59 W_6M_DO <= W_6M_DI;
60 end
61 //--- COL ROM --------------------------------------------------------
62 wire [4:0]W_COL_ROM_A = W_6M_DO[6:2];
63 wire [7:0]W_COL_ROM_DO;
64 wire W_COL_ROM_OEn = W_6M_DO[1];
65
66 `ifdef DEVICE_CYCLONE
67 mc_col_rom COL_ROM(
68
69 .I_CLK(I_CLK_12M),
70 .I_ADDR(W_COL_ROM_A),
71 .O_DO(W_COL_ROM_DO),
72 .I_OEn(W_COL_ROM_OEn)
73
74 );
75 `endif
76 `ifdef DEVICE_SPARTAN2E
77 GALAXIAN_6L COL_ROM(
78 .CLK(I_CLK_12M),
79 .ADDR(W_COL_ROM_A),
80 .DATA(W_COL_ROM_DO),
81 .ENA(1'b1)
82 );
83 //RAMB4_S8 col_rom00(
84 //
85 //.CLK(I_CLK_12M),
86 //.ADDR({4'b0000,W_COL_ROM_A[4:0]}),
87 //.DI(8'h00),
88 //.DO(W_COL_ROM_DO),
89 //.EN(1'b1),
90 //.WE(1'b0),
91 //.RST(1'b0)
92 //
93 //);
94 `endif
95 //--- VID OUT --------------------------------------------------------
96 assign O_R[0] = W_COL_ROM_DO[2];
97 assign O_R[1] = W_COL_ROM_DO[1];
98 assign O_R[2] = W_COL_ROM_DO[0];
99
100 assign O_G[0] = W_COL_ROM_DO[5];
101 assign O_G[1] = W_COL_ROM_DO[4];
102 assign O_G[2] = W_COL_ROM_DO[3];
103
104 assign O_B[0] = W_COL_ROM_DO[7];
105 assign O_B[1] = W_COL_ROM_DO[6];
106
107
108 endmodule
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