2 -- Z80 compatible microprocessor core
6 -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
10 -- Redistribution and use in source and synthezised forms, with or without
11 -- modification, are permitted provided that the following conditions are met:
13 -- Redistributions of source code must retain the above copyright notice,
14 -- this list of conditions and the following disclaimer.
16 -- Redistributions in synthesized form must reproduce the above copyright
17 -- notice, this list of conditions and the following disclaimer in the
18 -- documentation and/or other materials provided with the distribution.
20 -- Neither the name of the author nor the names of other contributors may
21 -- be used to endorse or promote products derived from this software without
22 -- specific prior written permission.
24 -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
28 -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 -- POSSIBILITY OF SUCH DAMAGE.
36 -- Please report bugs to the author, but before you do so, please
37 -- make sure that this is not a derivative work and that
38 -- you have the latest version of this file.
40 -- The latest version of this file can be found at:
41 -- http://www.opencores.org/cvsweb.shtml/t80/
47 -- 0208 : First complete release
49 -- 0210 : Fixed wait and halt
51 -- 0211 : Fixed Refresh addition and IM 1
53 -- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
55 -- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
57 -- 0235 : Added clock enable and IM 2 fix by Mike Johnson
59 -- 0237 : Changed 8080 I/O address output, added IntE output
61 -- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
63 -- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
65 -- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
67 -- 0247 : Fixed bus req/ack cycle
71 use IEEE.std_logic_1164.all;
72 use IEEE.numeric_std.all;
73 use work.T80_Pack.all;
77 Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
78 IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
79 Flag_C : integer := 0;
80 Flag_N : integer := 1;
81 Flag_P : integer := 2;
82 Flag_X : integer := 3;
83 Flag_H : integer := 4;
84 Flag_Y : integer := 5;
85 Flag_Z : integer := 6;
89 RESET_n : in std_logic;
92 WAIT_n : in std_logic;
95 BUSRQ_n : in std_logic;
98 NoRead : out std_logic;
99 Write : out std_logic;
100 RFSH_n : out std_logic;
101 HALT_n : out std_logic;
102 BUSAK_n : out std_logic;
103 A : out std_logic_vector(15 downto 0);
104 DInst : in std_logic_vector(7 downto 0);
105 DI : in std_logic_vector(7 downto 0);
106 DO : out std_logic_vector(7 downto 0);
107 MC : out std_logic_vector(2 downto 0);
108 TS : out std_logic_vector(2 downto 0);
109 IntCycle_n : out std_logic;
110 IntE : out std_logic;
115 architecture rtl of T80 is
117 constant aNone : std_logic_vector(2 downto 0) := "111";
118 constant aBC : std_logic_vector(2 downto 0) := "000";
119 constant aDE : std_logic_vector(2 downto 0) := "001";
120 constant aXY : std_logic_vector(2 downto 0) := "010";
121 constant aIOA : std_logic_vector(2 downto 0) := "100";
122 constant aSP : std_logic_vector(2 downto 0) := "101";
123 constant aZI : std_logic_vector(2 downto 0) := "110";
126 signal ACC, F : std_logic_vector(7 downto 0);
127 signal Ap, Fp : std_logic_vector(7 downto 0);
128 signal I : std_logic_vector(7 downto 0);
129 signal R : unsigned(7 downto 0);
130 signal SP, PC : unsigned(15 downto 0);
131 signal RegDIH : std_logic_vector(7 downto 0);
132 signal RegDIL : std_logic_vector(7 downto 0);
133 signal RegBusA : std_logic_vector(15 downto 0);
134 signal RegBusB : std_logic_vector(15 downto 0);
135 signal RegBusC : std_logic_vector(15 downto 0);
136 signal RegAddrA_r : std_logic_vector(2 downto 0);
137 signal RegAddrA : std_logic_vector(2 downto 0);
138 signal RegAddrB_r : std_logic_vector(2 downto 0);
139 signal RegAddrB : std_logic_vector(2 downto 0);
140 signal RegAddrC : std_logic_vector(2 downto 0);
141 signal RegWEH : std_logic;
142 signal RegWEL : std_logic;
143 signal Alternate : std_logic;
146 signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
147 signal IR : std_logic_vector(7 downto 0); -- Instruction register
148 signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
149 signal RegBusA_r : std_logic_vector(15 downto 0);
151 signal ID16 : signed(15 downto 0);
152 signal Save_Mux : std_logic_vector(7 downto 0);
154 signal TState : unsigned(2 downto 0);
155 signal MCycle : std_logic_vector(2 downto 0);
156 signal IntE_FF1 : std_logic;
157 signal IntE_FF2 : std_logic;
158 signal Halt_FF : std_logic;
159 signal BusReq_s : std_logic;
160 signal BusAck : std_logic;
161 signal ClkEn : std_logic;
162 signal NMI_s : std_logic;
163 signal INT_s : std_logic;
164 signal IStatus : std_logic_vector(1 downto 0);
166 signal DI_Reg : std_logic_vector(7 downto 0);
167 signal T_Res : std_logic;
168 signal XY_State : std_logic_vector(1 downto 0);
169 signal Pre_XY_F_M : std_logic_vector(2 downto 0);
170 signal NextIs_XY_Fetch : std_logic;
171 signal XY_Ind : std_logic;
172 signal No_BTR : std_logic;
173 signal BTR_r : std_logic;
174 signal Auto_Wait : std_logic;
175 signal Auto_Wait_t1 : std_logic;
176 signal Auto_Wait_t2 : std_logic;
177 signal IncDecZ : std_logic;
180 signal BusB : std_logic_vector(7 downto 0);
181 signal BusA : std_logic_vector(7 downto 0);
182 signal ALU_Q : std_logic_vector(7 downto 0);
183 signal F_Out : std_logic_vector(7 downto 0);
185 -- Registered micro code outputs
186 signal Read_To_Reg_r : std_logic_vector(4 downto 0);
187 signal Arith16_r : std_logic;
188 signal Z16_r : std_logic;
189 signal ALU_Op_r : std_logic_vector(3 downto 0);
190 signal Save_ALU_r : std_logic;
191 signal PreserveC_r : std_logic;
192 signal MCycles : std_logic_vector(2 downto 0);
194 -- Micro code outputs
195 signal MCycles_d : std_logic_vector(2 downto 0);
196 signal TStates : std_logic_vector(2 downto 0);
197 signal IntCycle : std_logic;
198 signal NMICycle : std_logic;
199 signal Inc_PC : std_logic;
200 signal Inc_WZ : std_logic;
201 signal IncDec_16 : std_logic_vector(3 downto 0);
202 signal Prefix : std_logic_vector(1 downto 0);
203 signal Read_To_Acc : std_logic;
204 signal Read_To_Reg : std_logic;
205 signal Set_BusB_To : std_logic_vector(3 downto 0);
206 signal Set_BusA_To : std_logic_vector(3 downto 0);
207 signal ALU_Op : std_logic_vector(3 downto 0);
208 signal Save_ALU : std_logic;
209 signal PreserveC : std_logic;
210 signal Arith16 : std_logic;
211 signal Set_Addr_To : std_logic_vector(2 downto 0);
212 signal Jump : std_logic;
213 signal JumpE : std_logic;
214 signal JumpXY : std_logic;
215 signal Call : std_logic;
216 signal RstP : std_logic;
217 signal LDZ : std_logic;
218 signal LDW : std_logic;
219 signal LDSPHL : std_logic;
220 signal IORQ_i : std_logic;
221 signal Special_LD : std_logic_vector(2 downto 0);
222 signal ExchangeDH : std_logic;
223 signal ExchangeRp : std_logic;
224 signal ExchangeAF : std_logic;
225 signal ExchangeRS : std_logic;
226 signal I_DJNZ : std_logic;
227 signal I_CPL : std_logic;
228 signal I_CCF : std_logic;
229 signal I_SCF : std_logic;
230 signal I_RETN : std_logic;
231 signal I_BT : std_logic;
232 signal I_BC : std_logic;
233 signal I_BTR : std_logic;
234 signal I_RLD : std_logic;
235 signal I_RRD : std_logic;
236 signal I_INRC : std_logic;
237 signal SetDI : std_logic;
238 signal SetEI : std_logic;
239 signal IMode : std_logic_vector(1 downto 0);
240 signal Halt : std_logic;
260 NMICycle => NMICycle,
261 IntCycle => IntCycle,
262 MCycles => MCycles_d,
267 IncDec_16 => IncDec_16,
268 Read_To_Acc => Read_To_Acc,
269 Read_To_Reg => Read_To_Reg,
270 Set_BusB_To => Set_BusB_To,
271 Set_BusA_To => Set_BusA_To,
273 Save_ALU => Save_ALU,
274 PreserveC => PreserveC,
276 Set_Addr_To => Set_Addr_To,
286 Special_LD => Special_LD,
287 ExchangeDH => ExchangeDH,
288 ExchangeRp => ExchangeRp,
289 ExchangeAF => ExchangeAF,
290 ExchangeRS => ExchangeRS,
321 Arith16 => Arith16_r,
324 IR => IR(5 downto 0),
332 ClkEn <= CEN and not BusAck;
334 T_Res <= '1' when TState = unsigned(TStates) else '0';
336 NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
337 ((Set_Addr_To = aXY) or
338 (MCycle = "001" and IR = "11001011") or
339 (MCycle = "001" and IR = "00110110")) else '0';
341 Save_Mux <= BusB when ExchangeRp = '1' else
342 DI_Reg when Save_ALU_r = '0' else
345 process (RESET_n, CLK_n)
347 if RESET_n = '0' then
348 PC <= (others => '0'); -- Program Counter
349 A <= (others => '0');
350 TmpAddr <= (others => '0');
358 ACC <= (others => '1');
359 F <= (others => '1');
360 Ap <= (others => '1');
361 Fp <= (others => '1');
362 I <= (others => '0');
363 R <= (others => '0');
364 SP <= (others => '1');
367 Read_To_Reg_r <= "00000";
368 F <= (others => '1');
377 elsif CLK_n'event and CLK_n = '1' then
383 Read_To_Reg_r <= "00000";
385 MCycles <= MCycles_d;
387 if IMode /= "11" then
391 Arith16_r <= Arith16;
392 PreserveC_r <= PreserveC;
393 if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
399 if MCycle = "001" and TState(2) = '0' then
400 -- MCycle = 1 and TState = 1, 2, or 3
402 if TState = 2 and Wait_n = '1' then
404 A(7 downto 0) <= std_logic_vector(R);
406 R(6 downto 0) <= R(6 downto 0) + 1;
409 if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
413 if IntCycle = '1' and IStatus = "01" then
415 elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
422 if Prefix /= "00" then
423 if Prefix = "11" then
430 if Prefix = "10" then
443 -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
445 if MCycle = "110" then
447 if Prefix = "01" then
453 BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
455 A(15 downto 8) <= DI_Reg;
456 A(7 downto 0) <= TmpAddr(7 downto 0);
457 PC(15 downto 8) <= unsigned(DI_Reg);
458 PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
459 elsif JumpXY = '1' then
461 PC <= unsigned(RegBusC);
462 elsif Call = '1' or RstP = '1' then
464 PC <= unsigned(TmpAddr);
465 elsif MCycle = MCycles and NMICycle = '1' then
466 A <= "0000000001100110";
467 PC <= "0000000001100110";
468 elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
470 A(7 downto 0) <= TmpAddr(7 downto 0);
471 PC(15 downto 8) <= unsigned(I);
472 PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
476 if XY_State = "00" then
479 if NextIs_XY_Fetch = '1' then
480 A <= std_logic_vector(PC);
487 -- Memory map I/O on GBZ80
488 A(15 downto 8) <= (others => '1');
490 -- Duplicate I/O address on 8080
491 A(15 downto 8) <= DI_Reg;
493 A(15 downto 8) <= ACC;
495 A(7 downto 0) <= DI_Reg;
497 A <= std_logic_vector(SP);
499 if Mode = 3 and IORQ_i = '1' then
500 -- Memory map I/O on GBZ80
501 A(15 downto 8) <= (others => '1');
502 A(7 downto 0) <= RegBusC(7 downto 0);
510 A <= std_logic_vector(unsigned(TmpAddr) + 1);
512 A(15 downto 8) <= DI_Reg;
513 A(7 downto 0) <= TmpAddr(7 downto 0);
516 A <= std_logic_vector(PC);
520 Save_ALU_r <= Save_ALU;
526 F(Flag_Y) <= not ACC(5);
528 F(Flag_X) <= not ACC(3);
533 F(Flag_C) <= not F(Flag_C);
535 F(Flag_H) <= F(Flag_C);
549 if TState = 2 and Wait_n = '1' then
550 if ISet = "01" and MCycle = "111" then
554 PC <= unsigned(signed(PC) + signed(DI_Reg));
555 elsif Inc_PC = '1' then
562 TmpAddr <= (others =>'0');
563 TmpAddr(5 downto 3) <= IR(5 downto 3);
566 if TState = 3 and MCycle = "110" then
567 TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
570 if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
571 if IncDec_16(2 downto 0) = "111" then
572 if IncDec_16(3) = '1' then
581 SP <= unsigned(RegBusC);
583 if ExchangeAF = '1' then
589 if ExchangeRS = '1' then
590 Alternate <= not Alternate;
596 TmpAddr(7 downto 0) <= DI_Reg;
599 TmpAddr(15 downto 8) <= DI_Reg;
602 if Special_LD(2) = '1' then
603 case Special_LD(1 downto 0) is
606 F(Flag_P) <= IntE_FF2;
608 ACC <= std_logic_vector(R);
609 F(Flag_P) <= IntE_FF2;
618 if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
623 if PreserveC_r = '0' then
627 F(7 downto 1) <= F_Out(7 downto 1);
628 if PreserveC_r = '0' then
629 F(Flag_C) <= F_Out(0);
633 if T_Res = '1' and I_INRC = '1' then
636 if DI_Reg(7 downto 0) = "00000000" then
641 F(Flag_S) <= DI_Reg(7);
642 F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
643 DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
646 if TState = 1 and Auto_Wait_t1 = '0' then
649 DO(3 downto 0) <= BusA(3 downto 0);
650 DO(7 downto 4) <= BusB(3 downto 0);
653 DO(3 downto 0) <= BusB(7 downto 4);
654 DO(7 downto 4) <= BusA(3 downto 0);
659 Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
660 Read_To_Reg_r(4) <= Read_To_Reg;
661 if Read_To_Acc = '1' then
662 Read_To_Reg_r(3 downto 0) <= "0111";
663 Read_To_Reg_r(4) <= '1';
667 if TState = 1 and I_BT = '1' then
668 F(Flag_X) <= ALU_Q(3);
669 F(Flag_Y) <= ALU_Q(1);
673 if I_BC = '1' or I_BT = '1' then
674 F(Flag_P) <= IncDecZ;
677 if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
678 (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
679 case Read_To_Reg_r is
685 SP(7 downto 0) <= unsigned(Save_Mux);
687 SP(15 downto 8) <= unsigned(Save_Mux);
700 ---------------------------------------------------------------------------
702 -- BC('), DE('), HL('), IX and IY
704 ---------------------------------------------------------------------------
707 if CLK_n'event and CLK_n = '1' then
710 RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
711 if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
712 RegAddrA_r <= XY_State(1) & "11";
716 RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
717 if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
718 RegAddrB_r <= XY_State(1) & "11";
721 -- Address from register
722 RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
723 -- Jump (HL), LD SP,HL
724 if (JumpXY = '1' or LDSPHL = '1') then
725 RegAddrC <= Alternate & "10";
727 if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
728 RegAddrC <= XY_State(1) & "11";
731 if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
732 IncDecZ <= F_Out(Flag_Z);
734 if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
742 RegBusA_r <= RegBusA;
748 -- 16 bit increment/decrement
749 Alternate & IncDec_16(1 downto 0) when (TState = 2 or
750 (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
751 XY_State(1) & "11" when (TState = 2 or
752 (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
754 Alternate & "10" when ExchangeDH = '1' and TState = 3 else
755 Alternate & "01" when ExchangeDH = '1' and TState = 4 else
761 Alternate & "01" when ExchangeDH = '1' and TState = 3 else
765 ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
768 process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
769 ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
773 if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
774 (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
775 case Read_To_Reg_r is
776 when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
777 RegWEH <= not Read_To_Reg_r(0);
778 RegWEL <= Read_To_Reg_r(0);
783 if ExchangeDH = '1' and (TState = 3 or TState = 4) then
788 if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
789 case IncDec_16(1 downto 0) is
790 when "00" | "01" | "10" =>
798 process (Save_Mux, RegBusB, RegBusA_r, ID16,
799 ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
804 if ExchangeDH = '1' and TState = 3 then
805 RegDIH <= RegBusB(15 downto 8);
806 RegDIL <= RegBusB(7 downto 0);
808 if ExchangeDH = '1' and TState = 4 then
809 RegDIH <= RegBusA_r(15 downto 8);
810 RegDIL <= RegBusA_r(7 downto 0);
813 if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
814 RegDIH <= std_logic_vector(ID16(15 downto 8));
815 RegDIL <= std_logic_vector(ID16(7 downto 0));
830 DOAH => RegBusA(15 downto 8),
831 DOAL => RegBusA(7 downto 0),
832 DOBH => RegBusB(15 downto 8),
833 DOBL => RegBusB(7 downto 0),
834 DOCH => RegBusC(15 downto 8),
835 DOCL => RegBusC(7 downto 0));
837 ---------------------------------------------------------------------------
841 ---------------------------------------------------------------------------
844 if CLK_n'event and CLK_n = '1' then
849 when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
850 if Set_BusB_To(0) = '1' then
851 BusB <= RegBusB(7 downto 0);
853 BusB <= RegBusB(15 downto 8);
858 BusB <= std_logic_vector(SP(7 downto 0));
860 BusB <= std_logic_vector(SP(15 downto 8));
866 BusB <= std_logic_vector(PC(7 downto 0));
868 BusB <= std_logic_vector(PC(15 downto 8));
878 when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
879 if Set_BusA_To(0) = '1' then
880 BusA <= RegBusA(7 downto 0);
882 BusA <= RegBusA(15 downto 8);
887 BusA <= std_logic_vector(SP(7 downto 0));
889 BusA <= std_logic_vector(SP(15 downto 8));
899 ---------------------------------------------------------------------------
901 -- Generate external control signals
903 ---------------------------------------------------------------------------
904 process (RESET_n,CLK_n)
906 if RESET_n = '0' then
908 elsif CLK_n'event and CLK_n = '1' then
910 if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
919 MC <= std_logic_vector(MCycle);
920 TS <= std_logic_vector(TState);
922 HALT_n <= not Halt_FF;
923 BUSAK_n <= not BusAck;
924 IntCycle_n <= not IntCycle;
929 -------------------------------------------------------------------------
933 -------------------------------------------------------------------------
934 process (RESET_n, CLK_n)
935 variable OldNMI_n : std_logic;
937 if RESET_n = '0' then
942 elsif CLK_n'event and CLK_n = '1' then
944 BusReq_s <= not BUSRQ_n;
946 if NMICycle = '1' then
948 elsif NMI_n = '0' and OldNMI_n = '1' then
956 -------------------------------------------------------------------------
958 -- Main state machine
960 -------------------------------------------------------------------------
961 process (RESET_n, CLK_n)
963 if RESET_n = '0' then
977 elsif CLK_n'event and CLK_n = '1' then
982 Auto_Wait_t1 <= Auto_Wait or IORQ_i;
984 Auto_Wait_t2 <= Auto_Wait_t1;
985 No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
986 (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
987 (I_BTR and (not IR(4) or F(Flag_Z)));
994 IntE_FF1 <= IntE_FF2;
1003 if IntCycle = '1' or NMICycle = '1' then
1006 if MCycle = "001" and TState = 2 and Wait_n = '1' then
1009 if BusReq_s = '1' and BusAck = '1' then
1012 if TState = 2 and Wait_n = '0' then
1013 elsif T_Res = '1' then
1017 if BusReq_s = '1' then
1021 if NextIs_XY_Fetch = '1' then
1023 Pre_XY_F_M <= MCycle;
1024 if IR = "00110110" and Mode = 0 then
1025 Pre_XY_F_M <= "010";
1027 elsif (MCycle = "111") or
1028 (MCycle = "110" and Mode = 1 and ISet /= "01") then
1029 MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
1030 elsif (MCycle = MCycles) or
1032 (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
1037 if NMI_s = '1' and Prefix = "00" then
1040 elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
1046 MCycle <= std_logic_vector(unsigned(MCycle) + 1);
1050 if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
1051 (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
1052 TState <= TState + 1;
1063 process (IntCycle, NMICycle, MCycle)
1066 if IntCycle = '1' or NMICycle = '1' then
1067 if MCycle = "001" then