git.zerfleddert.de Git - fpga-games/blob - galaxian/t80_ip/T80_Reg.vhd

   1 -- ****
   2 -- T80(b) core. In an effort to merge and maintain bug fixes ....
   3 --
   4 --
   5 -- Ver 300 started tidyup
   6 -- MikeJ March 2005
   7 -- Latest version from www.fpgaarcade.com (original www.opencores.org)
   8 --
   9 -- ****
  10 --
  11 -- T80 Registers, technology independent
  12 --
  13 -- Version : 0244
  14 --
  15 -- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
  16 --
  17 -- All rights reserved
  18 --
  19 -- Redistribution and use in source and synthezised forms, with or without
  20 -- modification, are permitted provided that the following conditions are met:
  21 --
  22 -- Redistributions of source code must retain the above copyright notice,
  23 -- this list of conditions and the following disclaimer.
  24 --
  25 -- Redistributions in synthesized form must reproduce the above copyright
  26 -- notice, this list of conditions and the following disclaimer in the
  27 -- documentation and/or other materials provided with the distribution.
  28 --
  29 -- Neither the name of the author nor the names of other contributors may
  30 -- be used to endorse or promote products derived from this software without
  31 -- specific prior written permission.
  32 --
  33 -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  34 -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  35 -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  36 -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
  37 -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  38 -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  39 -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  40 -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  41 -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  42 -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  43 -- POSSIBILITY OF SUCH DAMAGE.
  44 --
  45 -- Please report bugs to the author, but before you do so, please
  46 -- make sure that this is not a derivative work and that
  47 -- you have the latest version of this file.
  48 --
  49 -- The latest version of this file can be found at:
  50 --      http://www.opencores.org/cvsweb.shtml/t51/
  51 --
  52 -- Limitations :
  53 --
  54 -- File history :
  55 --
  56 --      0242 : Initial release
  57 --
  58 --      0244 : Changed to single register file
  59 --
  60
  61 library IEEE;
  62 use IEEE.std_logic_1164.all;
  63 use IEEE.numeric_std.all;
  64
  65 entity T80_Reg is
  66         port(
  67                 Clk                     : in std_logic;
  68                 CEN                     : in std_logic;
  69                 WEH                     : in std_logic;
  70                 WEL                     : in std_logic;
  71                 AddrA           : in std_logic_vector(2 downto 0);
  72                 AddrB           : in std_logic_vector(2 downto 0);
  73                 AddrC           : in std_logic_vector(2 downto 0);
  74                 DIH                     : in std_logic_vector(7 downto 0);
  75                 DIL                     : in std_logic_vector(7 downto 0);
  76                 DOAH            : out std_logic_vector(7 downto 0);
  77                 DOAL            : out std_logic_vector(7 downto 0);
  78                 DOBH            : out std_logic_vector(7 downto 0);
  79                 DOBL            : out std_logic_vector(7 downto 0);
  80                 DOCH            : out std_logic_vector(7 downto 0);
  81                 DOCL            : out std_logic_vector(7 downto 0)
  82         );
  83 end T80_Reg;
  84
  85 architecture rtl of T80_Reg is
  86
  87         type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
  88         signal      RegsH   : Register_Image(0 to 7);
  89         signal      RegsL   : Register_Image(0 to 7);
  90
  91 begin
  92
  93         process (Clk)
  94         begin
  95                 if Clk'event and Clk = '1' then
  96                         if CEN = '1' then
  97                                 if WEH = '1' then
  98                                         RegsH(to_integer(unsigned(AddrA))) <= DIH;
  99                                 end if;
 100                                 if WEL = '1' then
 101                                         RegsL(to_integer(unsigned(AddrA))) <= DIL;
 102                                 end if;
 103                         end if;
 104                 end if;
 105         end process;
 106
 107         DOAH <= RegsH(to_integer(unsigned(AddrA)));
 108         DOAL <= RegsL(to_integer(unsigned(AddrA)));
 109         DOBH <= RegsH(to_integer(unsigned(AddrB)));
 110         DOBL <= RegsL(to_integer(unsigned(AddrB)));
 111         DOCH <= RegsH(to_integer(unsigned(AddrC)));
 112         DOCL <= RegsL(to_integer(unsigned(AddrC)));
 113
 114 end;