1 From f8a6bbe8437ae48f5638a58472e5bb8c3f9101cf Mon Sep 17 00:00:00 2001
2 From: Saeed Bishara <saeed@marvell.com>
3 Date: Sun, 14 Feb 2010 18:28:46 +0200
4 Subject: [PATCH] arm: invalidate TLBs when enabling mmu
7 Signed-off-by: Saeed Bishara <saeed@marvell.com>
9 arch/arm/boot/compressed/head.S | 1 +
10 1 files changed, 1 insertions(+), 0 deletions(-)
12 diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
13 index 40ef902..f421d06 100644
14 --- a/arch/arm/boot/compressed/head.S
15 +++ b/arch/arm/boot/compressed/head.S
16 @@ -481,6 +481,7 @@ __armv7_mmu_cache_on:
17 mcr p15, 0, r0, c1, c0, 0 @ load control register
18 mrc p15, 0, r0, c1, c0, 0 @ and read it back
20 + mcr p15, 0, r0, c8, c7, 0 @ invalidate I,D TLBs
21 mcr p15, 0, r0, c7, c5, 4 @ ISB