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CHG: "hf legic read" - increased timeout values client side, reading MIM1024 takes...
[proxmark3-svn] / armsrc / legicrf.c
1 //-----------------------------------------------------------------------------
2 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // LEGIC RF simulation code
9 //-----------------------------------------------------------------------------
10 #include "legicrf.h"
11
12 static struct legic_frame {
13 uint8_t bits;
14 uint32_t data;
15 } current_frame;
16
17 static enum {
18 STATE_DISCON,
19 STATE_IV,
20 STATE_CON,
21 } legic_state;
22
23 static crc_t legic_crc;
24 static int legic_read_count;
25 static uint32_t legic_prng_bc;
26 static uint32_t legic_prng_iv;
27
28 static int legic_phase_drift;
29 static int legic_frame_drift;
30 static int legic_reqresp_drift;
31
32 AT91PS_TC timer;
33 AT91PS_TC prng_timer;
34
35 /*
36 static void setup_timer(void) {
37 // Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
38 // this it won't be terribly accurate but should be good enough.
39 //
40 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
41 timer = AT91C_BASE_TC1;
42 timer->TC_CCR = AT91C_TC_CLKDIS;
43 timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
44 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
45
46 //
47 // Set up Timer 2 to use for measuring time between frames in
48 // tag simulation mode. Runs 4x faster as Timer 1
49 //
50 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);
51 prng_timer = AT91C_BASE_TC2;
52 prng_timer->TC_CCR = AT91C_TC_CLKDIS;
53 prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
54 prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
55 }
56
57 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
58 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
59
60 // fast clock
61 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
62 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
63 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
64 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
65 AT91C_BASE_TC0->TC_RA = 1;
66 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
67
68 */
69
70 // At TIMER_CLOCK3 (MCK/32)
71 // testing calculating in (us) microseconds.
72 #define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks
73 #define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks
74 #define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */
75 #define TAG_BIT_PERIOD 142 // 100us == 100 * 1.5 == 150ticks
76 #define TAG_FRAME_WAIT 495 // 330us from READER frame end to TAG frame start. 330 * 1.5 == 495
77
78 #define RWD_TIME_FUZZ 20 // rather generous 13us, since the peak detector + hysteresis fuzz quite a bit
79
80 #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
81 #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
82
83 #define OFFSET_LOG 1024
84
85 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
86
87 #ifndef SHORT_COIL
88 # define SHORT_COIL LOW(GPIO_SSC_DOUT);
89 #endif
90 #ifndef OPEN_COIL
91 # define OPEN_COIL HIGH(GPIO_SSC_DOUT);
92 #endif
93
94 // Pause pulse, off in 20us / 30ticks,
95 // ONE / ZERO bit pulse,
96 // one == 80us / 120ticks
97 // zero == 40us / 60ticks
98 #ifndef COIL_PULSE
99 # define COIL_PULSE(x) \
100 do { \
101 SHORT_COIL; \
102 WaitTicks( (RWD_TIME_PAUSE) ); \
103 OPEN_COIL; \
104 WaitTicks((x)); \
105 } while (0)
106 #endif
107
108 // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
109 // Historically it used to be FREE_BUFFER_SIZE, which was 2744.
110 #define LEGIC_CARD_MEMSIZE 1024
111 static uint8_t* cardmem;
112
113 static void frame_append_bit(struct legic_frame * const f, uint8_t bit) {
114 // Overflow, won't happen
115 if (f->bits >= 31) return;
116
117 f->data |= (bit << f->bits);
118 f->bits++;
119 }
120
121 static void frame_clean(struct legic_frame * const f) {
122 f->data = 0;
123 f->bits = 0;
124 }
125
126 // Prng works when waiting in 99.1us cycles.
127 // and while sending/receiving in bit frames (100, 60)
128 /*static void CalibratePrng( uint32_t time){
129 // Calculate Cycles based on timer 100us
130 uint32_t i = (time - sendFrameStop) / 100 ;
131
132 // substract cycles of finished frames
133 int k = i - legic_prng_count()+1;
134
135 // substract current frame length, rewind to beginning
136 if ( k > 0 )
137 legic_prng_forward(k);
138 }
139 */
140
141 /* Generate Keystream */
142 uint32_t get_key_stream(int skip, int count) {
143 uint32_t key = 0;
144 int i;
145
146 // Use int to enlarge timer tc to 32bit
147 legic_prng_bc += prng_timer->TC_CV;
148
149 // reset the prng timer.
150 ResetTimer(prng_timer);
151
152 /* If skip == -1, forward prng time based */
153 if(skip == -1) {
154 i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */
155 i -= legic_prng_count(); /* substract cycles of finished frames */
156 i -= count; /* substract current frame length, rewind to beginning */
157 legic_prng_forward(i);
158 } else {
159 legic_prng_forward(skip);
160 }
161
162 i = (count == 6) ? -1 : legic_read_count;
163
164 /* Write Time Data into LOG */
165 // uint8_t *BigBuf = BigBuf_get_addr();
166 // BigBuf[OFFSET_LOG+128+i] = legic_prng_count();
167 // BigBuf[OFFSET_LOG+256+i*4] = (legic_prng_bc >> 0) & 0xff;
168 // BigBuf[OFFSET_LOG+256+i*4+1] = (legic_prng_bc >> 8) & 0xff;
169 // BigBuf[OFFSET_LOG+256+i*4+2] = (legic_prng_bc >>16) & 0xff;
170 // BigBuf[OFFSET_LOG+256+i*4+3] = (legic_prng_bc >>24) & 0xff;
171 // BigBuf[OFFSET_LOG+384+i] = count;
172
173 /* Generate KeyStream */
174 for(i=0; i<count; i++) {
175 key |= legic_prng_get_bit() << i;
176 legic_prng_forward(1);
177 }
178 return key;
179 }
180
181 /* Send a frame in tag mode, the FPGA must have been set up by
182 * LegicRfSimulate
183 */
184 void frame_send_tag(uint16_t response, uint8_t bits, uint8_t crypt) {
185 /* Bitbang the response */
186 LOW(GPIO_SSC_DOUT);
187 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
188 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
189
190 /* Use time to crypt frame */
191 if(crypt) {
192 legic_prng_forward(2); /* TAG_FRAME_WAIT -> shift by 2 */
193 response ^= legic_prng_get_bits(bits);
194 }
195
196 /* Wait for the frame start */
197 WaitUS( TAG_FRAME_WAIT );
198
199 uint8_t bit = 0;
200 for(int i = 0; i < bits; i++) {
201
202 bit = response & 1;
203 response >>= 1;
204
205 if (bit)
206 HIGH(GPIO_SSC_DOUT);
207 else
208 LOW(GPIO_SSC_DOUT);
209
210 WaitUS(100);
211 }
212 LOW(GPIO_SSC_DOUT);
213 }
214
215 /* Send a frame in reader mode, the FPGA must have been set up by
216 * LegicRfReader
217 */
218 void frame_sendAsReader(uint32_t data, uint8_t bits){
219
220 uint32_t starttime = GET_TICKS, send = 0;
221 uint16_t mask = 1;
222
223 // xor lsfr onto data.
224 send = data ^ legic_prng_get_bits(bits);
225
226 for (; mask < BITMASK(bits); mask <<= 1) {
227 if (send & mask)
228 COIL_PULSE(RWD_TIME_1);
229 else
230 COIL_PULSE(RWD_TIME_0);
231 }
232
233 // Final pause to mark the end of the frame
234 COIL_PULSE(0);
235
236 // log
237 uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1), BYTEx(send, 0), BYTEx(send, 1)};
238 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, TRUE);
239 }
240
241 /* Receive a frame from the card in reader emulation mode, the FPGA and
242 * timer must have been set up by LegicRfReader and frame_sendAsReader.
243 *
244 * The LEGIC RF protocol from card to reader does not include explicit
245 * frame start/stop information or length information. The reader must
246 * know beforehand how many bits it wants to receive. (Notably: a card
247 * sending a stream of 0-bits is indistinguishable from no card present.)
248 *
249 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
250 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
251 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
252 * for edges. Count the edges in each bit interval. If they are approximately
253 * 0 this was a 0-bit, if they are approximately equal to the number of edges
254 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
255 * timer that's still running from frame_sendAsReader in order to get a synchronization
256 * with the frame that we just sent.
257 *
258 * FIXME: Because we're relying on the hysteresis to just do the right thing
259 * the range is severely reduced (and you'll probably also need a good antenna).
260 * So this should be fixed some time in the future for a proper receiver.
261 */
262 static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) {
263
264 if ( bits > 32 ) return;
265
266 uint8_t i = bits, edges = 0;
267 uint32_t the_bit = 1, next_bit_at = 0, data = 0;
268 uint32_t old_level = 0;
269 volatile uint32_t level = 0;
270
271 frame_clean(f);
272
273 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
274 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
275
276 // calibrate the prng.
277 legic_prng_forward(2);
278 data = legic_prng_get_bits(bits);
279
280 //FIXED time between sending frame and now listening frame. 330us
281 uint32_t starttime = GET_TICKS;
282 // its about 9+9 ticks delay from end-send to here.
283 WaitTicks( 477 );
284
285 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
286
287 while ( i-- ){
288 edges = 0;
289 while ( GET_TICKS < next_bit_at) {
290
291 level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
292
293 if (level != old_level)
294 ++edges;
295
296 old_level = level;
297 }
298
299 next_bit_at += TAG_BIT_PERIOD;
300
301 // We expect 42 edges (ONE)
302 if ( edges > 20 )
303 data ^= the_bit;
304
305 the_bit <<= 1;
306 }
307
308 // output
309 f->data = data;
310 f->bits = bits;
311
312 // log
313 uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
314 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
315 }
316
317 // Setup pm3 as a Legic Reader
318 static uint32_t setup_phase_reader(uint8_t iv) {
319
320 // Switch on carrier and let the tag charge for 1ms
321 HIGH(GPIO_SSC_DOUT);
322 WaitUS(5000);
323
324 ResetTicks();
325
326 // no keystream yet
327 legic_prng_init(0);
328
329 // send IV handshake
330 frame_sendAsReader(iv, 7);
331
332 // Now both tag and reader has same IV. Prng can start.
333 legic_prng_init(iv);
334
335 frame_receiveAsReader(&current_frame, 6);
336
337 // 292us (438t) - fixed delay before sending ack.
338 // minus log and stuff 100tick?
339 WaitTicks(338);
340 legic_prng_forward(3);
341
342 // Send obsfuscated acknowledgment frame.
343 // 0x19 = 0x18 MIM22, 0x01 LSB READCMD
344 // 0x39 = 0x38 MIM256, MIM1024 0x01 LSB READCMD
345 switch ( current_frame.data ) {
346 case 0x0D: frame_sendAsReader(0x19, 6); break;
347 case 0x1D:
348 case 0x3D: frame_sendAsReader(0x39, 6); break;
349 default: break;
350 }
351
352 legic_prng_forward(2);
353 return current_frame.data;
354 }
355
356 static void LegicCommonInit(void) {
357
358 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
359 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
360 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
361
362 /* Bitbang the transmitter */
363 LOW(GPIO_SSC_DOUT);
364 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
365 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
366
367 // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
368 cardmem = BigBuf_get_EM_addr();
369 memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE);
370
371 clear_trace();
372 set_tracing(TRUE);
373 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
374
375 StartTicks();
376 }
377
378 // Switch off carrier, make sure tag is reset
379 static void switch_off_tag_rwd(void) {
380 LOW(GPIO_SSC_DOUT);
381 WaitUS(20);
382 WDT_HIT();
383 }
384
385 // calculate crc4 for a legic READ command
386 static uint32_t legic4Crc(uint8_t cmd, uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
387 crc_clear(&legic_crc);
388 uint32_t temp = (value << cmd_sz) | (byte_index << 1) | cmd;
389 crc_update(&legic_crc, temp, cmd_sz + 8 );
390 return crc_finish(&legic_crc);
391 }
392
393 int legic_read_byte( uint16_t index, uint8_t cmd_sz) {
394
395 uint8_t byte, crc, calcCrc = 0;
396 uint32_t cmd = (index << 1) | LEGIC_READ;
397
398 //WaitTicks(366);
399 WaitTicks(330);
400
401 frame_sendAsReader(cmd, cmd_sz);
402 frame_receiveAsReader(&current_frame, 12);
403
404 // CRC check.
405 byte = BYTEx(current_frame.data, 0);
406 crc = BYTEx(current_frame.data, 1);
407 calcCrc = legic4Crc(LEGIC_READ, index, byte, cmd_sz);
408
409 if( calcCrc != crc ) {
410 Dbprintf("!!! crc mismatch: expected %x but got %x !!!", calcCrc, crc);
411 return -1;
412 }
413
414 legic_prng_forward(4);
415 return byte;
416 }
417
418 /*
419 * - assemble a write_cmd_frame with crc and send it
420 * - wait until the tag sends back an ACK ('1' bit unencrypted)
421 * - forward the prng based on the timing
422 */
423 //int legic_write_byte(int byte, int addr, int addr_sz, int PrngCorrection) {
424 int legic_write_byte(uint8_t byte, uint16_t addr, uint8_t addr_sz) {
425
426 //do not write UID, CRC at offset 0-4.
427 if (addr <= 4) return 0;
428
429 // crc
430 crc_clear(&legic_crc);
431 crc_update(&legic_crc, 0, 1); /* CMD_WRITE */
432 crc_update(&legic_crc, addr, addr_sz);
433 crc_update(&legic_crc, byte, 8);
434 uint32_t crc = crc_finish(&legic_crc);
435 uint32_t crc2 = legic4Crc(LEGIC_WRITE, addr, byte, addr_sz+1);
436 if ( crc != crc2 ) {
437 Dbprintf("crc is missmatch");
438 return 1;
439 }
440 // send write command
441 uint32_t cmd = ((crc <<(addr_sz+1+8)) //CRC
442 |(byte <<(addr_sz+1)) //Data
443 |(addr <<1) //Address
444 | LEGIC_WRITE); //CMD = Write
445
446 uint32_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd
447
448 legic_prng_forward(2); /* we wait anyways */
449
450 WaitTicks(330);
451
452 frame_sendAsReader(cmd, cmd_sz);
453
454 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
455 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
456
457 // wait for ack
458 int t, old_level = 0, edges = 0;
459 int next_bit_at = 0;
460
461 WaitUS(TAG_FRAME_WAIT);
462
463 for( t = 0; t < 80; ++t) {
464 edges = 0;
465 next_bit_at += TAG_BIT_PERIOD;
466 while(timer->TC_CV < next_bit_at) {
467 volatile uint32_t level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
468 if(level != old_level)
469 edges++;
470
471 old_level = level;
472 }
473 if(edges > 20 ) { /* expected are 42 edges */
474 int t = timer->TC_CV;
475 int c = t / TAG_BIT_PERIOD;
476
477 ResetTimer(timer);
478 legic_prng_forward(c);
479 return 0;
480 }
481 }
482
483 ResetTimer(timer);
484 return -1;
485 }
486
487 int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) {
488
489 uint16_t i = 0;
490 uint8_t isOK = 1;
491 legic_card_select_t card;
492
493 LegicCommonInit();
494
495 if ( legic_select_card_iv(&card, iv) ) {
496 isOK = 0;
497 goto OUT;
498 }
499
500 switch_off_tag_rwd();
501
502 if (len + offset >= card.cardsize)
503 len = card.cardsize - offset;
504
505 setup_phase_reader(iv);
506
507 LED_B_ON();
508 while (i <= len) {
509 int r = legic_read_byte(offset + i, card.cmdsize);
510
511 if (r == -1 || BUTTON_PRESS()) {
512 if ( MF_DBGLEVEL >= 2) DbpString("operation aborted");
513 isOK = 0;
514 goto OUT;
515 }
516 cardmem[i++] = r;
517 WDT_HIT();
518 }
519
520 OUT:
521 WDT_HIT();
522 switch_off_tag_rwd();
523 LEDsoff();
524 cmd_send(CMD_ACK, isOK, len, 0, cardmem, len);
525 return 0;
526 }
527
528 /*int _LegicRfWriter(int offset, int bytes, int addr_sz, uint8_t *BigBuf, int RoundBruteforceValue) {
529 int byte_index=0;
530
531 LED_B_ON();
532 setup_phase_reader(iv);
533 //legic_prng_forward(2);
534 while(byte_index < bytes) {
535 int r;
536
537 //check if the DCF should be changed
538 if ( (offset == 0x05) && (bytes == 0x02) ) {
539 //write DCF in reverse order (addr 0x06 before 0x05)
540 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
541 //legic_prng_forward(1);
542 if(r == 0) {
543 byte_index++;
544 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
545 }
546 //legic_prng_forward(1);
547 }
548 else {
549 r = legic_write_byte(BigBuf[byte_index+offset], byte_index+offset, addr_sz, RoundBruteforceValue);
550 }
551 if((r != 0) || BUTTON_PRESS()) {
552 Dbprintf("operation aborted @ 0x%03.3x", byte_index);
553 switch_off_tag_rwd();
554 LED_B_OFF();
555 LED_C_OFF();
556 return -1;
557 }
558
559 WDT_HIT();
560 byte_index++;
561 if(byte_index & 0x10) LED_C_ON(); else LED_C_OFF();
562 }
563 LED_B_OFF();
564 LED_C_OFF();
565 DbpString("write successful");
566 return 0;
567 }*/
568
569 void LegicRfWriter(uint16_t offset, uint16_t bytes, uint8_t iv) {
570
571 int byte_index = 0;
572 uint8_t isOK = 1;
573 legic_card_select_t card;
574
575 LegicCommonInit();
576
577 if ( legic_select_card_iv(&card, iv) ) {
578 isOK = 0;
579 goto OUT;
580 }
581
582 switch_off_tag_rwd();
583
584 switch(card.tagtype) {
585 case 0x0d:
586 if(offset+bytes > 22) {
587 Dbprintf("Error: can not write to 0x%03.3x on MIM22", offset + bytes);
588 return;
589 }
590 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM22 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset + bytes);
591 break;
592 case 0x1d:
593 if(offset+bytes > 0x100) {
594 Dbprintf("Error: can not write to 0x%03.3x on MIM256", offset + bytes);
595 return;
596 }
597 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM256 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset + bytes);
598 break;
599 case 0x3d:
600 if(offset+bytes > 0x400) {
601 Dbprintf("Error: can not write to 0x%03.3x on MIM1024", offset + bytes);
602 return;
603 }
604 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM1024 card found, writing 0x%03.3x - 0x%03.3x ...", offset, offset + bytes);
605 break;
606 default:
607 return;
608 }
609
610 LED_B_ON();
611 setup_phase_reader(iv);
612
613 int r = 0;
614 while(byte_index < bytes) {
615
616 //check if the DCF should be changed
617 if ( ((byte_index+offset) == 0x05) && (bytes >= 0x02) ) {
618 //write DCF in reverse order (addr 0x06 before 0x05)
619 r = legic_write_byte(cardmem[(0x06-byte_index)], (0x06-byte_index), card.addrsize);
620
621 // write second byte on success
622 if(r == 0) {
623 byte_index++;
624 r = legic_write_byte(cardmem[(0x06-byte_index)], (0x06-byte_index), card.addrsize);
625 }
626 }
627 else {
628 r = legic_write_byte(cardmem[byte_index+offset], byte_index+offset, card.addrsize);
629 }
630
631 if ((r != 0) || BUTTON_PRESS()) {
632 Dbprintf("operation aborted @ 0x%03.3x", byte_index);
633 isOK = 0;
634 goto OUT;
635 }
636
637 WDT_HIT();
638 byte_index++;
639 }
640
641 OUT:
642 cmd_send(CMD_ACK, isOK, 0,0,0,0);
643 switch_off_tag_rwd();
644 LEDsoff();
645 }
646
647 void LegicRfRawWriter(int address, int byte, uint8_t iv) {
648
649 int byte_index = 0, addr_sz = 0;
650
651 LegicCommonInit();
652
653 if ( MF_DBGLEVEL >= 2) DbpString("setting up legic card");
654
655 uint32_t tag_type = setup_phase_reader(iv);
656
657 switch_off_tag_rwd();
658
659 switch(tag_type) {
660 case 0x0d:
661 if(address > 22) {
662 Dbprintf("Error: can not write to 0x%03.3x on MIM22", address);
663 return;
664 }
665 addr_sz = 5;
666 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM22 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address, byte);
667 break;
668 case 0x1d:
669 if(address > 0x100) {
670 Dbprintf("Error: can not write to 0x%03.3x on MIM256", address);
671 return;
672 }
673 addr_sz = 8;
674 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM256 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address, byte);
675 break;
676 case 0x3d:
677 if(address > 0x400) {
678 Dbprintf("Error: can not write to 0x%03.3x on MIM1024", address);
679 return;
680 }
681 addr_sz = 10;
682 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM1024 card found, writing at addr 0x%03.3x - value 0x%03.3x ...", address, byte);
683 break;
684 default:
685 Dbprintf("No or unknown card found, aborting");
686 return;
687 }
688
689 Dbprintf("integer value: %d address: %d addr_sz: %d", byte, address, addr_sz);
690 LED_B_ON();
691
692 setup_phase_reader(iv);
693
694 int r = legic_write_byte(byte, address, addr_sz);
695
696 if((r != 0) || BUTTON_PRESS()) {
697 Dbprintf("operation aborted @ 0x%03.3x (%1d)", byte_index, r);
698 switch_off_tag_rwd();
699 LEDsoff();
700 return;
701 }
702
703 LEDsoff();
704 if ( MF_DBGLEVEL >= 1) DbpString("write successful");
705 }
706
707 int legic_select_card_iv(legic_card_select_t *p_card, uint8_t iv){
708
709 if ( p_card == NULL ) return 1;
710
711 p_card->tagtype = setup_phase_reader(iv);
712
713 switch(p_card->tagtype) {
714 case 0x0d:
715 p_card->cmdsize = 6;
716 p_card->addrsize = 5;
717 p_card->cardsize = 22;
718 break;
719 case 0x1d:
720 p_card->cmdsize = 9;
721 p_card->addrsize = 8;
722 p_card->cardsize = 256;
723 break;
724 case 0x3d:
725 p_card->cmdsize = 11;
726 p_card->addrsize = 10;
727 p_card->cardsize = 1024;
728 break;
729 default:
730 p_card->cmdsize = 0;
731 p_card->addrsize = 0;
732 p_card->cardsize = 0;
733 return 2;
734 }
735 return 0;
736 }
737 int legic_select_card(legic_card_select_t *p_card){
738 return legic_select_card_iv(p_card, 0x01);
739 }
740
741 void LegicRfInfo(void){
742
743 uint8_t buf[sizeof(legic_card_select_t)] = {0x00};
744 legic_card_select_t *card = (legic_card_select_t*) buf;
745
746 LegicCommonInit();
747
748 if ( legic_select_card(card) ) {
749 cmd_send(CMD_ACK,0,0,0,0,0);
750 goto OUT;
751 }
752
753 // read UID bytes
754 for ( uint8_t i = 0; i < sizeof(card->uid); ++i) {
755 int r = legic_read_byte(i, card->cmdsize);
756 if ( r == -1 ) {
757 cmd_send(CMD_ACK,0,0,0,0,0);
758 goto OUT;
759 }
760 card->uid[i] = r & 0xFF;
761 }
762
763 cmd_send(CMD_ACK, 1, 0, 0, buf, sizeof(legic_card_select_t));
764
765 OUT:
766 switch_off_tag_rwd();
767 LEDsoff();
768 }
769
770 /* Handle (whether to respond) a frame in tag mode
771 * Only called when simulating a tag.
772 */
773 static void frame_handle_tag(struct legic_frame const * const f)
774 {
775 uint8_t *BigBuf = BigBuf_get_addr();
776
777 /* First Part of Handshake (IV) */
778 if(f->bits == 7) {
779
780 LED_C_ON();
781
782 // Reset prng timer
783 ResetTimer(prng_timer);
784
785 legic_prng_init(f->data);
786 frame_send_tag(0x3d, 6, 1); /* 0x3d^0x26 = 0x1B */
787 legic_state = STATE_IV;
788 legic_read_count = 0;
789 legic_prng_bc = 0;
790 legic_prng_iv = f->data;
791
792
793 ResetTimer(timer);
794 WaitUS(280);
795 return;
796 }
797
798 /* 0x19==??? */
799 if(legic_state == STATE_IV) {
800 int local_key = get_key_stream(3, 6);
801 int xored = 0x39 ^ local_key;
802 if((f->bits == 6) && (f->data == xored)) {
803 legic_state = STATE_CON;
804
805 ResetTimer(timer);
806 WaitUS(200);
807 return;
808
809 } else {
810 legic_state = STATE_DISCON;
811 LED_C_OFF();
812 Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored);
813 return;
814 }
815 }
816
817 /* Read */
818 if(f->bits == 11) {
819 if(legic_state == STATE_CON) {
820 int key = get_key_stream(2, 11); //legic_phase_drift, 11);
821 int addr = f->data ^ key; addr = addr >> 1;
822 int data = BigBuf[addr];
823 int hash = legic4Crc(LEGIC_READ, addr, data, 11) << 8;
824 BigBuf[OFFSET_LOG+legic_read_count] = (uint8_t)addr;
825 legic_read_count++;
826
827 //Dbprintf("Data:%03.3x, key:%03.3x, addr: %03.3x, read_c:%u", f->data, key, addr, read_c);
828 legic_prng_forward(legic_reqresp_drift);
829
830 frame_send_tag(hash | data, 12, 1);
831
832 ResetTimer(timer);
833 legic_prng_forward(2);
834 WaitUS(180);
835 return;
836 }
837 }
838
839 /* Write */
840 if(f->bits == 23) {
841 int key = get_key_stream(-1, 23); //legic_frame_drift, 23);
842 int addr = f->data ^ key; addr = addr >> 1; addr = addr & 0x3ff;
843 int data = f->data ^ key; data = data >> 11; data = data & 0xff;
844
845 /* write command */
846 legic_state = STATE_DISCON;
847 LED_C_OFF();
848 Dbprintf("write - addr: %x, data: %x", addr, data);
849 return;
850 }
851
852 if(legic_state != STATE_DISCON) {
853 Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count);
854 int i;
855 Dbprintf("IV: %03.3x", legic_prng_iv);
856 for(i = 0; i<legic_read_count; i++) {
857 Dbprintf("Read Nb: %u, Addr: %u", i, BigBuf[OFFSET_LOG+i]);
858 }
859
860 for(i = -1; i<legic_read_count; i++) {
861 uint32_t t;
862 t = BigBuf[OFFSET_LOG+256+i*4];
863 t |= BigBuf[OFFSET_LOG+256+i*4+1] << 8;
864 t |= BigBuf[OFFSET_LOG+256+i*4+2] <<16;
865 t |= BigBuf[OFFSET_LOG+256+i*4+3] <<24;
866
867 Dbprintf("Cycles: %u, Frame Length: %u, Time: %u",
868 BigBuf[OFFSET_LOG+128+i],
869 BigBuf[OFFSET_LOG+384+i],
870 t);
871 }
872 }
873 legic_state = STATE_DISCON;
874 legic_read_count = 0;
875 SpinDelay(10);
876 LED_C_OFF();
877 return;
878 }
879
880 /* Read bit by bit untill full frame is received
881 * Call to process frame end answer
882 */
883 static void emit(int bit) {
884
885 switch (bit) {
886 case 1:
887 frame_append_bit(&current_frame, 1);
888 break;
889 case 0:
890 frame_append_bit(&current_frame, 0);
891 break;
892 default:
893 if(current_frame.bits <= 4) {
894 frame_clean(&current_frame);
895 } else {
896 frame_handle_tag(&current_frame);
897 frame_clean(&current_frame);
898 }
899 WDT_HIT();
900 break;
901 }
902 }
903
904 void LegicRfSimulate(int phase, int frame, int reqresp)
905 {
906 /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
907 * modulation mode set to 212kHz subcarrier. We are getting the incoming raw
908 * envelope waveform on DIN and should send our response on DOUT.
909 *
910 * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
911 * measure the time between two rising edges on DIN, and no encoding on the
912 * subcarrier from card to reader, so we'll just shift out our verbatim data
913 * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
914 * seems to be 300us-ish.
915 */
916
917 legic_phase_drift = phase;
918 legic_frame_drift = frame;
919 legic_reqresp_drift = reqresp;
920
921 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
922 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
923 FpgaSetupSsc();
924 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
925
926 /* Bitbang the receiver */
927 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
928 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
929
930 //setup_timer();
931 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
932
933 int old_level = 0;
934 int active = 0;
935 legic_state = STATE_DISCON;
936
937 LED_B_ON();
938 DbpString("Starting Legic emulator, press button to end");
939
940 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
941 int level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
942 int time = timer->TC_CV;
943
944 if(level != old_level) {
945 if(level == 1) {
946 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
947
948 if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
949 /* 1 bit */
950 emit(1);
951 active = 1;
952 LED_A_ON();
953 } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
954 /* 0 bit */
955 emit(0);
956 active = 1;
957 LED_A_ON();
958 } else if (active) {
959 /* invalid */
960 emit(-1);
961 active = 0;
962 LED_A_OFF();
963 }
964 }
965 }
966
967 /* Frame end */
968 if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) {
969 emit(-1);
970 active = 0;
971 LED_A_OFF();
972 }
973
974 if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) {
975 timer->TC_CCR = AT91C_TC_CLKDIS;
976 }
977
978 old_level = level;
979 WDT_HIT();
980 }
981 if ( MF_DBGLEVEL >= 1) DbpString("Stopped");
982 LEDsoff();
983 }
984
985 //-----------------------------------------------------------------------------
986 // Code up a string of octets at layer 2 (including CRC, we don't generate
987 // that here) so that they can be transmitted to the reader. Doesn't transmit
988 // them yet, just leaves them ready to send in ToSend[].
989 //-----------------------------------------------------------------------------
990 // static void CodeLegicAsTag(const uint8_t *cmd, int len)
991 // {
992 // int i;
993
994 // ToSendReset();
995
996 // // Transmit a burst of ones, as the initial thing that lets the
997 // // reader get phase sync. This (TR1) must be > 80/fs, per spec,
998 // // but tag that I've tried (a Paypass) exceeds that by a fair bit,
999 // // so I will too.
1000 // for(i = 0; i < 20; i++) {
1001 // ToSendStuffBit(1);
1002 // ToSendStuffBit(1);
1003 // ToSendStuffBit(1);
1004 // ToSendStuffBit(1);
1005 // }
1006
1007 // // Send SOF.
1008 // for(i = 0; i < 10; i++) {
1009 // ToSendStuffBit(0);
1010 // ToSendStuffBit(0);
1011 // ToSendStuffBit(0);
1012 // ToSendStuffBit(0);
1013 // }
1014 // for(i = 0; i < 2; i++) {
1015 // ToSendStuffBit(1);
1016 // ToSendStuffBit(1);
1017 // ToSendStuffBit(1);
1018 // ToSendStuffBit(1);
1019 // }
1020
1021 // for(i = 0; i < len; i++) {
1022 // int j;
1023 // uint8_t b = cmd[i];
1024
1025 // // Start bit
1026 // ToSendStuffBit(0);
1027 // ToSendStuffBit(0);
1028 // ToSendStuffBit(0);
1029 // ToSendStuffBit(0);
1030
1031 // // Data bits
1032 // for(j = 0; j < 8; j++) {
1033 // if(b & 1) {
1034 // ToSendStuffBit(1);
1035 // ToSendStuffBit(1);
1036 // ToSendStuffBit(1);
1037 // ToSendStuffBit(1);
1038 // } else {
1039 // ToSendStuffBit(0);
1040 // ToSendStuffBit(0);
1041 // ToSendStuffBit(0);
1042 // ToSendStuffBit(0);
1043 // }
1044 // b >>= 1;
1045 // }
1046
1047 // // Stop bit
1048 // ToSendStuffBit(1);
1049 // ToSendStuffBit(1);
1050 // ToSendStuffBit(1);
1051 // ToSendStuffBit(1);
1052 // }
1053
1054 // // Send EOF.
1055 // for(i = 0; i < 10; i++) {
1056 // ToSendStuffBit(0);
1057 // ToSendStuffBit(0);
1058 // ToSendStuffBit(0);
1059 // ToSendStuffBit(0);
1060 // }
1061 // for(i = 0; i < 2; i++) {
1062 // ToSendStuffBit(1);
1063 // ToSendStuffBit(1);
1064 // ToSendStuffBit(1);
1065 // ToSendStuffBit(1);
1066 // }
1067
1068 // // Convert from last byte pos to length
1069 // ToSendMax++;
1070 // }
1071
1072 //-----------------------------------------------------------------------------
1073 // The software UART that receives commands from the reader, and its state
1074 // variables.
1075 //-----------------------------------------------------------------------------
1076 /*
1077 static struct {
1078 enum {
1079 STATE_UNSYNCD,
1080 STATE_GOT_FALLING_EDGE_OF_SOF,
1081 STATE_AWAITING_START_BIT,
1082 STATE_RECEIVING_DATA
1083 } state;
1084 uint16_t shiftReg;
1085 int bitCnt;
1086 int byteCnt;
1087 int byteCntMax;
1088 int posCnt;
1089 uint8_t *output;
1090 } Uart;
1091 */
1092 /* Receive & handle a bit coming from the reader.
1093 *
1094 * This function is called 4 times per bit (every 2 subcarrier cycles).
1095 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1096 *
1097 * LED handling:
1098 * LED A -> ON once we have received the SOF and are expecting the rest.
1099 * LED A -> OFF once we have received EOF or are in error state or unsynced
1100 *
1101 * Returns: true if we received a EOF
1102 * false if we are still waiting for some more
1103 */
1104 // static RAMFUNC int HandleLegicUartBit(uint8_t bit)
1105 // {
1106 // switch(Uart.state) {
1107 // case STATE_UNSYNCD:
1108 // if(!bit) {
1109 // // we went low, so this could be the beginning of an SOF
1110 // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
1111 // Uart.posCnt = 0;
1112 // Uart.bitCnt = 0;
1113 // }
1114 // break;
1115
1116 // case STATE_GOT_FALLING_EDGE_OF_SOF:
1117 // Uart.posCnt++;
1118 // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
1119 // if(bit) {
1120 // if(Uart.bitCnt > 9) {
1121 // // we've seen enough consecutive
1122 // // zeros that it's a valid SOF
1123 // Uart.posCnt = 0;
1124 // Uart.byteCnt = 0;
1125 // Uart.state = STATE_AWAITING_START_BIT;
1126 // LED_A_ON(); // Indicate we got a valid SOF
1127 // } else {
1128 // // didn't stay down long enough
1129 // // before going high, error
1130 // Uart.state = STATE_UNSYNCD;
1131 // }
1132 // } else {
1133 // // do nothing, keep waiting
1134 // }
1135 // Uart.bitCnt++;
1136 // }
1137 // if(Uart.posCnt >= 4) Uart.posCnt = 0;
1138 // if(Uart.bitCnt > 12) {
1139 // // Give up if we see too many zeros without
1140 // // a one, too.
1141 // LED_A_OFF();
1142 // Uart.state = STATE_UNSYNCD;
1143 // }
1144 // break;
1145
1146 // case STATE_AWAITING_START_BIT:
1147 // Uart.posCnt++;
1148 // if(bit) {
1149 // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
1150 // // stayed high for too long between
1151 // // characters, error
1152 // Uart.state = STATE_UNSYNCD;
1153 // }
1154 // } else {
1155 // // falling edge, this starts the data byte
1156 // Uart.posCnt = 0;
1157 // Uart.bitCnt = 0;
1158 // Uart.shiftReg = 0;
1159 // Uart.state = STATE_RECEIVING_DATA;
1160 // }
1161 // break;
1162
1163 // case STATE_RECEIVING_DATA:
1164 // Uart.posCnt++;
1165 // if(Uart.posCnt == 2) {
1166 // // time to sample a bit
1167 // Uart.shiftReg >>= 1;
1168 // if(bit) {
1169 // Uart.shiftReg |= 0x200;
1170 // }
1171 // Uart.bitCnt++;
1172 // }
1173 // if(Uart.posCnt >= 4) {
1174 // Uart.posCnt = 0;
1175 // }
1176 // if(Uart.bitCnt == 10) {
1177 // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
1178 // {
1179 // // this is a data byte, with correct
1180 // // start and stop bits
1181 // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
1182 // Uart.byteCnt++;
1183
1184 // if(Uart.byteCnt >= Uart.byteCntMax) {
1185 // // Buffer overflowed, give up
1186 // LED_A_OFF();
1187 // Uart.state = STATE_UNSYNCD;
1188 // } else {
1189 // // so get the next byte now
1190 // Uart.posCnt = 0;
1191 // Uart.state = STATE_AWAITING_START_BIT;
1192 // }
1193 // } else if (Uart.shiftReg == 0x000) {
1194 // // this is an EOF byte
1195 // LED_A_OFF(); // Finished receiving
1196 // Uart.state = STATE_UNSYNCD;
1197 // if (Uart.byteCnt != 0) {
1198 // return TRUE;
1199 // }
1200 // } else {
1201 // // this is an error
1202 // LED_A_OFF();
1203 // Uart.state = STATE_UNSYNCD;
1204 // }
1205 // }
1206 // break;
1207
1208 // default:
1209 // LED_A_OFF();
1210 // Uart.state = STATE_UNSYNCD;
1211 // break;
1212 // }
1213
1214 // return FALSE;
1215 // }
1216 /*
1217
1218 static void UartReset() {
1219 Uart.byteCntMax = 3;
1220 Uart.state = STATE_UNSYNCD;
1221 Uart.byteCnt = 0;
1222 Uart.bitCnt = 0;
1223 Uart.posCnt = 0;
1224 memset(Uart.output, 0x00, 3);
1225 }
1226 */
1227 // static void UartInit(uint8_t *data) {
1228 // Uart.output = data;
1229 // UartReset();
1230 // }
1231
1232 //=============================================================================
1233 // An LEGIC reader. We take layer two commands, code them
1234 // appropriately, and then send them to the tag. We then listen for the
1235 // tag's response, which we leave in the buffer to be demodulated on the
1236 // PC side.
1237 //=============================================================================
1238 /*
1239 static struct {
1240 enum {
1241 DEMOD_UNSYNCD,
1242 DEMOD_PHASE_REF_TRAINING,
1243 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
1244 DEMOD_GOT_FALLING_EDGE_OF_SOF,
1245 DEMOD_AWAITING_START_BIT,
1246 DEMOD_RECEIVING_DATA
1247 } state;
1248 int bitCount;
1249 int posCount;
1250 int thisBit;
1251 uint16_t shiftReg;
1252 uint8_t *output;
1253 int len;
1254 int sumI;
1255 int sumQ;
1256 } Demod;
1257 */
1258 /*
1259 * Handles reception of a bit from the tag
1260 *
1261 * This function is called 2 times per bit (every 4 subcarrier cycles).
1262 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1263 *
1264 * LED handling:
1265 * LED C -> ON once we have received the SOF and are expecting the rest.
1266 * LED C -> OFF once we have received EOF or are unsynced
1267 *
1268 * Returns: true if we received a EOF
1269 * false if we are still waiting for some more
1270 *
1271 */
1272
1273 /*
1274 static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq)
1275 {
1276 int v = 0;
1277 int ai = ABS(ci);
1278 int aq = ABS(cq);
1279 int halfci = (ai >> 1);
1280 int halfcq = (aq >> 1);
1281
1282 switch(Demod.state) {
1283 case DEMOD_UNSYNCD:
1284
1285 CHECK_FOR_SUBCARRIER()
1286
1287 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
1288 Demod.state = DEMOD_PHASE_REF_TRAINING;
1289 Demod.sumI = ci;
1290 Demod.sumQ = cq;
1291 Demod.posCount = 1;
1292 }
1293 break;
1294
1295 case DEMOD_PHASE_REF_TRAINING:
1296 if(Demod.posCount < 8) {
1297
1298 CHECK_FOR_SUBCARRIER()
1299
1300 if (v > SUBCARRIER_DETECT_THRESHOLD) {
1301 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
1302 // note: synchronization time > 80 1/fs
1303 Demod.sumI += ci;
1304 Demod.sumQ += cq;
1305 ++Demod.posCount;
1306 } else {
1307 // subcarrier lost
1308 Demod.state = DEMOD_UNSYNCD;
1309 }
1310 } else {
1311 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
1312 }
1313 break;
1314
1315 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
1316
1317 MAKE_SOFT_DECISION()
1318
1319 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
1320 // logic '0' detected
1321 if (v <= 0) {
1322
1323 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
1324
1325 // start of SOF sequence
1326 Demod.posCount = 0;
1327 } else {
1328 // maximum length of TR1 = 200 1/fs
1329 if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
1330 }
1331 ++Demod.posCount;
1332 break;
1333
1334 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
1335 ++Demod.posCount;
1336
1337 MAKE_SOFT_DECISION()
1338
1339 if(v > 0) {
1340 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
1341 if(Demod.posCount < 10*2) {
1342 Demod.state = DEMOD_UNSYNCD;
1343 } else {
1344 LED_C_ON(); // Got SOF
1345 Demod.state = DEMOD_AWAITING_START_BIT;
1346 Demod.posCount = 0;
1347 Demod.len = 0;
1348 }
1349 } else {
1350 // low phase of SOF too long (> 12 etu)
1351 if(Demod.posCount > 13*2) {
1352 Demod.state = DEMOD_UNSYNCD;
1353 LED_C_OFF();
1354 }
1355 }
1356 break;
1357
1358 case DEMOD_AWAITING_START_BIT:
1359 ++Demod.posCount;
1360
1361 MAKE_SOFT_DECISION()
1362
1363 if(v > 0) {
1364 // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
1365 if(Demod.posCount > 3*2) {
1366 Demod.state = DEMOD_UNSYNCD;
1367 LED_C_OFF();
1368 }
1369 } else {
1370 // start bit detected
1371 Demod.bitCount = 0;
1372 Demod.posCount = 1; // this was the first half
1373 Demod.thisBit = v;
1374 Demod.shiftReg = 0;
1375 Demod.state = DEMOD_RECEIVING_DATA;
1376 }
1377 break;
1378
1379 case DEMOD_RECEIVING_DATA:
1380
1381 MAKE_SOFT_DECISION()
1382
1383 if(Demod.posCount == 0) {
1384 // first half of bit
1385 Demod.thisBit = v;
1386 Demod.posCount = 1;
1387 } else {
1388 // second half of bit
1389 Demod.thisBit += v;
1390 Demod.shiftReg >>= 1;
1391 // logic '1'
1392 if(Demod.thisBit > 0)
1393 Demod.shiftReg |= 0x200;
1394
1395 ++Demod.bitCount;
1396
1397 if(Demod.bitCount == 10) {
1398
1399 uint16_t s = Demod.shiftReg;
1400
1401 if((s & 0x200) && !(s & 0x001)) {
1402 // stop bit == '1', start bit == '0'
1403 uint8_t b = (s >> 1);
1404 Demod.output[Demod.len] = b;
1405 ++Demod.len;
1406 Demod.state = DEMOD_AWAITING_START_BIT;
1407 } else {
1408 Demod.state = DEMOD_UNSYNCD;
1409 LED_C_OFF();
1410
1411 if(s == 0x000) {
1412 // This is EOF (start, stop and all data bits == '0'
1413 return TRUE;
1414 }
1415 }
1416 }
1417 Demod.posCount = 0;
1418 }
1419 break;
1420
1421 default:
1422 Demod.state = DEMOD_UNSYNCD;
1423 LED_C_OFF();
1424 break;
1425 }
1426 return FALSE;
1427 }
1428 */
1429 /*
1430 // Clear out the state of the "UART" that receives from the tag.
1431 static void DemodReset() {
1432 Demod.len = 0;
1433 Demod.state = DEMOD_UNSYNCD;
1434 Demod.posCount = 0;
1435 Demod.sumI = 0;
1436 Demod.sumQ = 0;
1437 Demod.bitCount = 0;
1438 Demod.thisBit = 0;
1439 Demod.shiftReg = 0;
1440 memset(Demod.output, 0x00, 3);
1441 }
1442
1443 static void DemodInit(uint8_t *data) {
1444 Demod.output = data;
1445 DemodReset();
1446 }
1447 */
1448
1449 /*
1450 * Demodulate the samples we received from the tag, also log to tracebuffer
1451 * quiet: set to 'TRUE' to disable debug output
1452 */
1453
1454 /*
1455 #define LEGIC_DMA_BUFFER_SIZE 256
1456
1457 static void GetSamplesForLegicDemod(int n, bool quiet)
1458 {
1459 int max = 0;
1460 bool gotFrame = FALSE;
1461 int lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1462 int ci, cq, samples = 0;
1463
1464 BigBuf_free();
1465
1466 // And put the FPGA in the appropriate mode
1467 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ);
1468
1469 // The response (tag -> reader) that we're receiving.
1470 // Set up the demodulator for tag -> reader responses.
1471 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1472
1473 // The DMA buffer, used to stream samples from the FPGA
1474 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE);
1475 int8_t *upTo = dmaBuf;
1476
1477 // Setup and start DMA.
1478 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){
1479 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1480 return;
1481 }
1482
1483 // Signal field is ON with the appropriate LED:
1484 LED_D_ON();
1485 for(;;) {
1486 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
1487 if(behindBy > max) max = behindBy;
1488
1489 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) {
1490 ci = upTo[0];
1491 cq = upTo[1];
1492 upTo += 2;
1493 if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) {
1494 upTo = dmaBuf;
1495 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
1496 AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE;
1497 }
1498 lastRxCounter -= 2;
1499 if(lastRxCounter <= 0)
1500 lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1501
1502 samples += 2;
1503
1504 gotFrame = HandleLegicSamplesDemod(ci , cq );
1505 if ( gotFrame )
1506 break;
1507 }
1508
1509 if(samples > n || gotFrame)
1510 break;
1511 }
1512
1513 FpgaDisableSscDma();
1514
1515 if (!quiet && Demod.len == 0) {
1516 Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
1517 max,
1518 samples,
1519 gotFrame,
1520 Demod.len,
1521 Demod.sumI,
1522 Demod.sumQ
1523 );
1524 }
1525
1526 //Tracing
1527 if (Demod.len > 0) {
1528 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1529 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
1530 }
1531 }
1532
1533 */
1534
1535 //-----------------------------------------------------------------------------
1536 // Transmit the command (to the tag) that was placed in ToSend[].
1537 //-----------------------------------------------------------------------------
1538 /*
1539 static void TransmitForLegic(void)
1540 {
1541 int c;
1542
1543 FpgaSetupSsc();
1544
1545 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
1546 AT91C_BASE_SSC->SSC_THR = 0xff;
1547
1548 // Signal field is ON with the appropriate Red LED
1549 LED_D_ON();
1550
1551 // Signal we are transmitting with the Green LED
1552 LED_B_ON();
1553 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1554
1555 for(c = 0; c < 10;) {
1556 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1557 AT91C_BASE_SSC->SSC_THR = 0xff;
1558 c++;
1559 }
1560 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1561 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1562 (void)r;
1563 }
1564 WDT_HIT();
1565 }
1566
1567 c = 0;
1568 for(;;) {
1569 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1570 AT91C_BASE_SSC->SSC_THR = ToSend[c];
1571 legic_prng_forward(1); // forward the lfsr
1572 c++;
1573 if(c >= ToSendMax) {
1574 break;
1575 }
1576 }
1577 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1578 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1579 (void)r;
1580 }
1581 WDT_HIT();
1582 }
1583 LED_B_OFF();
1584 }
1585 */
1586
1587 //-----------------------------------------------------------------------------
1588 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1589 // so that it is ready to transmit to the tag using TransmitForLegic().
1590 //-----------------------------------------------------------------------------
1591 /*
1592 static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1593 {
1594 int i, j;
1595 uint8_t b;
1596
1597 ToSendReset();
1598
1599 // Send SOF
1600 for(i = 0; i < 7; i++)
1601 ToSendStuffBit(1);
1602
1603
1604 for(i = 0; i < cmdlen; i++) {
1605 // Start bit
1606 ToSendStuffBit(0);
1607
1608 // Data bits
1609 b = cmd[i];
1610 for(j = 0; j < bits; j++) {
1611 if(b & 1) {
1612 ToSendStuffBit(1);
1613 } else {
1614 ToSendStuffBit(0);
1615 }
1616 b >>= 1;
1617 }
1618 }
1619
1620 // Convert from last character reference to length
1621 ++ToSendMax;
1622 }
1623 */
1624 /**
1625 Convenience function to encode, transmit and trace Legic comms
1626 **/
1627 /*
1628 static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1629 {
1630 CodeLegicBitsAsReader(cmd, cmdlen, bits);
1631 TransmitForLegic();
1632 if (tracing) {
1633 uint8_t parity[1] = {0x00};
1634 LogTrace(cmd, cmdlen, 0, 0, parity, TRUE);
1635 }
1636 }
1637
1638 */
1639 // Set up LEGIC communication
1640 /*
1641 void ice_legic_setup() {
1642
1643 // standard things.
1644 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1645 BigBuf_free(); BigBuf_Clear_ext(false);
1646 clear_trace();
1647 set_tracing(TRUE);
1648 DemodReset();
1649 UartReset();
1650
1651 // Set up the synchronous serial port
1652 FpgaSetupSsc();
1653
1654 // connect Demodulated Signal to ADC:
1655 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1656
1657 // Signal field is on with the appropriate LED
1658 LED_D_ON();
1659 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1660 SpinDelay(20);
1661 // Start the timer
1662 //StartCountSspClk();
1663
1664 // initalize CRC
1665 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
1666
1667 // initalize prng
1668 legic_prng_init(0);
1669 }
1670 */
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