+//-----------------------------------------------------------------------------\r
+// Routines to load the FPGA image, and then to configure the FPGA's major\r
+// mode once it is configured.\r
+//\r
+// Jonathan Westhues, April 2006\r
+//-----------------------------------------------------------------------------\r
+#include <proxmark3.h>\r
+#include "apps.h"\r
+\r
+//-----------------------------------------------------------------------------\r
+// Set up the Serial Peripheral Interface as master\r
+// Used to write the FPGA config word\r
+// May also be used to write to other SPI attached devices like an LCD\r
+//-----------------------------------------------------------------------------\r
+void SetupSpi(int mode)\r
+{\r
+ // PA10 -> SPI_NCS2 chip select (LCD)\r
+ // PA11 -> SPI_NCS0 chip select (FPGA)\r
+ // PA12 -> SPI_MISO Master-In Slave-Out\r
+ // PA13 -> SPI_MOSI Master-Out Slave-In\r
+ // PA14 -> SPI_SPCK Serial Clock\r
+\r
+ // Disable PIO control of the following pins, allows use by the SPI peripheral\r
+ PIO_DISABLE = (1 << GPIO_NCS0) |\r
+ (1 << GPIO_NCS2) |\r
+ (1 << GPIO_MISO) |\r
+ (1 << GPIO_MOSI) |\r
+ (1 << GPIO_SPCK);\r
+\r
+ PIO_PERIPHERAL_A_SEL = (1 << GPIO_NCS0) |\r
+ (1 << GPIO_MISO) |\r
+ (1 << GPIO_MOSI) |\r
+ (1 << GPIO_SPCK);\r
+\r
+ PIO_PERIPHERAL_B_SEL = (1 << GPIO_NCS2);\r
+\r
+ //enable the SPI Peripheral clock\r
+ PMC_PERIPHERAL_CLK_ENABLE = (1<<PERIPH_SPI);\r
+ // Enable SPI\r
+ SPI_CONTROL = SPI_CONTROL_ENABLE;\r
+\r
+ switch (mode) {\r
+ case SPI_FPGA_MODE:\r
+ SPI_MODE =\r
+ ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)\r
+ (14 << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)\r
+ ( 0 << 7) | // Local Loopback Disabled\r
+ ( 1 << 4) | // Mode Fault Detection disabled\r
+ ( 0 << 2) | // Chip selects connected directly to peripheral\r
+ ( 0 << 1) | // Fixed Peripheral Select\r
+ ( 1 << 0); // Master Mode\r
+ SPI_FOR_CHIPSEL_0 =\r
+ ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)\r
+ ( 1 << 16) | // Delay Before SPCK (1 MCK period)\r
+ ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
+ ( 8 << 4) | // Bits per Transfer (16 bits)\r
+ ( 0 << 3) | // Chip Select inactive after transfer\r
+ ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge\r
+ ( 0 << 0); // Clock Polarity inactive state is logic 0\r
+ break;\r
+ case SPI_LCD_MODE:\r
+ SPI_MODE =\r
+ ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)\r
+ (11 << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)\r
+ ( 0 << 7) | // Local Loopback Disabled\r
+ ( 1 << 4) | // Mode Fault Detection disabled\r
+ ( 0 << 2) | // Chip selects connected directly to peripheral\r
+ ( 0 << 1) | // Fixed Peripheral Select\r
+ ( 1 << 0); // Master Mode\r
+ SPI_FOR_CHIPSEL_2 =\r
+ ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)\r
+ ( 1 << 16) | // Delay Before SPCK (1 MCK period)\r
+ ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud\r
+ ( 1 << 4) | // Bits per Transfer (9 bits)\r
+ ( 0 << 3) | // Chip Select inactive after transfer\r
+ ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge\r
+ ( 0 << 0); // Clock Polarity inactive state is logic 0\r
+ break;\r
+ default: // Disable SPI\r
+ SPI_CONTROL = SPI_CONTROL_DISABLE;\r
+ break;\r
+ }\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Set up the synchronous serial port, with the one set of options that we\r
+// always use when we are talking to the FPGA. Both RX and TX are enabled.\r
+//-----------------------------------------------------------------------------\r
+void FpgaSetupSsc(void)\r
+{\r
+ // First configure the GPIOs, and get ourselves a clock.\r
+ PIO_PERIPHERAL_A_SEL = (1 << GPIO_SSC_FRAME) |\r
+ (1 << GPIO_SSC_DIN) |\r
+ (1 << GPIO_SSC_DOUT) |\r
+ (1 << GPIO_SSC_CLK);\r
+ PIO_DISABLE = (1 << GPIO_SSC_DOUT);\r
+\r
+ PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_SSC);\r
+\r
+ // Now set up the SSC proper, starting from a known state.\r
+ SSC_CONTROL = SSC_CONTROL_RESET;\r
+\r
+ // RX clock comes from TX clock, RX starts when TX starts, data changes\r
+ // on RX clock rising edge, sampled on falling edge\r
+ SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);\r
+\r
+ // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync\r
+ // pulse, no output sync, start on positive-going edge of sync\r
+ SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(8) |\r
+ SSC_FRAME_MODE_MSB_FIRST | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);\r
+\r
+ // clock comes from TK pin, no clock output, outputs change on falling\r
+ // edge of TK, start on rising edge of TF\r
+ SSC_TRANSMIT_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(2) |\r
+ SSC_CLOCK_MODE_START(5);\r
+\r
+ // tx framing is the same as the rx framing\r
+ SSC_TRANSMIT_FRAME_MODE = SSC_RECEIVE_FRAME_MODE;\r
+\r
+ SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Set up DMA to receive samples from the FPGA. We will use the PDC, with\r
+// a single buffer as a circular buffer (so that we just chain back to\r
+// ourselves, not to another buffer). The stuff to manipulate those buffers\r
+// is in apps.h, because it should be inlined, for speed.\r
+//-----------------------------------------------------------------------------\r
+void FpgaSetupSscDma(BYTE *buf, int len)\r
+{\r
+ PDC_RX_POINTER(SSC_BASE) = (DWORD)buf;\r
+ PDC_RX_COUNTER(SSC_BASE) = len;\r
+ PDC_RX_NEXT_POINTER(SSC_BASE) = (DWORD)buf;\r
+ PDC_RX_NEXT_COUNTER(SSC_BASE) = len;\r
+ PDC_CONTROL(SSC_BASE) = PDC_RX_ENABLE;\r
+}\r
+\r
+// Download the fpga image starting at FpgaImage and with length FpgaImageLen DWORDs (e.g. 4 bytes)\r
+// If bytereversal is set: reverse the byte order in each 4-byte word\r
+static void DownloadFPGA(const DWORD *FpgaImage, DWORD FpgaImageLen, int bytereversal)\r
+{\r
+ int i, j;\r
+\r
+ PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);\r
+ PIO_ENABLE = (1 << GPIO_FPGA_ON);\r
+ PIO_OUTPUT_DATA_SET = (1 << GPIO_FPGA_ON);\r
+\r
+ SpinDelay(50);\r
+\r
+ LED_D_ON();\r
+\r
+ HIGH(GPIO_FPGA_NPROGRAM);\r
+ LOW(GPIO_FPGA_CCLK);\r
+ LOW(GPIO_FPGA_DIN);\r
+ PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_NPROGRAM) |\r
+ (1 << GPIO_FPGA_CCLK) |\r
+ (1 << GPIO_FPGA_DIN);\r
+ SpinDelay(1);\r
+\r
+ LOW(GPIO_FPGA_NPROGRAM);\r
+ SpinDelay(50);\r
+ HIGH(GPIO_FPGA_NPROGRAM);\r
+\r
+ for(i = 0; i < FpgaImageLen; i++) {\r
+ DWORD v = FpgaImage[i];\r
+ unsigned char w;\r
+ for(j = 0; j < 4; j++) {\r
+ if(!bytereversal) \r
+ w = v >>(j*8);\r
+ else\r
+ w = v >>((3-j)*8);\r
+#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }\r
+ SEND_BIT(7);\r
+ SEND_BIT(6);\r
+ SEND_BIT(5);\r
+ SEND_BIT(4);\r
+ SEND_BIT(3);\r
+ SEND_BIT(2);\r
+ SEND_BIT(1);\r
+ SEND_BIT(0);\r
+ }\r
+ }\r
+\r
+ LED_D_OFF();\r
+}\r
+\r
+static char *bitparse_headers_start;\r
+static char *bitparse_bitstream_end;\r
+static int bitparse_initialized;\r
+/* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence\r
+ * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01\r
+ * After that the format is 1 byte section type (ASCII character), 2 byte length\r
+ * (big endian), <length> bytes content. Except for section 'e' which has 4 bytes\r
+ * length.
+ */\r
+static const char _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};\r
+static int bitparse_init(void * start_address, void *end_address)\r
+{\r
+ bitparse_initialized = 0;\r
+ \r
+ if(memcmp(_bitparse_fixed_header, start_address, sizeof(_bitparse_fixed_header)) != 0) {\r
+ return 0; /* Not matched */\r
+ } else {\r
+ bitparse_headers_start= ((char*)start_address) + sizeof(_bitparse_fixed_header);\r
+ bitparse_bitstream_end= (char*)end_address;\r
+ bitparse_initialized = 1;\r
+ return 1;\r
+ }\r
+}\r
+\r
+int bitparse_find_section(char section_name, void **section_start, unsigned int *section_length)\r
+{\r
+ char *pos = bitparse_headers_start;\r
+ int result = 0;\r
+\r
+ if(!bitparse_initialized) return 0;\r
+\r
+ while(pos < bitparse_bitstream_end) {\r
+ char current_name = *pos++;\r
+ unsigned int current_length = 0;\r
+ if(current_name < 'a' || current_name > 'e') {\r
+ /* Strange section name, abort */\r
+ break;\r
+ }\r
+ current_length = 0;\r
+ switch(current_name) {\r
+ case 'e':\r
+ /* Four byte length field */\r
+ current_length += (*pos++) << 24;\r
+ current_length += (*pos++) << 16;\r
+ default: /* Fall through, two byte length field */\r
+ current_length += (*pos++) << 8;\r
+ current_length += (*pos++) << 0;\r
+ }\r
+ \r
+ if(current_name != 'e' && current_length > 255) {\r
+ /* Maybe a parse error */\r
+ break;\r
+ }\r
+ \r
+ if(current_name == section_name) {\r
+ /* Found it */\r
+ *section_start = pos;\r
+ *section_length = current_length;\r
+ result = 1;\r
+ break;\r
+ }\r
+ \r
+ pos += current_length; /* Skip section */\r
+ }\r
+ \r
+ return result;\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Find out which FPGA image format is stored in flash, then call DownloadFPGA\r
+// with the right parameters to download the image\r
+//-----------------------------------------------------------------------------\r
+extern char _binary_fpga_bit_start, _binary_fpga_bit_end;\r
+void FpgaDownloadAndGo(void)\r
+{\r
+ /* Check for the new flash image format: Should have the .bit file at &_binary_fpga_bit_start
+ */\r
+ if(bitparse_init(&_binary_fpga_bit_start, &_binary_fpga_bit_end)) {\r
+ /* Successfully initialized the .bit parser. Find the 'e' section and\r
+ * send its contents to the FPGA.
+ */\r
+ void *bitstream_start;\r
+ unsigned int bitstream_length;\r
+ if(bitparse_find_section('e', &bitstream_start, &bitstream_length)) {\r
+ DownloadFPGA((DWORD *)bitstream_start, bitstream_length/4, 0);\r
+ \r
+ return; /* All done */\r
+ }\r
+ }\r
+ \r
+ /* Fallback for the old flash image format: Check for the magic marker 0xFFFFFFFF\r
+ * 0xAA995566 at address 0x2000. This is raw bitstream with a size of 336,768 bits \r
+ * = 10,524 DWORDs, stored as DWORDS e.g. little-endian in memory, but each DWORD\r
+ * is still to be transmitted in MSBit first order. Set the invert flag to indicate\r
+ * that the DownloadFPGA function should invert every 4 byte sequence when doing\r
+ * the bytewise download.
+ */\r
+ if( *(DWORD*)0x2000 == 0xFFFFFFFF && *(DWORD*)0x2004 == 0xAA995566 )\r
+ DownloadFPGA((DWORD *)0x2000, 10524, 1);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Send a 16 bit command/data pair to the FPGA.\r
+// The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0\r
+// where C is the 4 bit command and D is the 12 bit data\r
+//-----------------------------------------------------------------------------\r
+void FpgaSendCommand(WORD cmd, WORD v)\r
+{\r
+ SetupSpi(SPI_FPGA_MODE);\r
+ while ((SPI_STATUS & SPI_STATUS_TX_EMPTY) == 0); // wait for the transfer to complete\r
+ SPI_TX_DATA = SPI_CONTROL_LAST_TRANSFER | cmd | v; // send the data\r
+}\r
+//-----------------------------------------------------------------------------\r
+// Write the FPGA setup word (that determines what mode the logic is in, read\r
+// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to\r
+// avoid changing this function's occurence everywhere in the source code.\r
+//-----------------------------------------------------------------------------\r
+void FpgaWriteConfWord(BYTE v)\r
+{\r
+ FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);\r
+}\r
+\r
+//-----------------------------------------------------------------------------\r
+// Set up the CMOS switches that mux the ADC: four switches, independently\r
+// closable, but should only close one at a time. Not an FPGA thing, but\r
+// the samples from the ADC always flow through the FPGA.\r
+//-----------------------------------------------------------------------------\r
+void SetAdcMuxFor(int whichGpio)\r
+{\r
+ PIO_OUTPUT_ENABLE = (1 << GPIO_MUXSEL_HIPKD) |\r
+ (1 << GPIO_MUXSEL_LOPKD) |\r
+ (1 << GPIO_MUXSEL_LORAW) |\r
+ (1 << GPIO_MUXSEL_HIRAW);\r
+\r
+ PIO_ENABLE = (1 << GPIO_MUXSEL_HIPKD) |\r
+ (1 << GPIO_MUXSEL_LOPKD) |\r
+ (1 << GPIO_MUXSEL_LORAW) |\r
+ (1 << GPIO_MUXSEL_HIRAW);\r
+\r
+ LOW(GPIO_MUXSEL_HIPKD);\r
+ LOW(GPIO_MUXSEL_HIRAW);\r
+ LOW(GPIO_MUXSEL_LORAW);\r
+ LOW(GPIO_MUXSEL_LOPKD);\r
+\r
+ HIGH(whichGpio);\r
+}\r
projects / proxmark3-svn / commitdiff