rename fifo to dhwk_fifo
[raggedstone] / dhwk / fifo.xco
CommitLineData
12bc1626 1# BEGIN Project Options
2SET addpads = False
3SET asysymbol = False
4SET busformat = BusFormatAngleBracketNotRipped
5SET createndf = False
6SET designentry = VHDL
7SET device = xc3s1500
8SET devicefamily = spartan3
9SET flowvendor = Other
10SET formalverification = False
11SET foundationsym = False
12SET implementationfiletype = Ngc
13SET package = fg456
14SET removerpms = False
15SET simulationfiles = Behavioral
16SET speedgrade = -4
17SET verilogsim = False
18SET vhdlsim = True
19# END Project Options
20# BEGIN Select
21SELECT Fifo_Generator family Xilinx,_Inc. 3.2
22# END Select
23# BEGIN Parameters
24CSET almost_empty_flag=true
25CSET almost_full_flag=true
078adaa6 26CSET component_name=dhwk_fifo
12bc1626 27CSET data_count=false
28CSET data_count_width=12
29CSET dout_reset_value=0
30CSET empty_threshold_assert_value=2
31CSET empty_threshold_negate_value=3
32CSET fifo_implementation=Common_Clock_Block_RAM
33CSET full_threshold_assert_value=2048
34CSET full_threshold_negate_value=2047
35CSET input_data_width=8
36CSET input_depth=4096
37CSET output_data_width=8
38CSET output_depth=4096
39CSET overflow_flag=false
40CSET overflow_sense=Active_High
41CSET performance_options=Standard_FIFO
42CSET programmable_empty_type=No_Programmable_Empty_Threshold
43CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
44CSET read_clock_frequency=100
45CSET read_data_count=false
46CSET read_data_count_width=12
47CSET reset_pin=true
48CSET reset_type=Asynchronous_Reset
49CSET underflow_flag=false
50CSET underflow_sense=Active_High
51CSET use_extra_logic=false
52CSET valid_flag=false
53CSET valid_sense=Active_High
54CSET write_acknowledge_flag=false
55CSET write_acknowledge_sense=Active_High
56CSET write_clock_frequency=100
57CSET write_data_count=false
58CSET write_data_count_width=12
59# END Parameters
60GENERATE
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