first import of dhwk.
[raggedstone] / dhwk / source / COMM_FSM.vhd
CommitLineData
377c0242 1-- J.STELZNER\r
2-- INFORMATIK-3 LABOR\r
3-- 23.08.2006\r
4-- File: COMM_FSM.VHD\r
5\r
6library ieee;\r
7use ieee.std_logic_1164.all ;\r
8\r
9entity COMM_FSM is\r
10 port\r
11 (\r
12 PCI_CLOCK :in std_logic; \r
13 PCI_RSTn :in std_logic; \r
14 IO_READ :in std_logic;\r
15 IO_WRITE :in std_logic;\r
16 CONF_READ :in std_logic;\r
17 CONF_WRITE :in std_logic;\r
18 DEVSELn :in std_logic; \r
19\r
20 IO_RD_COM : out std_logic;--> MUX_SEL(0) \r
21 CF_RD_COM :out std_logic; \r
22 IO_WR_COM :out std_logic; \r
23 CF_WR_COM :out std_logic \r
24 );\r
25end entity COMM_FSM ;\r
26\r
27architecture COMM_FSM_DESIGN of COMM_FSM is\r
28\r
29\r
30--**********************************************************\r
31--*** COMMAND FSM CODIERUNG ***\r
32--**********************************************************\r
33--\r
34--\r
35-- |--------- IO_RD_COM \r
36-- ||-------- CF_RD_COM \r
37-- |||------- IO_WR_COM \r
38-- ||||------ CF_WR_COM \r
39-- |||| \r
40 constant ST_IDLE_COMM :std_logic_vector (3 downto 0) := "0000" ;-- \r
41 constant ST_CONF_WRITE :std_logic_vector (3 downto 0) := "0001" ;-- \r
42 constant ST_IO_WRITE :std_logic_vector (3 downto 0) := "0010" ;-- \r
43 constant ST_CONF_READ :std_logic_vector (3 downto 0) := "0100" ;-- \r
44 constant ST_IO_READ :std_logic_vector (3 downto 0) := "1000" ;--\r
45\r
46 signal COMM_STATE :std_logic_vector (3 downto 0);\r
47\r
48--************************************************************\r
49--*** FSM SPEICHER-AUTOMAT ***\r
50--************************************************************\r
51\r
52 attribute syn_state_machine : boolean;\r
53 attribute syn_state_machine of COMM_STATE : signal is false;\r
54\r
55begin\r
56\r
57--**********************************************************\r
58--*** COMMAND FSM ***\r
59--**********************************************************\r
60\r
61 process (PCI_CLOCK, PCI_RSTn) \r
62 begin\r
63 if PCI_RSTn = '0' then COMM_STATE <= "0000";\r
64\r
65 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
66 \r
67 case COMM_STATE is\r
68 \r
69 when ST_IDLE_COMM => \r
70 if IO_READ = '1' then COMM_STATE <= ST_IO_READ;\r
71\r
72 elsif CONF_READ = '1' then COMM_STATE <= ST_CONF_READ; \r
73\r
74 elsif IO_WRITE = '1' then COMM_STATE <= ST_IO_WRITE; \r
75 \r
76 elsif CONF_WRITE = '1' then COMM_STATE <= ST_CONF_WRITE; \r
77\r
78 else COMM_STATE <= ST_IDLE_COMM;\r
79 end if; \r
80 \r
81 when ST_IO_READ => if DEVSELn = '1' then COMM_STATE <= ST_IDLE_COMM; end if; \r
82 when ST_CONF_READ => if DEVSELn = '1' then COMM_STATE <= ST_IDLE_COMM; end if; \r
83 when ST_IO_WRITE => if DEVSELn = '1' then COMM_STATE <= ST_IDLE_COMM; end if; \r
84 when ST_CONF_WRITE => if DEVSELn = '1' then COMM_STATE <= ST_IDLE_COMM; end if;\r
85 \r
86 when others => COMM_STATE <= ST_IDLE_COMM; \r
87\r
88 end case; -- COMM_STATE \r
89 end if; -- CLOCK \r
90 end process; -- PROCESS\r
91\r
92 IO_RD_COM <= COMM_STATE(3); \r
93 CF_RD_COM <= COMM_STATE(2); \r
94 IO_WR_COM <= COMM_STATE(1); \r
95 CF_WR_COM <= COMM_STATE(0); \r
96 \r
97end architecture COMM_FSM_DESIGN ;\r
98\r
Impressum, Datenschutz