[raggedstone] / ethernet / source / top.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity ethernet is
PORT(
        PCI_AD : INOUT std_logic_vector(31 downto 0);
        PCI_CLOCK : IN std_logic;
        PCI_IDSEL : IN std_logic;
        PCI_CBEn : INOUT std_logic_vector (3 downto 0);
        PCI_FRAMEn : INOUT std_logic;
        PCI_IRDYn : INOUT std_logic;
        PCI_RSTn : INOUT std_logic;
        PCI_DEVSELn : INOUT std_logic;
        PCI_INTAn : INOUT std_logic;
        PCI_PERRn : INOUT std_logic;
        PCI_SERRn : INOUT std_logic;
        PCI_STOPn : INOUT std_logic;
        PCI_TRDYn : INOUT std_logic;
        PCI_PAR   : INOUT std_logic;
        PCI_REQn  : OUT std_logic;
        PCI_GNTn : IN std_logic;

        MTX_CLK_PAD_I : IN std_logic;
        MTXD_PAD_O : OUT std_logic_vector (3 downto 0);
        MTXEN_PAD_O : OUT std_logic;
        MRX_CLK_PAD_I : IN std_logic;
        MRXD_PAD_I : IN std_logic_vector (3 downto 0);
        MRXDV_PAD_I : IN std_logic;
        MRXERR_PAD_I : IN std_logic;
        MCOLL_PAD_I : IN std_logic;
        MCRS_PAD_I : IN std_logic;
        MD_PAD_IO : INOUT std_logic;
        MDC_PAD_O : OUT std_logic;

	PHY_CLOCK : OUT std_logic;

	LED_2 : OUT std_logic
);
end ethernet;

architecture ethernet_arch of ethernet is

COMPONENT eth_top
PORT(
        wb_clk_i : IN std_logic;
        wb_rst_i : IN std_logic;
        wb_dat_i : IN std_logic_vector(31 downto 0);
        wb_adr_i : IN std_logic_vector(11 downto 2);
        wb_sel_i : IN std_logic_vector(3 downto 0);
        wb_we_i : IN std_logic;
        wb_cyc_i : IN std_logic;
        wb_stb_i : IN std_logic;
        m_wb_dat_i : IN std_logic_vector(31 downto 0);
        m_wb_ack_i : IN std_logic;
        m_wb_err_i : IN std_logic;
        mtx_clk_pad_i : IN std_logic;
        mrx_clk_pad_i : IN std_logic;
        mrxd_pad_i : IN std_logic_vector(3 downto 0);
        mrxdv_pad_i : IN std_logic;
        mrxerr_pad_i : IN std_logic;
        mcoll_pad_i : IN std_logic;
        mcrs_pad_i : IN std_logic;
        md_pad_i : IN std_logic;          
        wb_dat_o : OUT std_logic_vector(31 downto 0);
        wb_ack_o : OUT std_logic;
        wb_err_o : OUT std_logic;
        m_wb_adr_o : OUT std_logic_vector(31 downto 0);
        m_wb_sel_o : OUT std_logic_vector(3 downto 0);
        m_wb_we_o : OUT std_logic;
        m_wb_dat_o : OUT std_logic_vector(31 downto 0);
        m_wb_cyc_o : OUT std_logic;
        m_wb_stb_o : OUT std_logic;
        mtxd_pad_o : OUT std_logic_vector(3 downto 0);
        mtxen_pad_o : OUT std_logic;
        mtxerr_pad_o : OUT std_logic;
        mdc_pad_o : OUT std_logic;
        md_pad_o : OUT std_logic;
        md_padoe_o : OUT std_logic;
        m_wb_cti_o : OUT std_logic_vector(2 downto 0);
        m_wb_bte_o : OUT std_logic_vector(1 downto 0);
        int_o : OUT std_logic
        );
END COMPONENT;

COMPONENT pci_bridge32
PORT(
        wb_clk_i : IN std_logic;
        wb_rst_i : IN std_logic;
        wb_int_i : IN std_logic;
        wbs_adr_i : IN std_logic_vector(31 downto 0);
        wbs_dat_i : IN std_logic_vector(31 downto 0);
        wbs_sel_i : IN std_logic_vector(3 downto 0);
        wbs_cyc_i : IN std_logic;
        wbs_stb_i : IN std_logic;
        wbs_we_i : IN std_logic;
        wbs_cti_i : IN std_logic_vector(2 downto 0);
        wbs_bte_i : IN std_logic_vector(1 downto 0);
        wbm_dat_i : IN std_logic_vector(31 downto 0);
        wbm_ack_i : IN std_logic;
        wbm_rty_i : IN std_logic;
        wbm_err_i : IN std_logic;
        pci_clk_i : IN std_logic;
        pci_rst_i : IN std_logic;
        pci_inta_i : IN std_logic;
        pci_gnt_i : IN std_logic;
        pci_frame_i : IN std_logic;
        pci_irdy_i : IN std_logic;
        pci_idsel_i : IN std_logic;
        pci_devsel_i : IN std_logic;
        pci_trdy_i : IN std_logic;
        pci_stop_i : IN std_logic;
        pci_ad_i : IN std_logic_vector(31 downto 0);
        pci_cbe_i : IN std_logic_vector(3 downto 0);
        pci_par_i : IN std_logic;
        pci_perr_i : IN std_logic;          
        wb_rst_o : OUT std_logic;
        wb_int_o : OUT std_logic;
        wbs_dat_o : OUT std_logic_vector(31 downto 0);
        wbs_ack_o : OUT std_logic;
        wbs_rty_o : OUT std_logic;
        wbs_err_o : OUT std_logic;
        wbm_adr_o : OUT std_logic_vector(31 downto 0);
        wbm_dat_o : OUT std_logic_vector(31 downto 0);
        wbm_sel_o : OUT std_logic_vector(3 downto 0);
        wbm_cyc_o : OUT std_logic;
        wbm_stb_o : OUT std_logic;
        wbm_we_o : OUT std_logic;
        wbm_cti_o : OUT std_logic_vector(2 downto 0);
        wbm_bte_o : OUT std_logic_vector(1 downto 0);
        pci_rst_o : OUT std_logic;
        pci_inta_o : OUT std_logic;
        pci_rst_oe_o : OUT std_logic;
        pci_inta_oe_o : OUT std_logic;
        pci_req_o : OUT std_logic;
        pci_req_oe_o : OUT std_logic;
        pci_frame_o : OUT std_logic;
        pci_frame_oe_o : OUT std_logic;
        pci_irdy_oe_o : OUT std_logic;
        pci_devsel_oe_o : OUT std_logic;
        pci_trdy_oe_o : OUT std_logic;
        pci_stop_oe_o : OUT std_logic;
        pci_ad_oe_o : OUT std_logic_vector(31 downto 0);
        pci_cbe_oe_o : OUT std_logic_vector(3 downto 0);
        pci_irdy_o : OUT std_logic;
        pci_devsel_o : OUT std_logic;
        pci_trdy_o : OUT std_logic;
        pci_stop_o : OUT std_logic;
        pci_ad_o : OUT std_logic_vector(31 downto 0);
        pci_cbe_o : OUT std_logic_vector(3 downto 0);
        pci_par_o : OUT std_logic;
        pci_par_oe_o : OUT std_logic;
        pci_perr_o : OUT std_logic;
        pci_perr_oe_o : OUT std_logic;
        pci_serr_o : OUT std_logic;
        pci_serr_oe_o : OUT std_logic
        );
END COMPONENT;

component icon
port (
	control0 : out std_logic_vector(35 downto 0)
	);
end component;

component ila
port (
	control : in std_logic_vector(35 downto 0);
	clk : in std_logic;
	data : in std_logic_vector(63 downto 0);
	trig0 : in std_logic_vector(31 downto 0)
	);
end component;

component phydcm is
port ( CLKIN_IN        : in    std_logic;
       RST_IN          : in    std_logic;
       CLKFX_OUT       : out   std_logic;
       CLK0_OUT        : out   std_logic;
       LOCKED_OUT      : out   std_logic);
end component;

signal pci_rst_o : std_logic;
signal pci_rst_oe_o : std_logic;
signal pci_inta_o : std_logic;
signal pci_inta_oe_o : std_logic;
signal pci_req_o : std_logic;
signal pci_req_oe_o : std_logic;
signal pci_frame_o : std_logic;
signal pci_frame_oe_o : std_logic;
signal pci_irdy_o : std_logic;
signal pci_irdy_oe_o : std_logic;
signal pci_devsel_o : std_logic;
signal pci_devsel_oe_o : std_logic;
signal pci_trdy_o : std_logic;
signal pci_trdy_oe_o : std_logic;
signal pci_stop_o : std_logic;
signal pci_stop_oe_o : std_logic;
signal pci_par_o : std_logic;
signal pci_par_oe_o : std_logic;
signal pci_perr_o : std_logic;
signal pci_perr_oe_o : std_logic;
signal pci_serr_o : std_logic;
signal pci_serr_oe_o : std_logic;
signal pci_ad_oe_o : std_logic_vector(31 downto 0);
signal pci_cbe_oe_o : std_logic_vector(3 downto 0);
signal pci_ad_o : std_logic_vector (31 downto 0);
signal pci_cbe_o : std_logic_vector (3 downto 0);

signal wb_clk_i : std_logic;
signal wb_rst_i : std_logic;
signal wb_dat_i : std_logic_vector (31 downto 0);
signal wb_dat_o : std_logic_vector (31 downto 0);
signal wb_adr_i : std_logic_vector (11 downto 2);
signal wb_sel_i : std_logic_vector (3 downto 0);
signal wb_we_i : std_logic;
signal wb_cyc_i : std_logic;
signal wb_stb_i : std_logic;
signal wb_ack_o : std_logic;
signal wb_err_o : std_logic;
signal m_wb_adr_o : std_logic_vector(31 downto 0);
signal m_wb_sel_o : std_logic_vector(3 downto 0);
signal m_wb_we_o : std_logic;
signal m_wb_dat_o : std_logic_vector(31 downto 0);
signal m_wb_dat_i : std_logic_vector(31 downto 0);
signal m_wb_cyc_o : std_logic;
signal m_wb_stb_o : std_logic;
signal m_wb_ack_i : std_logic;
signal m_wb_err_i : std_logic;
signal md_pad_o : std_logic;
signal md_padoe_o : std_logic;
signal int_o : std_logic;
signal wbm_adr_o : std_logic_vector(31 downto 0);

signal m_wb_cti_o : std_logic_vector(2 downto 0);
signal m_wb_bte_o : std_logic_vector(1 downto 0);

signal control0 : std_logic_vector(35 downto 0);
signal data : std_logic_vector(63 downto 0);
signal trig0 : std_logic_vector(31 downto 0);


BEGIN

PCI_RSTn    <= pci_rst_o    when (pci_rst_oe_o = '1')     else 'Z';
PCI_INTAn   <= pci_inta_o   when (pci_inta_oe_o = '1')    else 'Z';
PCI_REQn    <= pci_req_o    when (pci_req_oe_o = '1')     else 'Z';
PCI_FRAMEn  <= pci_frame_o  when (pci_frame_oe_o = '1')     else 'Z';
PCI_IRDYn   <= pci_irdy_o   when (pci_irdy_oe_o = '1')    else 'Z';
PCI_DEVSELn <= pci_devsel_o when (pci_devsel_oe_o = '1')  else 'Z';
PCI_TRDYn   <= pci_trdy_o   when (pci_trdy_oe_o = '1')    else 'Z';
PCI_STOPn   <= pci_stop_o   when (pci_stop_oe_o = '1')    else 'Z';
PCI_PAR     <= pci_par_o    when (pci_par_oe_o = '1')     else 'Z';
PCI_PERRn   <= pci_perr_o   when (pci_perr_oe_o = '1')    else 'Z';
PCI_SERRn   <= pci_serr_o   when (pci_serr_oe_o = '1')    else 'Z';
MD_PAD_IO   <= md_pad_o     when (md_padoe_o = '1')       else 'Z';

BLA1: FOR i in 31 downto 0 generate
PCI_AD(i) <= pci_ad_o(i) when (pci_ad_oe_o(i) = '1') else 'Z';
end generate;

BLA2: FOR i in 3 downto 0 generate
PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
end generate;

wb_adr_i(11 downto 8) <= (others => '0');
wb_adr_i(7 downto 2)  <= wbm_adr_o (7 downto 2);

wb_clk_i <= PCI_CLOCK;

data(31 downto 0)  <= wbm_adr_o;
data(40 downto 33) <= wbm_adr_o (7 downto 0);
data(63 downto 41) <= (others => '0');

trig0(31 downto 0) <= (
	0 => wb_stb_i,
	others => '0'
);

Inst_pci_bridge32: pci_bridge32 PORT MAP(
        wb_clk_i => wb_clk_i ,
        wb_rst_i => '0',
        wb_rst_o => wb_rst_i,
        wb_int_i => int_o,
        -- wb_int_o => ,
        wbs_adr_i => m_wb_adr_o ,
        wbs_dat_i => m_wb_dat_o,
        wbs_dat_o => m_wb_dat_i,
        wbs_sel_i => m_wb_sel_o,
        wbs_cyc_i => m_wb_cyc_o,
        wbs_stb_i => m_wb_stb_o,
        wbs_we_i => m_wb_we_o,
        wbs_cti_i => m_wb_cti_o,
        wbs_bte_i => m_wb_bte_o,
        wbs_ack_o => m_wb_ack_i,
        -- wbs_rty_o => ,
        wbs_err_o => m_wb_err_i,
        wbm_adr_o => wbm_adr_o,
        wbm_dat_i => wb_dat_o,
        wbm_dat_o => wb_dat_i,
        wbm_sel_o => wb_sel_i,
        wbm_cyc_o => wb_cyc_i,
        wbm_stb_o => wb_stb_i,
        wbm_we_o => wb_we_i,
        -- wbm_cti_o => ,
        -- wbm_bte_o => ,
        wbm_ack_i => wb_ack_o ,
        wbm_rty_i => '0',
        wbm_err_i => wb_err_o,
        pci_clk_i => PCI_CLOCK,
        pci_rst_i => PCI_RSTn,
        pci_rst_o => pci_rst_o ,
        pci_rst_oe_o => pci_rst_oe_o,
        pci_inta_i => PCI_INTAn,
        pci_inta_o => pci_inta_o,
        pci_inta_oe_o => pci_inta_oe_o,
        pci_req_o => pci_req_o,
        pci_req_oe_o => pci_req_oe_o,
        pci_gnt_i => PCI_GNTn,
        pci_frame_i => PCI_FRAMEn,
        pci_frame_o => pci_frame_o,
        pci_frame_oe_o => pci_frame_oe_o,
        pci_irdy_oe_o => pci_irdy_oe_o,
        pci_devsel_oe_o => pci_devsel_oe_o,
        pci_trdy_oe_o => pci_trdy_oe_o,
        pci_stop_oe_o => pci_stop_oe_o,
        pci_ad_oe_o => pci_ad_oe_o,
        pci_cbe_oe_o => pci_cbe_oe_o,
        pci_irdy_i => PCI_IRDYn,
        pci_irdy_o => pci_irdy_o,
        pci_idsel_i => PCI_IDSEL,
        pci_devsel_i => PCI_DEVSELn,
        pci_devsel_o => pci_devsel_o,
        pci_trdy_i => PCI_TRDYn,
        pci_trdy_o => pci_trdy_o,
        pci_stop_i => PCI_STOPn,
        pci_stop_o => pci_stop_o,
        pci_ad_i => PCI_AD,
        pci_ad_o => pci_ad_o,
        pci_cbe_i => PCI_CBEn,
        pci_cbe_o => pci_cbe_o,
        pci_par_i => PCI_PAR,
        pci_par_o => pci_par_o,
        pci_par_oe_o => pci_par_oe_o,
        pci_perr_i => PCI_PERRn,
        pci_perr_o => pci_perr_o,
        pci_perr_oe_o => pci_perr_oe_o,
        pci_serr_o => pci_serr_o,
        pci_serr_oe_o =>  pci_serr_oe_o
);

Inst_eth_top: eth_top PORT MAP(
        wb_clk_i   => wb_clk_i  ,
        wb_rst_i   => wb_rst_i  ,
        wb_dat_i   => wb_dat_i  ,
        wb_dat_o   => wb_dat_o  ,
        wb_adr_i   => wb_adr_i  ,
        wb_sel_i   => wb_sel_i  ,
        wb_we_i    => wb_we_i   ,
        wb_cyc_i   => wb_cyc_i  ,
        wb_stb_i   => wb_stb_i,
        wb_ack_o   => wb_ack_o  ,
        wb_err_o   => wb_err_o  ,
        m_wb_adr_o => m_wb_adr_o,
        m_wb_sel_o => m_wb_sel_o,
        m_wb_we_o  => m_wb_we_o ,
        m_wb_dat_o => m_wb_dat_o,
        m_wb_dat_i => m_wb_dat_i,
        m_wb_cyc_o => m_wb_cyc_o,
        m_wb_stb_o => m_wb_stb_o,
        m_wb_ack_i => m_wb_ack_i,
        m_wb_err_i => m_wb_err_i,
        mtx_clk_pad_i => MTX_CLK_PAD_I,
        mtxd_pad_o => MTXD_PAD_O,
        mtxen_pad_o => MTXEN_PAD_O,
        mtxerr_pad_o => LED_2,
        mrx_clk_pad_i => MRX_CLK_PAD_I,
        mrxd_pad_i => MRXD_PAD_I,
        mrxdv_pad_i => MRXDV_PAD_I,
        mrxerr_pad_i => MRXERR_PAD_I,
        mcoll_pad_i => MCOLL_PAD_I,
        mcrs_pad_i => MCRS_PAD_I,
        mdc_pad_o => MDC_PAD_O,
        md_pad_i => MD_PAD_IO,
        md_pad_o => md_pad_o,
        md_padoe_o => md_padoe_o,
        m_wb_cti_o => m_wb_cti_o,
        m_wb_bte_o => m_wb_bte_o, 
        int_o => int_o
);

i_icon : icon
port map (
	control0 => control0
	);

i_ila : ila
port map (
	control => control0,
	clk => PCI_CLOCK,
	data => data,
	trig0 => trig0
	);

eth_dcm : phydcm
port map (
	CLKIN_IN => PCI_CLOCK,
	RST_IN => not PCI_RSTn,
	CLKFX_OUT => PHY_CLOCK,
	CLK0_OUT => open,
	LOCKED_OUT => open
	);

end architecture ethernet_arch;
Commit	Line	Data
27f6f620	1	LIBRARY ieee;
	2	USE ieee.std_logic_1164.ALL;
	3
	4	entity ethernet is
40a1f26c	5	PORT(
	6	PCI_AD : INOUT std_logic_vector(31 downto 0);
	7	PCI_CLOCK : IN std_logic;
	8	PCI_IDSEL : IN std_logic;
	9	PCI_CBEn : INOUT std_logic_vector (3 downto 0);
	10	PCI_FRAMEn : INOUT std_logic;
	11	PCI_IRDYn : INOUT std_logic;
	12	PCI_RSTn : INOUT std_logic;
	13	PCI_DEVSELn : INOUT std_logic;
	14	PCI_INTAn : INOUT std_logic;
	15	PCI_PERRn : INOUT std_logic;
	16	PCI_SERRn : INOUT std_logic;
	17	PCI_STOPn : INOUT std_logic;
	18	PCI_TRDYn : INOUT std_logic;
	19	PCI_PAR : INOUT std_logic;
	20	PCI_REQn : OUT std_logic;
	21	PCI_GNTn : IN std_logic;
	22
	23	MTX_CLK_PAD_I : IN std_logic;
	24	MTXD_PAD_O : OUT std_logic_vector (3 downto 0);
	25	MTXEN_PAD_O : OUT std_logic;
	26	MRX_CLK_PAD_I : IN std_logic;
	27	MRXD_PAD_I : IN std_logic_vector (3 downto 0);
	28	MRXDV_PAD_I : IN std_logic;
	29	MRXERR_PAD_I : IN std_logic;
	30	MCOLL_PAD_I : IN std_logic;
	31	MCRS_PAD_I : IN std_logic;
	32	MD_PAD_IO : INOUT std_logic;
4d7b5fdd	33	MDC_PAD_O : OUT std_logic;
4d7b5fdd	34
7a6a1ff7	35	PHY_CLOCK : OUT std_logic;
7a6a1ff7	36
4d7b5fdd	37	LED_2 : OUT std_logic
40a1f26c	38	);
27f6f620	39	end ethernet;
40a1f26c	40
27f6f620	41	architecture ethernet_arch of ethernet is
40a1f26c	42
	43	COMPONENT eth_top
	44	PORT(
	45	wb_clk_i : IN std_logic;
	46	wb_rst_i : IN std_logic;
	47	wb_dat_i : IN std_logic_vector(31 downto 0);
	48	wb_adr_i : IN std_logic_vector(11 downto 2);
	49	wb_sel_i : IN std_logic_vector(3 downto 0);
	50	wb_we_i : IN std_logic;
	51	wb_cyc_i : IN std_logic;
	52	wb_stb_i : IN std_logic;
	53	m_wb_dat_i : IN std_logic_vector(31 downto 0);
	54	m_wb_ack_i : IN std_logic;
	55	m_wb_err_i : IN std_logic;
	56	mtx_clk_pad_i : IN std_logic;
	57	mrx_clk_pad_i : IN std_logic;
	58	mrxd_pad_i : IN std_logic_vector(3 downto 0);
	59	mrxdv_pad_i : IN std_logic;
	60	mrxerr_pad_i : IN std_logic;
	61	mcoll_pad_i : IN std_logic;
	62	mcrs_pad_i : IN std_logic;
	63	md_pad_i : IN std_logic;
	64	wb_dat_o : OUT std_logic_vector(31 downto 0);
	65	wb_ack_o : OUT std_logic;
	66	wb_err_o : OUT std_logic;
	67	m_wb_adr_o : OUT std_logic_vector(31 downto 0);
	68	m_wb_sel_o : OUT std_logic_vector(3 downto 0);
	69	m_wb_we_o : OUT std_logic;
	70	m_wb_dat_o : OUT std_logic_vector(31 downto 0);
	71	m_wb_cyc_o : OUT std_logic;
	72	m_wb_stb_o : OUT std_logic;
	73	mtxd_pad_o : OUT std_logic_vector(3 downto 0);
	74	mtxen_pad_o : OUT std_logic;
	75	mtxerr_pad_o : OUT std_logic;
	76	mdc_pad_o : OUT std_logic;
	77	md_pad_o : OUT std_logic;
	78	md_padoe_o : OUT std_logic;
361ec26f	79	m_wb_cti_o : OUT std_logic_vector(2 downto 0);
361ec26f	80	m_wb_bte_o : OUT std_logic_vector(1 downto 0);
40a1f26c	81	int_o : OUT std_logic
	82	);
	83	END COMPONENT;
	84
	85	COMPONENT pci_bridge32
	86	PORT(
	87	wb_clk_i : IN std_logic;
	88	wb_rst_i : IN std_logic;
	89	wb_int_i : IN std_logic;
	90	wbs_adr_i : IN std_logic_vector(31 downto 0);
	91	wbs_dat_i : IN std_logic_vector(31 downto 0);
	92	wbs_sel_i : IN std_logic_vector(3 downto 0);
	93	wbs_cyc_i : IN std_logic;
	94	wbs_stb_i : IN std_logic;
	95	wbs_we_i : IN std_logic;
	96	wbs_cti_i : IN std_logic_vector(2 downto 0);
	97	wbs_bte_i : IN std_logic_vector(1 downto 0);
	98	wbm_dat_i : IN std_logic_vector(31 downto 0);
	99	wbm_ack_i : IN std_logic;
	100	wbm_rty_i : IN std_logic;
	101	wbm_err_i : IN std_logic;
	102	pci_clk_i : IN std_logic;
	103	pci_rst_i : IN std_logic;
	104	pci_inta_i : IN std_logic;
	105	pci_gnt_i : IN std_logic;
	106	pci_frame_i : IN std_logic;
	107	pci_irdy_i : IN std_logic;
	108	pci_idsel_i : IN std_logic;
	109	pci_devsel_i : IN std_logic;
	110	pci_trdy_i : IN std_logic;
	111	pci_stop_i : IN std_logic;
	112	pci_ad_i : IN std_logic_vector(31 downto 0);
	113	pci_cbe_i : IN std_logic_vector(3 downto 0);
	114	pci_par_i : IN std_logic;
	115	pci_perr_i : IN std_logic;
	116	wb_rst_o : OUT std_logic;
	117	wb_int_o : OUT std_logic;
	118	wbs_dat_o : OUT std_logic_vector(31 downto 0);
	119	wbs_ack_o : OUT std_logic;
	120	wbs_rty_o : OUT std_logic;
	121	wbs_err_o : OUT std_logic;
	122	wbm_adr_o : OUT std_logic_vector(31 downto 0);
	123	wbm_dat_o : OUT std_logic_vector(31 downto 0);
	124	wbm_sel_o : OUT std_logic_vector(3 downto 0);
	125	wbm_cyc_o : OUT std_logic;
	126	wbm_stb_o : OUT std_logic;
	127	wbm_we_o : OUT std_logic;
	128	wbm_cti_o : OUT std_logic_vector(2 downto 0);
	129	wbm_bte_o : OUT std_logic_vector(1 downto 0);
	130	pci_rst_o : OUT std_logic;
	131	pci_inta_o : OUT std_logic;
	132	pci_rst_oe_o : OUT std_logic;
	133	pci_inta_oe_o : OUT std_logic;
	134	pci_req_o : OUT std_logic;
	135	pci_req_oe_o : OUT std_logic;
	136	pci_frame_o : OUT std_logic;
	137	pci_frame_oe_o : OUT std_logic;
	138	pci_irdy_oe_o : OUT std_logic;
	139	pci_devsel_oe_o : OUT std_logic;
	140	pci_trdy_oe_o : OUT std_logic;
	141	pci_stop_oe_o : OUT std_logic;
	142	pci_ad_oe_o : OUT std_logic_vector(31 downto 0);
	143	pci_cbe_oe_o : OUT std_logic_vector(3 downto 0);
	144	pci_irdy_o : OUT std_logic;
145	pci_devsel_o : OUT std_logic;
146	pci_trdy_o : OUT std_logic;
147	pci_stop_o : OUT std_logic;
148	pci_ad_o : OUT std_logic_vector(31 downto 0);
149	pci_cbe_o : OUT std_logic_vector(3 downto 0);
150	pci_par_o : OUT std_logic;
151	pci_par_oe_o : OUT std_logic;
152	pci_perr_o : OUT std_logic;
153	pci_perr_oe_o : OUT std_logic;
154	pci_serr_o : OUT std_logic;
155	pci_serr_oe_o : OUT std_logic
156	);
157	END COMPONENT;
158
c8b3e197	159	component icon
	160	port (
	161	control0 : out std_logic_vector(35 downto 0)
70f633de	162	);
c8b3e197	163	end component;
	164
	165	component ila
	166	port (
	167	control : in std_logic_vector(35 downto 0);
	168	clk : in std_logic;
	169	data : in std_logic_vector(63 downto 0);
	170	trig0 : in std_logic_vector(31 downto 0)
	171	);
	172	end component;
70f633de	173
ac5b8271	174	component phydcm is
	175	port ( CLKIN_IN : in std_logic;
	176	RST_IN : in std_logic;
	177	CLKFX_OUT : out std_logic;
ac5b8271	178	CLK0_OUT : out std_logic;
	179	LOCKED_OUT : out std_logic);
	180	end component;
	181
40a1f26c	182	signal pci_rst_o : std_logic;
	183	signal pci_rst_oe_o : std_logic;
	184	signal pci_inta_o : std_logic;
	185	signal pci_inta_oe_o : std_logic;
	186	signal pci_req_o : std_logic;
	187	signal pci_req_oe_o : std_logic;
	188	signal pci_frame_o : std_logic;
	189	signal pci_frame_oe_o : std_logic;
	190	signal pci_irdy_o : std_logic;
	191	signal pci_irdy_oe_o : std_logic;
	192	signal pci_devsel_o : std_logic;
	193	signal pci_devsel_oe_o : std_logic;
	194	signal pci_trdy_o : std_logic;
	195	signal pci_trdy_oe_o : std_logic;
	196	signal pci_stop_o : std_logic;
	197	signal pci_stop_oe_o : std_logic;
	198	signal pci_par_o : std_logic;
	199	signal pci_par_oe_o : std_logic;
	200	signal pci_perr_o : std_logic;
	201	signal pci_perr_oe_o : std_logic;
	202	signal pci_serr_o : std_logic;
	203	signal pci_serr_oe_o : std_logic;
27f6f620	204	signal pci_ad_oe_o : std_logic_vector(31 downto 0);
27f6f620	205	signal pci_cbe_oe_o : std_logic_vector(3 downto 0);
40a1f26c	206	signal pci_ad_o : std_logic_vector (31 downto 0);
	207	signal pci_cbe_o : std_logic_vector (3 downto 0);
	208
27f6f620	209	signal wb_clk_i : std_logic;
	210	signal wb_rst_i : std_logic;
	211	signal wb_dat_i : std_logic_vector (31 downto 0);
	212	signal wb_dat_o : std_logic_vector (31 downto 0);
	213	signal wb_adr_i : std_logic_vector (11 downto 2);
	214	signal wb_sel_i : std_logic_vector (3 downto 0);
	215	signal wb_we_i : std_logic;
	216	signal wb_cyc_i : std_logic;
	217	signal wb_stb_i : std_logic;
	218	signal wb_ack_o : std_logic;
	219	signal wb_err_o : std_logic;
	220	signal m_wb_adr_o : std_logic_vector(31 downto 0);
	221	signal m_wb_sel_o : std_logic_vector(3 downto 0);
	222	signal m_wb_we_o : std_logic;
	223	signal m_wb_dat_o : std_logic_vector(31 downto 0);
	224	signal m_wb_dat_i : std_logic_vector(31 downto 0);
	225	signal m_wb_cyc_o : std_logic;
	226	signal m_wb_stb_o : std_logic;
	227	signal m_wb_ack_i : std_logic;
	228	signal m_wb_err_i : std_logic;
	229	signal md_pad_o : std_logic;
	230	signal md_padoe_o : std_logic;
	231	signal int_o : std_logic;
	232	signal wbm_adr_o : std_logic_vector(31 downto 0);
	233
361ec26f	234	signal m_wb_cti_o : std_logic_vector(2 downto 0);
	235	signal m_wb_bte_o : std_logic_vector(1 downto 0);
	236
c8b3e197	237	signal control0 : std_logic_vector(35 downto 0);
	238	signal data : std_logic_vector(63 downto 0);
	239	signal trig0 : std_logic_vector(31 downto 0);
	240
	241
40a1f26c	242	BEGIN
40a1f26c	243
221bd70b	244	PCI_RSTn <= pci_rst_o when (pci_rst_oe_o = '1') else 'Z';
	245	PCI_INTAn <= pci_inta_o when (pci_inta_oe_o = '1') else 'Z';
	246	PCI_REQn <= pci_req_o when (pci_req_oe_o = '1') else 'Z';
	247	PCI_FRAMEn <= pci_frame_o when (pci_frame_oe_o = '1') else 'Z';
	248	PCI_IRDYn <= pci_irdy_o when (pci_irdy_oe_o = '1') else 'Z';
	249	PCI_DEVSELn <= pci_devsel_o when (pci_devsel_oe_o = '1') else 'Z';
	250	PCI_TRDYn <= pci_trdy_o when (pci_trdy_oe_o = '1') else 'Z';
	251	PCI_STOPn <= pci_stop_o when (pci_stop_oe_o = '1') else 'Z';
27f6f620	252	PCI_PAR <= pci_par_o when (pci_par_oe_o = '1') else 'Z';
221bd70b	253	PCI_PERRn <= pci_perr_o when (pci_perr_oe_o = '1') else 'Z';
221bd70b	254	PCI_SERRn <= pci_serr_o when (pci_serr_oe_o = '1') else 'Z';
27f6f620	255	MD_PAD_IO <= md_pad_o when (md_padoe_o = '1') else 'Z';
	256
	257	BLA1: FOR i in 31 downto 0 generate
	258	PCI_AD(i) <= pci_ad_o(i) when (pci_ad_oe_o(i) = '1') else 'Z';
	259	end generate;
	260
	261	BLA2: FOR i in 3 downto 0 generate
	262	PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
	263	end generate;
	264
1a94112a	265	wb_adr_i(11 downto 8) <= (others => '0');
1a94112a	266	wb_adr_i(7 downto 2) <= wbm_adr_o (7 downto 2);
23944ea1	267
2c4b2f25	268	wb_clk_i <= PCI_CLOCK;
2c4b2f25	269
23944ea1	270	data(31 downto 0) <= wbm_adr_o;
	271	data(40 downto 33) <= wbm_adr_o (7 downto 0);
	272	data(63 downto 41) <= (others => '0');
c8b3e197	273
0d71737f	274	trig0(31 downto 0) <= (
c8b3e197	275	0 => wb_stb_i,
	276	others => '0'
	277	);
	278
40a1f26c	279	Inst_pci_bridge32: pci_bridge32 PORT MAP(
27f6f620	280	wb_clk_i => wb_clk_i ,
	281	wb_rst_i => '0',
	282	wb_rst_o => wb_rst_i,
	283	wb_int_i => int_o,
	284	-- wb_int_o => ,
	285	wbs_adr_i => m_wb_adr_o ,
	286	wbs_dat_i => m_wb_dat_o,
	287	wbs_dat_o => m_wb_dat_i,
	288	wbs_sel_i => m_wb_sel_o,
	289	wbs_cyc_i => m_wb_cyc_o,
	290	wbs_stb_i => m_wb_stb_o,
	291	wbs_we_i => m_wb_we_o,
361ec26f	292	wbs_cti_i => m_wb_cti_o,
361ec26f	293	wbs_bte_i => m_wb_bte_o,
27f6f620	294	wbs_ack_o => m_wb_ack_i,
	295	-- wbs_rty_o => ,
	296	wbs_err_o => m_wb_err_i,
	297	wbm_adr_o => wbm_adr_o,
	298	wbm_dat_i => wb_dat_o,
	299	wbm_dat_o => wb_dat_i,
	300	wbm_sel_o => wb_sel_i,
	301	wbm_cyc_o => wb_cyc_i,
	302	wbm_stb_o => wb_stb_i,
	303	wbm_we_o => wb_we_i,
	304	-- wbm_cti_o => ,
	305	-- wbm_bte_o => ,
	306	wbm_ack_i => wb_ack_o ,
	307	wbm_rty_i => '0',
	308	wbm_err_i => wb_err_o,
40a1f26c	309	pci_clk_i => PCI_CLOCK,
221bd70b	310	pci_rst_i => PCI_RSTn,
40a1f26c	311	pci_rst_o => pci_rst_o ,
40a1f26c	312	pci_rst_oe_o => pci_rst_oe_o,
221bd70b	313	pci_inta_i => PCI_INTAn,
40a1f26c	314	pci_inta_o => pci_inta_o,
	315	pci_inta_oe_o => pci_inta_oe_o,
	316	pci_req_o => pci_req_o,
	317	pci_req_oe_o => pci_req_oe_o,
221bd70b	318	pci_gnt_i => PCI_GNTn,
221bd70b	319	pci_frame_i => PCI_FRAMEn,
40a1f26c	320	pci_frame_o => pci_frame_o,
	321	pci_frame_oe_o => pci_frame_oe_o,
	322	pci_irdy_oe_o => pci_irdy_oe_o,
	323	pci_devsel_oe_o => pci_devsel_oe_o,
	324	pci_trdy_oe_o => pci_trdy_oe_o,
	325	pci_stop_oe_o => pci_stop_oe_o,
	326	pci_ad_oe_o => pci_ad_oe_o,
	327	pci_cbe_oe_o => pci_cbe_oe_o,
221bd70b	328	pci_irdy_i => PCI_IRDYn,
40a1f26c	329	pci_irdy_o => pci_irdy_o,
40a1f26c	330	pci_idsel_i => PCI_IDSEL,
221bd70b	331	pci_devsel_i => PCI_DEVSELn,
40a1f26c	332	pci_devsel_o => pci_devsel_o,
221bd70b	333	pci_trdy_i => PCI_TRDYn,
40a1f26c	334	pci_trdy_o => pci_trdy_o,
221bd70b	335	pci_stop_i => PCI_STOPn,
40a1f26c	336	pci_stop_o => pci_stop_o,
	337	pci_ad_i => PCI_AD,
	338	pci_ad_o => pci_ad_o,
221bd70b	339	pci_cbe_i => PCI_CBEn,
40a1f26c	340	pci_cbe_o => pci_cbe_o,
	341	pci_par_i => PCI_PAR,
	342	pci_par_o => pci_par_o,
	343	pci_par_oe_o => pci_par_oe_o,
221bd70b	344	pci_perr_i => PCI_PERRn,
40a1f26c	345	pci_perr_o => pci_perr_o,
	346	pci_perr_oe_o => pci_perr_oe_o,
	347	pci_serr_o => pci_serr_o,
	348	pci_serr_oe_o => pci_serr_oe_o
	349	);
	350
	351	Inst_eth_top: eth_top PORT MAP(
27f6f620	352	wb_clk_i => wb_clk_i ,
	353	wb_rst_i => wb_rst_i ,
	354	wb_dat_i => wb_dat_i ,
	355	wb_dat_o => wb_dat_o ,
	356	wb_adr_i => wb_adr_i ,
	357	wb_sel_i => wb_sel_i ,
	358	wb_we_i => wb_we_i ,
	359	wb_cyc_i => wb_cyc_i ,
3f7aa675	360	wb_stb_i => wb_stb_i,
27f6f620	361	wb_ack_o => wb_ack_o ,
	362	wb_err_o => wb_err_o ,
	363	m_wb_adr_o => m_wb_adr_o,
	364	m_wb_sel_o => m_wb_sel_o,
	365	m_wb_we_o => m_wb_we_o ,
	366	m_wb_dat_o => m_wb_dat_o,
	367	m_wb_dat_i => m_wb_dat_i,
	368	m_wb_cyc_o => m_wb_cyc_o,
	369	m_wb_stb_o => m_wb_stb_o,
	370	m_wb_ack_i => m_wb_ack_i,
	371	m_wb_err_i => m_wb_err_i,
	372	mtx_clk_pad_i => MTX_CLK_PAD_I,
	373	mtxd_pad_o => MTXD_PAD_O,
	374	mtxen_pad_o => MTXEN_PAD_O,
4d7b5fdd	375	mtxerr_pad_o => LED_2,
27f6f620	376	mrx_clk_pad_i => MRX_CLK_PAD_I,
	377	mrxd_pad_i => MRXD_PAD_I,
	378	mrxdv_pad_i => MRXDV_PAD_I,
	379	mrxerr_pad_i => MRXERR_PAD_I,
	380	mcoll_pad_i => MCOLL_PAD_I,
	381	mcrs_pad_i => MCRS_PAD_I,
	382	mdc_pad_o => MDC_PAD_O,
	383	md_pad_i => MD_PAD_IO,
	384	md_pad_o => md_pad_o,
	385	md_padoe_o => md_padoe_o,
361ec26f	386	m_wb_cti_o => m_wb_cti_o,
361ec26f	387	m_wb_bte_o => m_wb_bte_o,
27f6f620	388	int_o => int_o
40a1f26c	389	);
40a1f26c	390
c8b3e197	391	i_icon : icon
	392	port map (
	393	control0 => control0
	394	);
	395
	396	i_ila : ila
	397	port map (
	398	control => control0,
	399	clk => PCI_CLOCK,
	400	data => data,
	401	trig0 => trig0
	402	);
70f633de	403
ac5b8271	404	eth_dcm : phydcm
	405	port map (
	406	CLKIN_IN => PCI_CLOCK,
	407	RST_IN => not PCI_RSTn,
675f45d0	408	CLKFX_OUT => PHY_CLOCK,
	409	CLK0_OUT => open,
	410	LOCKED_OUT => open
ac5b8271	411	);
ac5b8271	412
27f6f620	413	end architecture ethernet_arch;