[raggedstone] / dhwk / source / pci / address_register.vhd

-- J.STELZNER
-- INFORMATIK-3 LABOR
-- 23.08.2006
-- File: ADDR_REG.VHD

library IEEE;
use IEEE.std_logic_1164.all;

entity ADDRESS_REGISTER is
	port (
                PCI_CLOCK	:in	std_logic;
                PCI_RSTn	:in	std_logic;
                LOAD_ADDR_REG	:in	std_logic;
                AD_REG		:in	std_logic_vector (31 downto 0);
                ADDR_REG	:out	std_logic_vector (31 downto 0)
        );
end entity ADDRESS_REGISTER;

architecture ADDR_REGI_DESIGN of ADDRESS_REGISTER is
	signal	REG_ADDR	:std_logic_vector (31 downto 0); 
begin 

	process (PCI_CLOCK, PCI_RSTn) 
	begin
		if	PCI_RSTn = '0'	then
                        REG_ADDR	<= X"00000000";

		elsif (rising_edge(PCI_CLOCK)) then
			if LOAD_ADDR_REG = '1' then
                                REG_ADDR	<=	AD_REG;
			else
                                REG_ADDR	<=	REG_ADDR;
			end if;
		end if;
	end process;

	ADDR_REG	<=	REG_ADDR;

end architecture ADDR_REGI_DESIGN;
Commit	Line	Data
696ded12	1	-- J.STELZNER
	2	-- INFORMATIK-3 LABOR
	3	-- 23.08.2006
	4	-- File: ADDR_REG.VHD
	5
	6	library IEEE;
	7	use IEEE.std_logic_1164.all;
	8
	9	entity ADDRESS_REGISTER is
	10	port (
	11	PCI_CLOCK :in std_logic;
	12	PCI_RSTn :in std_logic;
	13	LOAD_ADDR_REG :in std_logic;
	14	AD_REG :in std_logic_vector (31 downto 0);
	15	ADDR_REG :out std_logic_vector (31 downto 0)
	16	);
	17	end entity ADDRESS_REGISTER;
	18
	19	architecture ADDR_REGI_DESIGN of ADDRESS_REGISTER is
	20	signal REG_ADDR :std_logic_vector (31 downto 0);
	21	begin
	22
	23	process (PCI_CLOCK, PCI_RSTn)
	24	begin
	25	if PCI_RSTn = '0' then
	26	REG_ADDR <= X"00000000";
	27
e687cadb	28	elsif (rising_edge(PCI_CLOCK)) then
696ded12	29	if LOAD_ADDR_REG = '1' then
	30	REG_ADDR <= AD_REG;
	31	else
	32	REG_ADDR <= REG_ADDR;
	33	end if;
	34	end if;
	35	end process;
	36
	37	ADDR_REG <= REG_ADDR;
	38
	39	end architecture ADDR_REGI_DESIGN;