+= heartbeat
[raggedstone] / heartbeat / source / heartbeat.vhd
1 library ieee;
2
3 use ieee.std_logic_1164.all;
4 use ieee.std_logic_unsigned.all;
5
6 entity heartbeat is
7 generic (
8 divider : integer := 33000000
9 );
10
11 port (
12 clk_i : in std_logic;
13 nrst_i : in std_logic;
14 led_o : out std_logic
15 );
16
17 end heartbeat;
18
19 architecture rtl of heartbeat is
20 begin
21
22 process(clk_i, nrst_i)
23 variable counter : std_logic_vector(31 downto 0);
24 variable state : std_logic := '0';
25 begin
26
27 if (clk_i'event AND clk_i = '1') then
28 if nrst_i = '0' then
29 counter := (others => '0');
30 else
31 led_o <= state;
32 counter := counter + 1;
33 if counter = divider then
34 state := not state;
35 end if;
36 end if;
37 end if;
38 end process;
39 end architecture;
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