22ef572a11510086778b5040c9021301e7f13b96
[raggedstone] / ethernet / source / pci / pci_user_constants.v
1 //////////////////////////////////////////////////////////////////////
2 //// ////
3 //// File name "pci_user_constants.v" ////
4 //// ////
5 //// This file is part of the "PCI bridge" project ////
6 //// http://www.opencores.org/cores/pci/ ////
7 //// ////
8 //// Author(s): ////
9 //// - Miha Dolenc (mihad@opencores.org) ////
10 //// - Tadej Markovic (tadej@opencores.org) ////
11 //// ////
12 //////////////////////////////////////////////////////////////////////
13 //// ////
14 //// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
15 //// ////
16 //// This source file may be used and distributed without ////
17 //// restriction provided that this copyright statement is not ////
18 //// removed from the file and that any derivative work contains ////
19 //// the original copyright notice and the associated disclaimer. ////
20 //// ////
21 //// This source file is free software; you can redistribute it ////
22 //// and/or modify it under the terms of the GNU Lesser General ////
23 //// Public License as published by the Free Software Foundation; ////
24 //// either version 2.1 of the License, or (at your option) any ////
25 //// later version. ////
26 //// ////
27 //// This source is distributed in the hope that it will be ////
28 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
30 //// PURPOSE. See the GNU Lesser General Public License for more ////
31 //// details. ////
32 //// ////
33 //// You should have received a copy of the GNU Lesser General ////
34 //// Public License along with this source; if not, download it ////
35 //// from http://www.opencores.org/lgpl.shtml ////
36 //// ////
37 //////////////////////////////////////////////////////////////////////
38 //
39 // CVS Revision History
40 //
41 // $Log: pci_user_constants.v,v $
42 // Revision 1.1 2007-03-20 17:50:56 sithglan
43 // add shit
44 //
45 // Revision 1.15 2004/08/19 15:27:34 mihad
46 // Changed minimum pci image size to 256 bytes because
47 // of some PC system problems with size of IO images.
48 //
49 // Revision 1.14 2004/07/07 12:45:01 mihad
50 // Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines.
51 // Enabled value loading from serial EEPROM for all of the above + VendorID and DeviceID registers.
52 //
53 // Revision 1.13 2004/01/24 11:54:18 mihad
54 // Update! SPOCI Implemented!
55 //
56 // Revision 1.12 2003/12/28 09:54:48 fr2201
57 // def_wb_imagex_addr_map defined correctly
58 //
59 // Revision 1.11 2003/12/28 09:20:00 fr2201
60 // Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO)
61 //
62 // Revision 1.10 2003/12/19 11:11:30 mihad
63 // Compact PCI Hot Swap support added.
64 // New testcases added.
65 // Specification updated.
66 // Test application changed to support WB B3 cycles.
67 //
68 // Revision 1.9 2003/08/03 18:05:06 mihad
69 // Added limited WISHBONE B3 support for WISHBONE Slave Unit.
70 // Doesn't support full speed bursts yet.
71 //
72 // Revision 1.8 2003/03/14 15:31:57 mihad
73 // Entered the option to disable no response counter in wb master.
74 //
75 // Revision 1.7 2003/01/27 17:05:50 mihad
76 // Updated.
77 //
78 // Revision 1.6 2003/01/27 16:51:19 mihad
79 // Old files with wrong names removed.
80 //
81 // Revision 1.5 2003/01/21 16:06:56 mihad
82 // Bug fixes, testcases added.
83 //
84 // Revision 1.4 2002/09/30 17:22:45 mihad
85 // Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
86 //
87 // Revision 1.3 2002/08/13 11:03:53 mihad
88 // Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
89 //
90 // Revision 1.2 2002/03/05 11:53:47 mihad
91 // Added some testcases, removed un-needed fifo signals
92 //
93 // Revision 1.1 2002/02/01 14:43:31 mihad
94 // *** empty log message ***
95 //
96 //
97
98 // Fifo implementation defines:
99 // If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.
100 // 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),
101 // then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used
102 // If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations )
103 // If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with
104 // width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
105 // in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
106 // If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
107 // WB_FIFO_RAM_ADDR_LENGTH.
108
109 `define WBW_ADDR_LENGTH 4
110 `define WBR_ADDR_LENGTH 4
111 `define PCIW_ADDR_LENGTH 3
112 `define PCIR_ADDR_LENGTH 3
113
114 //`define FPGA
115 //`define XILINX
116
117 `define WB_RAM_DONT_SHARE
118 `define PCI_RAM_DONT_SHARE
119
120 `ifdef FPGA
121 `ifdef XILINX
122 `define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
123 `define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
124 `define PCI_XILINX_RAMB4
125 `define WB_XILINX_RAMB4
126 //`define PCI_XILINX_DIST_RAM
127 //`define WB_XILINX_DIST_RAM
128 `endif
129 `else
130 `define PCI_FIFO_RAM_ADDR_LENGTH 3 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
131 `define WB_FIFO_RAM_ADDR_LENGTH 4 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
132 // `define WB_ARTISAN_SDP
133 // `define PCI_ARTISAN_SDP
134 // `define PCI_VS_STP
135 // `define WB_VS_STP
136 `endif
137
138 // these two defines allow user to select active high or low output enables on PCI bus signals, depending on
139 // output buffers instantiated. Xilinx FPGAs use active low output enables.
140 `define ACTIVE_LOW_OE
141 //`define ACTIVE_HIGH_OE
142
143 // HOST/GUEST implementation selection - see design document and specification for description of each implementation
144 // only one can be defined at same time
145 //`define HOST
146 `define GUEST
147
148 // if NO_CNF_IMAGE is commented out, then READ-ONLY access to configuration space is ENABLED:
149 // - ENABLED Read-Only access from WISHBONE for GUEST bridges
150 // - ENABLED Read-Only access from PCI for HOST bridges
151 // with defining NO_CNF_IMAGE, one decoder and one multiplexer are saved
152 `define NO_CNF_IMAGE
153
154 // number defined here specifies how many MS bits in PCI address are compared with base address, to decode
155 // accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
156 // allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
157 // you have to define a number of minimum sized image and enlarge others by specifying different address mask.
158 // smaller the number here, faster the decoder operation
159 `define PCI_NUM_OF_DEC_ADDR_LINES 24
160
161 // no. of PCI Target IMAGES
162 // - PCI provides 6 base address registers for image implementation.
163 // PCI_IMAGE1 definition is not required and has no effect, since PCI image 1 is always implemented
164 // If GUEST is defined, PCI Image 0 is also always implemented and is used for configuration space
165 // access.
166 // If HOST is defined and NO_CNF_IMAGE is not, then PCI Image 0 is used for Read Only access to configuration
167 // space. If HOST is defined and NO_CNF_IMAGE is defined, then user can define PCI_IMAGE0 as normal image, and there
168 // is no access to Configuration space possible from PCI bus.
169 // Implementation of all other PCI images is selected by defining PCI_IMAGE2 through PCI_IMAGE5 regardles of HOST
170 // or GUEST implementation.
171 `ifdef HOST
172 `ifdef NO_CNF_IMAGE
173 //`define PCI_IMAGE0
174 `endif
175 `endif
176
177 //`define PCI_IMAGE2
178 //`define PCI_IMAGE3
179 //`define PCI_IMAGE4
180 //`define PCI_IMAGE5
181
182 // initial value for PCI image address masks. Address masks can be defined in enabled state,
183 // to allow device independent software to detect size of image and map base addresses to
184 // memory space. If initial mask for an image is defined as 0, then device independent software
185 // won't detect base address implemented and device dependent software will have to configure
186 // address masks as well as base addresses!
187 // Don't define PCI_AMx to 24'hffff_ff for memory images! Use that just for I/O images.
188 `define PCI_AM0 24'hffff_f0
189 `define PCI_AM1 24'hffff_ff
190 `define PCI_AM2 24'hffff_f0
191 `define PCI_AM3 24'hffff_f0
192 `define PCI_AM4 24'hffff_f0
193 `define PCI_AM5 24'hffff_f0
194
195 // initial value for PCI image maping to MEMORY or IO spaces. If initial define is set to 0,
196 // then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D
197 // Device independent software sets the base addresses acording to MEMORY or IO maping!
198 `define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
199 `define PCI_BA1_MEM_IO 1'b1
200 `define PCI_BA2_MEM_IO 1'b0
201 `define PCI_BA3_MEM_IO 1'b0
202 `define PCI_BA4_MEM_IO 1'b0
203 `define PCI_BA5_MEM_IO 1'b0
204
205 // initial value for PCI translation addresses. The initial values
206 // are set after reset. When ADDR_TRAN_IMPL is defined then then Images
207 // are transleted to this adresses whithout access to pci_ta registers.
208 `define PCI_TA0 24'h0000_0
209 `define PCI_TA1 24'h0000_0
210 `define PCI_TA2 24'h0000_0
211 `define PCI_TA3 24'h0000_0
212 `define PCI_TA4 24'h0000_0
213 `define PCI_TA5 24'h0000_0
214
215 `define PCI_AT_EN0 1'b0
216 `define PCI_AT_EN1 1'b0
217 `define PCI_AT_EN2 1'b0
218 `define PCI_AT_EN3 1'b0
219 `define PCI_AT_EN4 1'b0
220 `define PCI_AT_EN5 1'b0
221
222 // number defined here specifies how many MS bits in WB address are compared with base address, to decode
223 // accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
224 // allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
225 // you have to define a number of minimum sized image and enlarge others by specifying different address mask.
226 // smaller the number here, faster the decoder operation
227 `define WB_NUM_OF_DEC_ADDR_LINES 1
228
229 // no. of WISHBONE Slave IMAGES
230 // WB image 0 is always used for access to configuration space. In case configuration space access is not implemented,
231 // ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
232 // WB Image 1 is always implemented and user doesnt need to specify its definition
233 // WB images' 2 through 5 implementation by defining each one.
234 `define WB_IMAGE2
235 //`define WB_IMAGE3
236 //`define WB_IMAGE4
237 //`define WB_IMAGE5
238
239 //Address bar register defines the base address for each image.
240 //To asccess bus without Software configuration.
241 `define WB_BA1 20'h0000_0
242 `define WB_BA2 20'h8000_0
243 `define WB_BA3 20'h0000_0
244 `define WB_BA4 20'h0000_0
245 `define WB_BA5 20'h0000_0
246
247 // initial value for WB image maping to MEMORY or IO spaces. If initial define is set to 0,
248 // then IMAGE with that base address points to MEMORY space, othervise it points ti IO space.
249 `define WB_BA1_MEM_IO 1'b0
250 `define WB_BA2_MEM_IO 1'b0
251 `define WB_BA3_MEM_IO 1'b0
252 `define WB_BA4_MEM_IO 1'b0
253 `define WB_BA5_MEM_IO 1'b0
254
255 // initial value for WB image address masks.
256 `define WB_AM1 20'h8000_0
257 `define WB_AM2 20'h8000_0
258 `define WB_AM3 20'h0000_0
259 `define WB_AM4 20'h0000_0
260 `define WB_AM5 20'h0000_0
261
262 // initial value for WB translation addresses. The initial values
263 // are set after reset. When ADDR_TRAN_IMPL is defined then then Images
264 // are transleted to this adresses whithout access to pci_ta registers.
265 `define WB_TA1 20'h0000_0
266 `define WB_TA2 20'h0000_0
267 `define WB_TA3 20'h0000_0
268 `define WB_TA4 20'h0000_0
269 `define WB_TA5 20'h0000_0
270
271 `define WB_AT_EN1 1'b0
272 `define WB_AT_EN2 1'b0
273 `define WB_AT_EN3 1'b0
274 `define WB_AT_EN4 1'b0
275 `define WB_AT_EN5 1'b0
276
277 // If this define is commented out, then address translation will not be implemented.
278 // addresses will pass through bridge unchanged, regardles of address translation enable bits.
279 // Address translation also slows down the decoding
280 //When ADDR_TRAN_IMPL this define is present then adress translation is enabled after reset.
281 //`define ADDR_TRAN_IMPL
282
283 // decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
284 // slower decode speed can be used, to provide enough time for address to be decoded.
285 `define WB_DECODE_FAST
286 //`define WB_DECODE_MEDIUM
287 //`define WB_DECODE_SLOW
288
289 // Base address for Configuration space access from WB bus. This value cannot be changed during runtime
290 `define WB_CONFIGURATION_BASE 20'h0000_0
291
292 // Turn registered WISHBONE slave outputs on or off
293 // all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
294 // outputs to internals of the core.
295 //`define REGISTER_WBS_OUTPUTS
296
297 /*-----------------------------------------------------------------------------------------------------------
298 Core speed definition - used for simulation and 66MHz Capable bit value in status register indicating 66MHz
299 capable device
300 -----------------------------------------------------------------------------------------------------------*/
301 `define PCI33
302 //`define PCI66
303
304 /*-----------------------------------------------------------------------------------------------------------
305 [000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
306 Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
307 Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
308 together by application.
309 -----------------------------------------------------------------------------------------------------------*/
310 `define HEADER_VENDOR_ID 16'h1895
311 `define HEADER_DEVICE_ID 16'h0001
312 `define HEADER_REVISION_ID 8'h01
313 `define HEADER_SUBSYS_VENDOR_ID 16'h1895
314 `define HEADER_SUBSYS_ID 16'h0001
315 `define HEADER_MAX_LAT 8'h1a
316 `define HEADER_MIN_GNT 8'h08
317
318 // MAX Retry counter value for WISHBONE Master state-machine
319 // This value is 8-bit because of 8-bit retry counter !!!
320 `define WB_RTY_CNT_MAX 8'hff
321
322 // define the macro below to disable internal retry generation in the wishbone master interface
323 // used when wb master accesses extremly slow devices.
324 `define PCI_WBM_NO_RESPONSE_CNT_DISABLE
325
326 `define PCI_WB_REV_B3
327 //`define PCI_WBS_B3_RTY_DISABLE
328
329 `ifdef GUEST
330 // `define PCI_CPCI_HS_IMPLEMENT
331 // `define PCI_SPOCI
332 `endif
333
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