all files to lowercase,
[raggedstone] / dhwk / source / pci / cont_fsm.vhd
1 -- J.STELZNER
2 -- INFORMATIK-3 LABOR
3 -- 23.08.2006
4 -- File: CONT_FSM.VHD
5
6 library ieee;
7 use ieee.std_logic_1164.all;
8
9 entity CONT_FSM is
10 port
11 (
12 PCI_CLOCK :in std_logic;
13 PCI_RSTn :in std_logic;
14 IO_READ :in std_logic;
15 IO_WRITE :in std_logic;
16 CONF_READ :in std_logic;
17 CONF_WRITE :in std_logic;
18 FIFO_READ :in std_logic;
19 READ :out std_logic;--> MUX_SEL(1) , OE_PCI_AD
20 PERR_CHECK :out std_logic;
21 DEVSELn :out std_logic;
22 OE_PCI_PAR :out std_logic;
23 OE_PCI_PERR :out std_logic;
24 TRDYn :out std_logic;
25 PCI_TRDYn :out std_logic; -- s/t/s
26 PCI_STOPn :out std_logic; -- s/t/s
27 PCI_DEVSELn :out std_logic; -- s/t/s
28 FIFO_RDn :out std_logic
29 );
30 end entity CONT_FSM;
31
32 architecture CONT_FSM_DESIGN of CONT_FSM is
33
34
35
36 --**********************************************************
37 --*** CONTROL FSM CODIERUNG ***
38 --**********************************************************
39 --
40 --
41 --
42 -- |----------- HELP
43 -- ||---------- FIFO_READn
44 -- |||--------- OE_PCI_PERR
45 -- ||||-------- PERR_CHECK
46 -- |||||------- TRDYn
47 -- ||||||------ STOPn
48 -- |||||||----- DEVSELn
49 -- ||||||||---- OE_PCI_PAR
50 -- |||||||||--- OE_CONTROL
51 -- ||||||||||-- READ / MUX_SEL(1) / OE_PCI_AD
52 -- ||||||||||
53 constant ST_IDLE :std_logic_vector (9 downto 0) := "0100111000";-- 138
54
55 constant ST_READ_1 :std_logic_vector (9 downto 0) := "0100110011";-- 133
56 constant ST_READ_2 :std_logic_vector (9 downto 0) := "0100000111";-- 107
57 constant ST_READ_3 :std_logic_vector (9 downto 0) := "0100111111";-- 13F
58
59 constant ST_RD_FIFO_1 :std_logic_vector (9 downto 0) := "0000110011";-- 033
60 constant ST_RD_FIFO_2 :std_logic_vector (9 downto 0) := "1100110011";-- 233
61
62
63 constant ST_WRITE_1 :std_logic_vector (9 downto 0) := "0111110010";-- 1F2
64 constant ST_WRITE_2 :std_logic_vector (9 downto 0) := "0110000010";-- 182
65 constant ST_WRITE_3 :std_logic_vector (9 downto 0) := "0110111010";-- 1BA
66
67 signal CONTROL_STATE :std_logic_vector (9 downto 0);
68
69
70 --signal DEVSELn :std_logic;
71 signal STOPn :std_logic;
72 --signal TRDYn :std_logic;
73
74 --************************************************************
75 --*** FSM SPEICHER-AUTOMAT ***
76 --************************************************************
77
78 attribute syn_state_machine : boolean;
79 attribute syn_state_machine of CONTROL_STATE : signal is false;
80
81 begin
82
83 --**********************************************************
84 --*** CONTROL FSM ***
85 --**********************************************************
86
87 process (PCI_CLOCK, PCI_RSTn)
88 begin
89 if PCI_RSTn = '0' then CONTROL_STATE <= ST_IDLE;
90
91 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
92
93 case CONTROL_STATE is
94 when ST_IDLE =>
95 if IO_READ = '1' then
96 CONTROL_STATE <= ST_READ_1;
97
98 elsif CONF_READ = '1' then
99 CONTROL_STATE <= ST_READ_1;
100
101 elsif IO_WRITE = '1' then
102 CONTROL_STATE <= ST_WRITE_1;
103
104 elsif CONF_WRITE = '1' then
105 CONTROL_STATE <= ST_WRITE_1;
106
107 else CONTROL_STATE <= ST_IDLE;
108 end if;
109
110 -- when ST_READ_1 =>
111 -- CONTROL_STATE <= ST_READ_2;
112
113 when ST_READ_1 =>
114 if FIFO_READ = '1' then
115 CONTROL_STATE <= ST_RD_FIFO_1;
116 else
117 CONTROL_STATE <= ST_READ_2;
118 end if;
119
120 when ST_READ_2 =>
121 CONTROL_STATE <= ST_READ_3;
122
123 when ST_READ_3 =>
124 CONTROL_STATE <= ST_IDLE;
125
126 when ST_RD_FIFO_1=>
127 CONTROL_STATE <= ST_RD_FIFO_2;
128
129 when ST_RD_FIFO_2=>
130 CONTROL_STATE <= ST_READ_2;
131
132 when ST_WRITE_1 =>
133 CONTROL_STATE <= ST_WRITE_2;
134
135 when ST_WRITE_2 =>
136 CONTROL_STATE <= ST_WRITE_3;
137
138 when ST_WRITE_3 =>
139 CONTROL_STATE <= ST_IDLE;
140
141 when others =>
142 CONTROL_STATE <= ST_IDLE;
143
144 end case; -- COMM_STATE
145 end if; -- CLOCK
146 end process; -- PROCESS
147
148
149 READ <= CONTROL_STATE(0);
150 --OE_CONTROL <= CONTROL_STATE(1);
151 OE_PCI_PAR <= CONTROL_STATE(2);
152 DEVSELn <= CONTROL_STATE(3);
153 STOPn <= CONTROL_STATE(4);
154 TRDYn <= CONTROL_STATE(5);
155 PERR_CHECK <= CONTROL_STATE(6);
156 OE_PCI_PERR <= CONTROL_STATE(7);
157
158 FIFO_RDn <= CONTROL_STATE(8);
159
160
161 PCI_DEVSELn <= CONTROL_STATE(3) when CONTROL_STATE(1) = '1' else 'Z';
162 PCI_STOPn <= STOPn when CONTROL_STATE(1) = '1' else 'Z';
163 PCI_TRDYn <= CONTROL_STATE(5) when CONTROL_STATE(1) = '1' else 'Z';
164
165 end architecture CONT_FSM_DESIGN;
Impressum, Datenschutz