first import of dhwk.
[raggedstone] / dhwk / source / user_io.vhd
1 -- VHDL model created from schematic user_io.sch -- Jan 09 09:34:12 2007
2
3
4
5 LIBRARY ieee;
6
7 USE ieee.std_logic_1164.ALL;
8 USE ieee.numeric_std.ALL;
9
10
11 entity USER_IO is
12 Port ( AD_REG : In std_logic_vector (31 downto 0);
13 ADDR_REG : In std_logic_vector (31 downto 0);
14 CBE_REGn : In std_logic_vector (3 downto 0);
15 FLAG : In std_logic_vector (7 downto 0);
16 INT_REG : In std_logic_vector (7 downto 0);
17 IO_WR_COM : In std_logic;
18 IRDY_REGn : In std_logic;
19 PCI_CLK : In std_logic;
20 R_FIFO_Q : In std_logic_vector (7 downto 0);
21 READ_SEL : In std_logic_vector (1 downto 0);
22 TRDYn : In std_logic;
23 READ_XX1_0 : Out std_logic;
24 READ_XX3_2 : Out std_logic;
25 READ_XX5_4 : Out std_logic;
26 READ_XX7_6 : Out std_logic;
27 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
28 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
29 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
30 USER_DATA_OUT : Out std_logic_vector (31 downto 0);
31 WRITE_XX1_0 : Out std_logic;
32 WRITE_XX3_2 : Out std_logic;
33 WRITE_XX5_4 : Out std_logic;
34 WRITE_XX7_6 : Out std_logic );
35 end USER_IO;
36
37 architecture SCHEMATIC of USER_IO is
38
39 SIGNAL gnd : std_logic := '0';
40 SIGNAL vcc : std_logic := '1';
41
42 signal WRITE_XX1_0_DUMMY : std_logic;
43 signal WRITE_XX7_6_DUMMY : std_logic;
44 signal REG_OUT_XX7_DUMMY : std_logic_vector (7 downto 0);
45 signal REG_OUT_XX6_DUMMY : std_logic_vector (7 downto 0);
46 signal REG_OUT_XX0_DUMMY : std_logic_vector (7 downto 0);
47
48 component IO_WR_SEL
49 Port ( ADDR_REG : In std_logic_vector (31 downto 0);
50 CBE_REGn : In std_logic_vector (3 downto 0);
51 IO_WR_COM : In std_logic;
52 IRDY_REGn : In std_logic;
53 TRDYn : In std_logic;
54 WRITE_XX1_0 : Out std_logic;
55 WRITE_XX3_2 : Out std_logic;
56 WRITE_XX5_4 : Out std_logic;
57 WRITE_XX7_6 : Out std_logic );
58 end component;
59
60 component DATA_MUX
61 Port ( ADDR_REG : In std_logic_vector (31 downto 0);
62 CBE_REGn : In std_logic_vector (3 downto 0);
63 MUX_IN_XX0 : In std_logic_vector (7 downto 0);
64 MUX_IN_XX1 : In std_logic_vector (7 downto 0);
65 MUX_IN_XX2 : In std_logic_vector (7 downto 0);
66 MUX_IN_XX3 : In std_logic_vector (7 downto 0);
67 MUX_IN_XX4 : In std_logic_vector (7 downto 0);
68 MUX_IN_XX5 : In std_logic_vector (7 downto 0);
69 MUX_IN_XX6 : In std_logic_vector (7 downto 0);
70 MUX_IN_XX7 : In std_logic_vector (7 downto 0);
71 READ_SEL : In std_logic_vector (1 downto 0);
72 MUX_OUT : Out std_logic_vector (31 downto 0);
73 READ_XX1_0 : Out std_logic;
74 READ_XX3_2 : Out std_logic;
75 READ_XX5_4 : Out std_logic;
76 READ_XX7_6 : Out std_logic );
77 end component;
78
79 component REG_IO
80 Port ( AD_REG : In std_logic_vector (31 downto 0);
81 PCI_CLOCK : In std_logic;
82 RESET : In std_logic;
83 WRITE_XX1_0 : In std_logic;
84 WRITE_XX7_6 : In std_logic;
85 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
86 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
87 REG_OUT_XX7 : Out std_logic_vector (7 downto 0) );
88 end component;
89
90 begin
91
92 REG_OUT_XX0 <= REG_OUT_XX0_DUMMY;
93 REG_OUT_XX6 <= REG_OUT_XX6_DUMMY;
94 REG_OUT_XX7 <= REG_OUT_XX7_DUMMY;
95 WRITE_XX7_6 <= WRITE_XX7_6_DUMMY;
96 WRITE_XX1_0 <= WRITE_XX1_0_DUMMY;
97
98 I4 : IO_WR_SEL
99 Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
100 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
101 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
102 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
103 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
104 WRITE_XX7_6=>WRITE_XX7_6_DUMMY );
105 I2 : DATA_MUX
106 Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
107 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
108 MUX_IN_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
109 MUX_IN_XX1(7 downto 0)=>FLAG(7 downto 0),
110 MUX_IN_XX2(7 downto 0)=>R_FIFO_Q(7 downto 0),
111 MUX_IN_XX3(7 downto 0)=>FLAG(7 downto 0),
112 MUX_IN_XX4(7 downto 0)=>INT_REG(7 downto 0),
113 MUX_IN_XX5(7 downto 0)=>FLAG(7 downto 0),
114 MUX_IN_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
115 MUX_IN_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0),
116 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
117 MUX_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
118 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
119 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6 );
120 I1 : REG_IO
121 Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
122 PCI_CLOCK=>PCI_CLK, RESET=>REG_OUT_XX7_DUMMY(0),
123 WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
124 WRITE_XX7_6=>WRITE_XX7_6_DUMMY,
125 REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
126 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
127 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0) );
128
129 end SCHEMATIC;
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