name ports
[raggedstone] / dhwk / source / Addr_regi.vhd
1 -- J.STELZNER
2 -- INFORMATIK-3 LABOR
3 -- 23.08.2006
4 -- File: ADDR_REG.VHD
5
6 library IEEE;
7 use IEEE.std_logic_1164.all;
8
9 entity ADDR_REGI is
10 port
11 (
12 PCI_CLOCK :in std_logic;
13 PCI_RSTn :in std_logic;
14 LOAD_ADDR_REG :in std_logic;
15 AD_REG :in std_logic_vector (31 downto 0);
16 ADDR_REG :out std_logic_vector (31 downto 0)
17 );
18 end entity ADDR_REGI;
19
20 architecture ADDR_REGI_DESIGN of ADDR_REGI is
21
22 signal REG_ADDR :std_logic_vector (31 downto 0);
23
24 begin
25
26 process (PCI_CLOCK, PCI_RSTn)
27 begin
28 if PCI_RSTn = '0' then REG_ADDR <= X"00000000";
29
30 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
31
32 if LOAD_ADDR_REG = '1' then
33 REG_ADDR <= AD_REG;
34
35 else REG_ADDR <= REG_ADDR;
36 end if;
37
38 end if;
39 end process;
40
41 ADDR_REG <= REG_ADDR;
42
43 end architecture ADDR_REGI_DESIGN;
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