git.zerfleddert.de Git - raggedstone/blob - ethernet/source/pci/pci_par_crit.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  File name "par_crit.v"                                      ////
   4 ////                                                              ////
   5 ////  This file is part of the "PCI bridge" project               ////
   6 ////  http://www.opencores.org/cores/pci/                         ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Miha Dolenc (mihad@opencores.org)                     ////
  10 ////                                                              ////
  11 ////  All additional information is avaliable in the README       ////
  12 ////  file.                                                       ////
  13 ////                                                              ////
  14 ////                                                              ////
  15 //////////////////////////////////////////////////////////////////////
  16 ////                                                              ////
  17 //// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
  18 ////                                                              ////
  19 //// This source file may be used and distributed without         ////
  20 //// restriction provided that this copyright statement is not    ////
  21 //// removed from the file and that any derivative work contains  ////
  22 //// the original copyright notice and the associated disclaimer. ////
  23 ////                                                              ////
  24 //// This source file is free software; you can redistribute it   ////
  25 //// and/or modify it under the terms of the GNU Lesser General   ////
  26 //// Public License as published by the Free Software Foundation; ////
  27 //// either version 2.1 of the License, or (at your option) any   ////
  28 //// later version.                                               ////
  29 ////                                                              ////
  30 //// This source is distributed in the hope that it will be       ////
  31 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  32 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  33 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  34 //// details.                                                     ////
  35 ////                                                              ////
  36 //// You should have received a copy of the GNU Lesser General    ////
  37 //// Public License along with this source; if not, download it   ////
  38 //// from http://www.opencores.org/lgpl.shtml                     ////
  39 ////                                                              ////
  40 //////////////////////////////////////////////////////////////////////
  41 //
  42 // CVS Revision History
  43 //
  44 // $Log: pci_par_crit.v,v $
  45 // Revision 1.1  2007-03-20 17:50:56  sithglan
  46 // add shit
  47 //
  48 // Revision 1.2  2003/02/13 18:26:33  mihad
  49 // Cleaned up the code. No functional changes.
  50 //
  51 // Revision 1.1  2003/01/27 16:49:31  mihad
  52 // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
  53 //
  54 // Revision 1.3  2002/02/01 15:25:12  mihad
  55 // Repaired a few bugs, updated specification, added test bench files and design document
  56 //
  57 // Revision 1.2  2001/10/05 08:14:28  mihad
  58 // Updated all files with inclusion of timescale file for simulation purposes.
  59 //
  60 // Revision 1.1.1.1  2001/10/02 15:33:46  mihad
  61 // New project directory structure
  62 //
  63 //
  64
  65 // module is used to separate logic which uses criticaly constrained inputs from slower logic.
  66 // It is used to synthesize critical timing logic separately with faster cells or without optimization
  67
  68 // this one is used in parity generator/checker for calculating parity signal
  69
  70 // synopsys translate_off
  71 `include "timescale.v"
  72 // synopsys translate_on
  73
  74 module pci_par_crit
  75 (
  76     par_out,
  77     par_out_in,
  78     pci_cbe_en_in,
  79     data_par_in,
  80     pci_cbe_in
  81 ) ;
  82
  83 output par_out ;
  84
  85 input   par_out_in,
  86         pci_cbe_en_in,
  87         data_par_in ;
  88
  89 input   [3:0] pci_cbe_in ;
  90
  91 assign par_out = pci_cbe_en_in ? par_out_in : ( pci_cbe_in[3] ^ pci_cbe_in[2] ^ pci_cbe_in[1] ^ pci_cbe_in[0] ^ data_par_in) ;
  92
  93 endmodule