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[raggedstone] / ethernet / source / pci / pci_wb_slave_unit.v
1 //////////////////////////////////////////////////////////////////////
2 //// ////
3 //// File name "wb_slave_unit.v" ////
4 //// ////
5 //// This file is part of the "PCI bridge" project ////
6 //// http://www.opencores.org/cores/pci/ ////
7 //// ////
8 //// Author(s): ////
9 //// - Miha Dolenc (mihad@opencores.org) ////
10 //// ////
11 //// All additional information is avaliable in the README ////
12 //// file. ////
13 //// ////
14 //// ////
15 //////////////////////////////////////////////////////////////////////
16 //// ////
17 //// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
18 //// ////
19 //// This source file may be used and distributed without ////
20 //// restriction provided that this copyright statement is not ////
21 //// removed from the file and that any derivative work contains ////
22 //// the original copyright notice and the associated disclaimer. ////
23 //// ////
24 //// This source file is free software; you can redistribute it ////
25 //// and/or modify it under the terms of the GNU Lesser General ////
26 //// Public License as published by the Free Software Foundation; ////
27 //// either version 2.1 of the License, or (at your option) any ////
28 //// later version. ////
29 //// ////
30 //// This source is distributed in the hope that it will be ////
31 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
32 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
33 //// PURPOSE. See the GNU Lesser General Public License for more ////
34 //// details. ////
35 //// ////
36 //// You should have received a copy of the GNU Lesser General ////
37 //// Public License along with this source; if not, download it ////
38 //// from http://www.opencores.org/lgpl.shtml ////
39 //// ////
40 //////////////////////////////////////////////////////////////////////
41 //
42 // CVS Revision History
43 //
44 // $Log: pci_wb_slave_unit.v,v $
45 // Revision 1.1 2007-03-20 17:50:56 sithglan
46 // add shit
47 //
48 // Revision 1.4 2006/07/04 13:16:19 mihad
49 // Write burst performance patch applied.
50 // Not tested. Everything should be backwards
51 // compatible, since functional code is ifdefed.
52 //
53 // Revision 1.3 2004/01/24 11:54:18 mihad
54 // Update! SPOCI Implemented!
55 //
56 // Revision 1.2 2003/10/17 09:11:52 markom
57 // mbist signals updated according to newest convention
58 //
59 // Revision 1.1 2003/01/27 16:49:31 mihad
60 // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
61 //
62 // Revision 1.8 2002/10/18 03:36:37 tadejm
63 // Changed wrong signal name mbist_sen into mbist_ctrl_i.
64 //
65 // Revision 1.7 2002/10/17 22:49:22 tadejm
66 // Changed BIST signals for RAMs.
67 //
68 // Revision 1.6 2002/10/11 10:09:01 mihad
69 // Added additional testcase and changed rst name in BIST to trst
70 //
71 // Revision 1.5 2002/10/08 17:17:06 mihad
72 // Added BIST signals for RAMs.
73 //
74 // Revision 1.4 2002/09/25 15:53:52 mihad
75 // Removed all logic from asynchronous reset network
76 //
77 // Revision 1.3 2002/02/01 15:25:13 mihad
78 // Repaired a few bugs, updated specification, added test bench files and design document
79 //
80 // Revision 1.2 2001/10/05 08:14:30 mihad
81 // Updated all files with inclusion of timescale file for simulation purposes.
82 //
83 // Revision 1.1.1.1 2001/10/02 15:33:46 mihad
84 // New project directory structure
85 //
86 //
87
88 // Module instantiates and connects other modules lower in hierarcy
89 // Wishbone slave unit consists of modules that together form datapath
90 // between external WISHBONE masters and external PCI targets
91 `include "pci_constants.v"
92
93 // synopsys translate_off
94 `include "timescale.v"
95 // synopsys translate_on
96
97 module pci_wb_slave_unit
98 (
99 reset_in,
100 wb_clock_in,
101 pci_clock_in,
102 ADDR_I,
103 SDATA_I,
104 SDATA_O,
105 CYC_I,
106 STB_I,
107 WE_I,
108 SEL_I,
109 ACK_O,
110 RTY_O,
111 ERR_O,
112 CAB_I,
113 wbu_map_in,
114 wbu_pref_en_in,
115 wbu_mrl_en_in,
116 wbu_pci_drcomp_pending_in,
117 wbu_conf_data_in,
118 wbu_pciw_empty_in,
119 wbu_bar0_in,
120 wbu_bar1_in,
121 wbu_bar2_in,
122 wbu_bar3_in,
123 wbu_bar4_in,
124 wbu_bar5_in,
125 wbu_am0_in,
126 wbu_am1_in,
127 wbu_am2_in,
128 wbu_am3_in,
129 wbu_am4_in,
130 wbu_am5_in,
131 wbu_ta0_in,
132 wbu_ta1_in,
133 wbu_ta2_in,
134 wbu_ta3_in,
135 wbu_ta4_in,
136 wbu_ta5_in,
137 wbu_at_en_in,
138 wbu_ccyc_addr_in ,
139 wbu_master_enable_in,
140 wb_init_complete_in,
141 wbu_cache_line_size_not_zero,
142 wbu_cache_line_size_in,
143 wbu_pciif_gnt_in,
144 wbu_pciif_frame_in,
145 wbu_pciif_irdy_in,
146 wbu_pciif_trdy_in,
147 wbu_pciif_trdy_reg_in,
148 wbu_pciif_stop_in,
149 wbu_pciif_stop_reg_in,
150 wbu_pciif_devsel_in,
151 wbu_pciif_devsel_reg_in,
152 wbu_pciif_ad_reg_in,
153 wbu_pciif_req_out,
154 wbu_pciif_frame_out,
155 wbu_pciif_frame_en_out,
156 wbu_pciif_frame_en_in,
157 wbu_pciif_frame_out_in,
158 wbu_pciif_frame_load_out,
159 wbu_pciif_irdy_out,
160 wbu_pciif_irdy_en_out,
161 wbu_pciif_ad_out,
162 wbu_pciif_ad_en_out,
163 wbu_pciif_cbe_out,
164 wbu_pciif_cbe_en_out,
165 wbu_err_addr_out,
166 wbu_err_bc_out,
167 wbu_err_signal_out,
168 wbu_err_source_out,
169 wbu_err_rty_exp_out,
170 wbu_tabort_rec_out,
171 wbu_mabort_rec_out,
172 wbu_conf_offset_out,
173 wbu_conf_renable_out,
174 wbu_conf_wenable_out,
175 wbu_conf_be_out,
176 wbu_conf_data_out,
177 wbu_del_read_comp_pending_out,
178 wbu_wbw_fifo_empty_out,
179 wbu_latency_tim_val_in,
180 wbu_ad_load_out,
181 wbu_ad_load_on_transfer_out
182
183 `ifdef PCI_BIST
184 ,
185 // debug chain signals
186 mbist_si_i, // bist scan serial in
187 mbist_so_o, // bist scan serial out
188 mbist_ctrl_i // bist chain shift control
189 `endif
190 );
191
192 input reset_in,
193 wb_clock_in,
194 pci_clock_in ;
195
196 input [31:0] ADDR_I ;
197 input [31:0] SDATA_I ;
198 output [31:0] SDATA_O ;
199 input CYC_I ;
200 input STB_I ;
201 input WE_I ;
202 input [3:0] SEL_I ;
203 output ACK_O ;
204 output RTY_O ;
205 output ERR_O ;
206 input CAB_I ;
207
208 input [5:0] wbu_map_in ;
209 input [5:0] wbu_pref_en_in ;
210 input [5:0] wbu_mrl_en_in ;
211
212 input wbu_pci_drcomp_pending_in ;
213
214 input [31:0] wbu_conf_data_in ;
215
216 input wbu_pciw_empty_in ;
217
218 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar0_in ;
219 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar1_in ;
220 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar2_in ;
221 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar3_in ;
222 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar4_in ;
223 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar5_in ;
224 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am0_in ;
225 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am1_in ;
226 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am2_in ;
227 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am3_in ;
228 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am4_in ;
229 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am5_in ;
230 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta0_in ;
231 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta1_in ;
232 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta2_in ;
233 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta3_in ;
234 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta4_in ;
235 input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta5_in ;
236 input [5:0] wbu_at_en_in ;
237
238 input [23:0] wbu_ccyc_addr_in ;
239
240 input wbu_master_enable_in ;
241 input wb_init_complete_in ;
242
243 input wbu_cache_line_size_not_zero ;
244 input [7:0] wbu_cache_line_size_in ;
245
246 input wbu_pciif_gnt_in ;
247 input wbu_pciif_frame_in ;
248 input wbu_pciif_frame_en_in ;
249 input wbu_pciif_irdy_in ;
250 input wbu_pciif_trdy_in;
251 input wbu_pciif_trdy_reg_in;
252 input wbu_pciif_stop_in ;
253 input wbu_pciif_stop_reg_in ;
254 input wbu_pciif_devsel_in ;
255 input wbu_pciif_devsel_reg_in ;
256 input [31:0] wbu_pciif_ad_reg_in ;
257
258 output wbu_pciif_req_out ;
259 output wbu_pciif_frame_out ;
260 output wbu_pciif_frame_en_out ;
261 input wbu_pciif_frame_out_in ;
262 output wbu_pciif_frame_load_out ;
263 output wbu_pciif_irdy_out ;
264 output wbu_pciif_irdy_en_out ;
265 output [31:0] wbu_pciif_ad_out ;
266 output wbu_pciif_ad_en_out ;
267 output [3:0] wbu_pciif_cbe_out ;
268 output wbu_pciif_cbe_en_out ;
269
270 output [31:0] wbu_err_addr_out ;
271 output [3:0] wbu_err_bc_out ;
272 output wbu_err_signal_out ;
273 output wbu_err_source_out ;
274 output wbu_err_rty_exp_out ;
275 output wbu_tabort_rec_out ;
276 output wbu_mabort_rec_out ;
277
278 output [11:0] wbu_conf_offset_out ;
279 output wbu_conf_renable_out ;
280 output wbu_conf_wenable_out ;
281 output [3:0] wbu_conf_be_out ;
282 output [31:0] wbu_conf_data_out ;
283
284 output wbu_del_read_comp_pending_out ;
285 output wbu_wbw_fifo_empty_out ;
286
287 input [7:0] wbu_latency_tim_val_in ;
288
289 output wbu_ad_load_out ;
290 output wbu_ad_load_on_transfer_out ;
291
292 `ifdef PCI_BIST
293 /*-----------------------------------------------------
294 BIST debug chain port signals
295 -----------------------------------------------------*/
296 input mbist_si_i; // bist scan serial in
297 output mbist_so_o; // bist scan serial out
298 input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
299 `endif
300
301 // pci master interface outputs
302 wire [31:0] pcim_if_address_out ;
303 wire [3:0] pcim_if_bc_out ;
304 wire [31:0] pcim_if_data_out ;
305 wire [3:0] pcim_if_be_out ;
306 wire pcim_if_req_out ;
307 wire pcim_if_rdy_out ;
308 wire pcim_if_last_out ;
309 wire pcim_if_wbw_renable_out ;
310 wire pcim_if_wbr_wenable_out ;
311 wire [31:0] pcim_if_wbr_data_out ;
312 wire [3:0] pcim_if_wbr_be_out ;
313 wire [3:0] pcim_if_wbr_control_out ;
314 wire pcim_if_del_complete_out ;
315 wire pcim_if_del_error_out ;
316 wire pcim_if_del_rty_exp_out ;
317 wire [31:0] pcim_if_err_addr_out ;
318 wire [3:0] pcim_if_err_bc_out ;
319 wire pcim_if_err_signal_out ;
320 wire pcim_if_err_source_out ;
321 wire pcim_if_err_rty_exp_out ;
322 wire pcim_if_tabort_out ;
323 wire pcim_if_mabort_out ;
324 wire [31:0] pcim_if_next_data_out ;
325 wire [3:0] pcim_if_next_be_out ;
326 wire pcim_if_next_last_out ;
327 wire pcim_if_posted_write_not_present_out ;
328
329
330
331 wire pcim_sm_req_out ;
332 wire pcim_sm_frame_out ;
333 wire pcim_sm_frame_en_out ;
334 wire pcim_sm_irdy_out ;
335 wire pcim_sm_irdy_en_out ;
336 wire [31:0] pcim_sm_ad_out ;
337 wire pcim_sm_ad_en_out ;
338 wire [3:0] pcim_sm_cbe_out ;
339 wire pcim_sm_cbe_en_out ;
340 wire pcim_sm_ad_load_out ;
341 wire pcim_sm_ad_load_on_transfer_out ;
342
343 wire pcim_sm_wait_out ;
344 wire pcim_sm_wtransfer_out ;
345 wire pcim_sm_rtransfer_out ;
346 wire pcim_sm_retry_out ;
347 wire pcim_sm_rerror_out ;
348 wire pcim_sm_first_out ;
349 wire pcim_sm_mabort_out ;
350 wire pcim_sm_frame_load_out ;
351
352 assign wbu_pciif_frame_load_out = pcim_sm_frame_load_out ;
353
354 assign wbu_err_addr_out = pcim_if_err_addr_out ;
355 assign wbu_err_bc_out = pcim_if_err_bc_out ;
356 assign wbu_err_signal_out = pcim_if_err_signal_out ;
357 assign wbu_err_source_out = pcim_if_err_source_out ;
358 assign wbu_err_rty_exp_out = pcim_if_err_rty_exp_out ;
359 assign wbu_tabort_rec_out = pcim_if_tabort_out ;
360 assign wbu_mabort_rec_out = pcim_if_mabort_out ;
361
362 assign wbu_wbw_fifo_empty_out = pcim_if_posted_write_not_present_out ;
363
364 // pci master state machine outputs
365 // pci interface signals
366 assign wbu_pciif_req_out = pcim_sm_req_out ;
367 assign wbu_pciif_frame_out = pcim_sm_frame_out ;
368 assign wbu_pciif_frame_en_out = pcim_sm_frame_en_out ;
369 assign wbu_pciif_irdy_out = pcim_sm_irdy_out ;
370 assign wbu_pciif_irdy_en_out = pcim_sm_irdy_en_out ;
371 assign wbu_pciif_ad_out = pcim_sm_ad_out ;
372 assign wbu_pciif_ad_en_out = pcim_sm_ad_en_out ;
373 assign wbu_pciif_cbe_out = pcim_sm_cbe_out ;
374 assign wbu_pciif_cbe_en_out = pcim_sm_cbe_en_out ;
375 assign wbu_ad_load_out = pcim_sm_ad_load_out ;
376 assign wbu_ad_load_on_transfer_out = pcim_sm_ad_load_on_transfer_out ;
377
378 // signals to internal of the core
379 wire [31:0] pcim_sm_data_out ;
380
381 // wishbone slave state machine outputs
382 wire [3:0] wbs_sm_del_bc_out ;
383 wire wbs_sm_del_req_out ;
384 wire wbs_sm_del_done_out ;
385 wire wbs_sm_del_burst_out ;
386 wire wbs_sm_del_write_out ;
387 wire [11:0] wbs_sm_conf_offset_out ;
388 wire wbs_sm_conf_renable_out ;
389 wire wbs_sm_conf_wenable_out ;
390 wire [3:0] wbs_sm_conf_be_out ;
391 wire [31:0] wbs_sm_conf_data_out ;
392 wire [31:0] wbs_sm_data_out ;
393 wire [3:0] wbs_sm_cbe_out ;
394 wire wbs_sm_wbw_wenable_out ;
395 wire [3:0] wbs_sm_wbw_control_out ;
396 wire wbs_sm_wbr_renable_out ;
397 wire wbs_sm_wbr_flush_out ;
398 wire wbs_sm_del_in_progress_out ;
399 wire [31:0] wbs_sm_sdata_out ;
400 wire wbs_sm_ack_out ;
401 wire wbs_sm_rty_out ;
402 wire wbs_sm_err_out ;
403 wire wbs_sm_sample_address_out ;
404
405 assign wbu_conf_offset_out = wbs_sm_conf_offset_out ;
406 assign wbu_conf_renable_out = wbs_sm_conf_renable_out ;
407 assign wbu_conf_wenable_out = wbs_sm_conf_wenable_out ;
408 assign wbu_conf_be_out = ~wbs_sm_conf_be_out ;
409 assign wbu_conf_data_out = wbs_sm_conf_data_out ;
410
411 assign SDATA_O = wbs_sm_sdata_out ;
412 assign ACK_O = wbs_sm_ack_out ;
413 assign RTY_O = wbs_sm_rty_out ;
414 assign ERR_O = wbs_sm_err_out ;
415
416
417 // wbw_wbr fifo outputs
418
419 // wbw_fifo_outputs:
420 wire [31:0] fifos_wbw_addr_data_out ;
421 wire [3:0] fifos_wbw_cbe_out ;
422 wire [3:0] fifos_wbw_control_out ;
423 wire fifos_wbw_almost_full_out ;
424 wire fifos_wbw_full_out ;
425 wire fifos_wbw_half_full_out; //Robert, burst issue
426 wire fifos_wbw_empty_out ;
427 wire fifos_wbw_transaction_ready_out ;
428
429 // wbr_fifo_outputs
430 wire [31:0] fifos_wbr_data_out ;
431 wire [3:0] fifos_wbr_be_out ;
432 wire [3:0] fifos_wbr_control_out ;
433 wire fifos_wbr_empty_out ;
434
435 // address multiplexer outputs
436 wire [5:0] amux_hit_out ;
437 wire [31:0] amux_address_out ;
438
439 // delayed transaction logic outputs
440 wire [31:0] del_sync_addr_out ;
441 wire [3:0] del_sync_be_out ;
442 wire del_sync_we_out ;
443 wire del_sync_comp_req_pending_out ;
444 wire del_sync_comp_comp_pending_out ;
445 wire del_sync_req_req_pending_out ;
446 wire del_sync_req_comp_pending_out ;
447 wire [3:0] del_sync_bc_out ;
448 wire del_sync_status_out ;
449 wire del_sync_comp_flush_out ;
450 wire del_sync_burst_out ;
451
452 assign wbu_del_read_comp_pending_out = del_sync_comp_comp_pending_out ;
453
454 // delayed write storage output
455 wire [31:0] del_write_data_out ;
456
457 // config. cycle address decoder output
458 wire [31:0] ccyc_addr_out ;
459
460
461 // WISHBONE slave interface inputs
462 wire [4:0] wbs_sm_hit_in = amux_hit_out[5:1] ;
463 wire wbs_sm_conf_hit_in = amux_hit_out[0] ;
464 wire [4:0] wbs_sm_map_in = wbu_map_in[5:1] ;
465 wire [4:0] wbs_sm_pref_en_in = wbu_pref_en_in[5:1] ;
466 wire [4:0] wbs_sm_mrl_en_in = wbu_mrl_en_in[5:1] ;
467 wire [31:0] wbs_sm_addr_in = amux_address_out ;
468 wire [3:0] wbs_sm_del_bc_in = del_sync_bc_out ;
469 wire wbs_sm_del_req_pending_in = del_sync_req_req_pending_out ;
470 wire wbs_sm_wb_del_comp_pending_in = del_sync_req_comp_pending_out ;
471 wire wbs_sm_pci_drcomp_pending_in = wbu_pci_drcomp_pending_in ;
472 wire wbs_sm_del_write_in = del_sync_we_out ;
473 wire wbs_sm_del_error_in = del_sync_status_out ;
474 wire [31:0] wbs_sm_del_addr_in = del_sync_addr_out ;
475 wire [3:0] wbs_sm_del_be_in = del_sync_be_out ;
476 wire [31:0] wbs_sm_conf_data_in = wbu_conf_data_in ;
477 wire wbs_sm_wbw_almost_full_in = fifos_wbw_almost_full_out ;
478 wire wbs_sm_wbw_full_in = fifos_wbw_full_out ;
479 wire wbs_sm_wbw_half_full_in = fifos_wbw_half_full_out; ////Robert, burst issue
480 wire [3:0] wbs_sm_wbr_be_in = fifos_wbr_be_out ;
481 wire [31:0] wbs_sm_wbr_data_in = fifos_wbr_data_out ;
482 wire [3:0] wbs_sm_wbr_control_in = fifos_wbr_control_out ;
483 wire wbs_sm_wbr_empty_in = fifos_wbr_empty_out ;
484 wire wbs_sm_pciw_empty_in = wbu_pciw_empty_in ;
485 wire wbs_sm_lock_in = ~wbu_master_enable_in ;
486 wire wbs_sm_cache_line_size_not_zero = wbu_cache_line_size_not_zero ;
487 wire wbs_sm_cyc_in = CYC_I ;
488 wire wbs_sm_stb_in = STB_I ;
489 wire wbs_sm_we_in = WE_I ;
490 wire [3:0] wbs_sm_sel_in = SEL_I ;
491 wire [31:0] wbs_sm_sdata_in = SDATA_I ;
492 wire wbs_sm_cab_in = CAB_I ;
493 wire [31:0] wbs_sm_ccyc_addr_in = ccyc_addr_out ;
494 wire wbs_sm_init_complete_in = wb_init_complete_in ;
495
496 // WISHBONE slave interface instantiation
497 pci_wb_slave wishbone_slave(
498 .wb_clock_in (wb_clock_in) ,
499 .reset_in (reset_in) ,
500 .wb_hit_in (wbs_sm_hit_in) ,
501 .wb_conf_hit_in (wbs_sm_conf_hit_in) ,
502 .wb_map_in (wbs_sm_map_in) ,
503 .wb_pref_en_in (wbs_sm_pref_en_in) ,
504 .wb_mrl_en_in (wbs_sm_mrl_en_in) ,
505 .wb_addr_in (wbs_sm_addr_in),
506 .del_bc_in (wbs_sm_del_bc_in),
507 .wb_del_req_pending_in (wbs_sm_del_req_pending_in),
508 .wb_del_comp_pending_in (wbs_sm_wb_del_comp_pending_in),
509 .pci_drcomp_pending_in (wbs_sm_pci_drcomp_pending_in),
510 .del_bc_out (wbs_sm_del_bc_out),
511 .del_req_out (wbs_sm_del_req_out),
512 .del_done_out (wbs_sm_del_done_out),
513 .del_burst_out (wbs_sm_del_burst_out),
514 .del_write_out (wbs_sm_del_write_out),
515 .del_write_in (wbs_sm_del_write_in),
516 .del_error_in (wbs_sm_del_error_in),
517 .wb_del_addr_in (wbs_sm_del_addr_in),
518 .wb_del_be_in (wbs_sm_del_be_in),
519 .wb_conf_offset_out (wbs_sm_conf_offset_out),
520 .wb_conf_renable_out (wbs_sm_conf_renable_out),
521 .wb_conf_wenable_out (wbs_sm_conf_wenable_out),
522 .wb_conf_be_out (wbs_sm_conf_be_out),
523 .wb_conf_data_in (wbs_sm_conf_data_in),
524 .wb_conf_data_out (wbs_sm_conf_data_out),
525 .wb_data_out (wbs_sm_data_out),
526 .wb_cbe_out (wbs_sm_cbe_out),
527 .wbw_fifo_wenable_out (wbs_sm_wbw_wenable_out),
528 .wbw_fifo_control_out (wbs_sm_wbw_control_out),
529 .wbw_fifo_almost_full_in (wbs_sm_wbw_almost_full_in),
530 .wbw_fifo_full_in (wbs_sm_wbw_full_in),
531 .wbw_fifo_half_full_in (wbs_sm_wbw_half_full_in), ////Robert, burst issue
532 .wbr_fifo_renable_out (wbs_sm_wbr_renable_out),
533 .wbr_fifo_be_in (wbs_sm_wbr_be_in),
534 .wbr_fifo_data_in (wbs_sm_wbr_data_in),
535 .wbr_fifo_control_in (wbs_sm_wbr_control_in),
536 .wbr_fifo_flush_out (wbs_sm_wbr_flush_out),
537 .wbr_fifo_empty_in (wbs_sm_wbr_empty_in),
538 .pciw_fifo_empty_in (wbs_sm_pciw_empty_in),
539 .wbs_lock_in (wbs_sm_lock_in),
540 .init_complete_in (wbs_sm_init_complete_in),
541 .cache_line_size_not_zero (wbs_sm_cache_line_size_not_zero),
542 .del_in_progress_out (wbs_sm_del_in_progress_out),
543 .ccyc_addr_in (wbs_sm_ccyc_addr_in),
544 .sample_address_out (wbs_sm_sample_address_out),
545 .CYC_I (wbs_sm_cyc_in),
546 .STB_I (wbs_sm_stb_in),
547 .WE_I (wbs_sm_we_in),
548 .SEL_I (wbs_sm_sel_in),
549 .SDATA_I (wbs_sm_sdata_in),
550 .SDATA_O (wbs_sm_sdata_out),
551 .ACK_O (wbs_sm_ack_out),
552 .RTY_O (wbs_sm_rty_out),
553 .ERR_O (wbs_sm_err_out),
554 .CAB_I (wbs_sm_cab_in)
555 );
556
557 // wbw_wbr_fifos inputs
558 // WBW_FIFO inputs
559 wire fifos_wbw_wenable_in = wbs_sm_wbw_wenable_out;
560 wire [31:0] fifos_wbw_addr_data_in = wbs_sm_data_out ;
561 wire [3:0] fifos_wbw_cbe_in = wbs_sm_cbe_out ;
562 wire [3:0] fifos_wbw_control_in = wbs_sm_wbw_control_out ;
563 wire fifos_wbw_renable_in = pcim_if_wbw_renable_out ;
564
565 //wire fifos_wbw_flush_in = 1'b0 ; flush for write fifo not used
566
567 // WBR_FIFO inputs
568 wire fifos_wbr_wenable_in = pcim_if_wbr_wenable_out ;
569 wire [31:0] fifos_wbr_data_in = pcim_if_wbr_data_out ;
570 wire [3:0] fifos_wbr_be_in = pcim_if_wbr_be_out ;
571 wire [3:0] fifos_wbr_control_in = pcim_if_wbr_control_out ;
572 wire fifos_wbr_renable_in = wbs_sm_wbr_renable_out ;
573 wire fifos_wbr_flush_in = wbs_sm_wbr_flush_out || del_sync_comp_flush_out ;
574
575 // WBW_FIFO and WBR_FIFO instantiation
576 pci_wbw_wbr_fifos fifos
577 (
578 .wb_clock_in (wb_clock_in),
579 .pci_clock_in (pci_clock_in),
580 .reset_in (reset_in),
581 .wbw_wenable_in (fifos_wbw_wenable_in),
582 .wbw_addr_data_in (fifos_wbw_addr_data_in),
583 .wbw_cbe_in (fifos_wbw_cbe_in),
584 .wbw_control_in (fifos_wbw_control_in),
585 .wbw_renable_in (fifos_wbw_renable_in),
586 .wbw_addr_data_out (fifos_wbw_addr_data_out),
587 .wbw_cbe_out (fifos_wbw_cbe_out),
588 .wbw_control_out (fifos_wbw_control_out),
589 // .wbw_flush_in (fifos_wbw_flush_in), // flush for write fifo not used
590 .wbw_almost_full_out (fifos_wbw_almost_full_out),
591 .wbw_full_out (fifos_wbw_full_out),
592 .wbw_empty_out (fifos_wbw_empty_out),
593 .wbw_transaction_ready_out (fifos_wbw_transaction_ready_out),
594 .wbw_half_full_out (fifos_wbw_half_full_out),////Robert, burst issue
595 .wbr_wenable_in (fifos_wbr_wenable_in),
596 .wbr_data_in (fifos_wbr_data_in),
597 .wbr_be_in (fifos_wbr_be_in),
598 .wbr_control_in (fifos_wbr_control_in),
599 .wbr_renable_in (fifos_wbr_renable_in),
600 .wbr_data_out (fifos_wbr_data_out),
601 .wbr_be_out (fifos_wbr_be_out),
602 .wbr_control_out (fifos_wbr_control_out),
603 .wbr_flush_in (fifos_wbr_flush_in),
604 .wbr_empty_out (fifos_wbr_empty_out)
605
606 `ifdef PCI_BIST
607 ,
608 .mbist_si_i (mbist_si_i),
609 .mbist_so_o (mbist_so_o),
610 .mbist_ctrl_i (mbist_ctrl_i)
611 `endif
612 ) ;
613
614 wire [31:0] amux_addr_in = ADDR_I ;
615 wire amux_sample_address_in = wbs_sm_sample_address_out ;
616
617 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar0_in = wbu_bar0_in ;
618 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar1_in = wbu_bar1_in ;
619 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar2_in = wbu_bar2_in ;
620 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar3_in = wbu_bar3_in ;
621 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar4_in = wbu_bar4_in ;
622 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar5_in = wbu_bar5_in ;
623 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am0_in = wbu_am0_in ;
624 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am1_in = wbu_am1_in ;
625 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am2_in = wbu_am2_in ;
626 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am3_in = wbu_am3_in ;
627 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am4_in = wbu_am4_in ;
628 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am5_in = wbu_am5_in ;
629 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta0_in = wbu_ta0_in ;
630 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta1_in = wbu_ta1_in ;
631 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta2_in = wbu_ta2_in ;
632 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta3_in = wbu_ta3_in ;
633 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta4_in = wbu_ta4_in ;
634 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta5_in = wbu_ta5_in ;
635 wire [5:0] amux_at_en_in = wbu_at_en_in ;
636
637 pci_wb_addr_mux wb_addr_dec
638 (
639 `ifdef REGISTER_WBS_OUTPUTS
640 .clk_in (wb_clock_in),
641 .reset_in (reset_in),
642 .sample_address_in (amux_sample_address_in),
643 `endif
644 .address_in (amux_addr_in),
645 .bar0_in (amux_bar0_in),
646 .bar1_in (amux_bar1_in),
647 .bar2_in (amux_bar2_in),
648 .bar3_in (amux_bar3_in),
649 .bar4_in (amux_bar4_in),
650 .bar5_in (amux_bar5_in),
651 .am0_in (amux_am0_in),
652 .am1_in (amux_am1_in),
653 .am2_in (amux_am2_in),
654 .am3_in (amux_am3_in),
655 .am4_in (amux_am4_in),
656 .am5_in (amux_am5_in),
657 .ta0_in (amux_ta0_in),
658 .ta1_in (amux_ta1_in),
659 .ta2_in (amux_ta2_in),
660 .ta3_in (amux_ta3_in),
661 .ta4_in (amux_ta4_in),
662 .ta5_in (amux_ta5_in),
663 .at_en_in (amux_at_en_in),
664 .hit_out (amux_hit_out),
665 .address_out (amux_address_out)
666 );
667
668 // delayed transaction logic inputs
669 wire del_sync_req_in = wbs_sm_del_req_out ;
670 wire del_sync_comp_in = pcim_if_del_complete_out ;
671 wire del_sync_done_in = wbs_sm_del_done_out ;
672 wire del_sync_in_progress_in = wbs_sm_del_in_progress_out ;
673 wire [31:0] del_sync_addr_in = wbs_sm_data_out ;
674 wire [3:0] del_sync_be_in = wbs_sm_conf_be_out ;
675 wire del_sync_we_in = wbs_sm_del_write_out ;
676 wire [3:0] del_sync_bc_in = wbs_sm_del_bc_out ;
677 wire del_sync_status_in = pcim_if_del_error_out ;
678 wire del_sync_burst_in = wbs_sm_del_burst_out ;
679 wire del_sync_retry_expired_in = pcim_if_del_rty_exp_out ;
680
681 // delayed transaction logic instantiation
682 pci_delayed_sync del_sync (
683 .reset_in (reset_in),
684 .req_clk_in (wb_clock_in),
685 .comp_clk_in (pci_clock_in),
686 .req_in (del_sync_req_in),
687 .comp_in (del_sync_comp_in),
688 .done_in (del_sync_done_in),
689 .in_progress_in (del_sync_in_progress_in),
690 .comp_req_pending_out (del_sync_comp_req_pending_out),
691 .comp_comp_pending_out(del_sync_comp_comp_pending_out),
692 .req_req_pending_out (del_sync_req_req_pending_out),
693 .req_comp_pending_out (del_sync_req_comp_pending_out),
694 .addr_in (del_sync_addr_in),
695 .be_in (del_sync_be_in),
696 .addr_out (del_sync_addr_out),
697 .be_out (del_sync_be_out),
698 .we_in (del_sync_we_in),
699 .we_out (del_sync_we_out),
700 .bc_in (del_sync_bc_in),
701 .bc_out (del_sync_bc_out),
702 .status_in (del_sync_status_in),
703 .status_out (del_sync_status_out),
704 .comp_flush_out (del_sync_comp_flush_out),
705 .burst_in (del_sync_burst_in),
706 .burst_out (del_sync_burst_out),
707 .retry_expired_in (del_sync_retry_expired_in)
708 );
709
710 // delayed write storage inputs
711 wire del_write_we_in = wbs_sm_del_req_out && wbs_sm_del_write_out ;
712 wire [31:0] del_write_data_in = wbs_sm_conf_data_out ;
713
714 pci_delayed_write_reg delayed_write_data
715 (
716 .reset_in (reset_in),
717 .req_clk_in (wb_clock_in),
718 .comp_wdata_out (del_write_data_out),
719 .req_we_in (del_write_we_in),
720 .req_wdata_in (del_write_data_in)
721 );
722
723 `ifdef HOST
724 // configuration cycle address decoder input
725 wire [31:0] ccyc_addr_in = {8'h00, wbu_ccyc_addr_in} ;
726
727 pci_conf_cyc_addr_dec ccyc_addr_dec
728 (
729 .ccyc_addr_in (ccyc_addr_in),
730 .ccyc_addr_out (ccyc_addr_out)
731 ) ;
732 `else
733 `ifdef GUEST
734 assign ccyc_addr_out = 32'h0000_0000 ;
735 `endif
736 `endif
737
738 // pci master interface inputs
739 wire [31:0] pcim_if_wbw_addr_data_in = fifos_wbw_addr_data_out ;
740 wire [3:0] pcim_if_wbw_cbe_in = fifos_wbw_cbe_out ;
741 wire [3:0] pcim_if_wbw_control_in = fifos_wbw_control_out ;
742 wire pcim_if_wbw_empty_in = fifos_wbw_empty_out ;
743 wire pcim_if_wbw_transaction_ready_in = fifos_wbw_transaction_ready_out ;
744 wire [31:0] pcim_if_data_in = pcim_sm_data_out ;
745 wire [31:0] pcim_if_del_wdata_in = del_write_data_out ;
746 wire pcim_if_del_req_in = del_sync_comp_req_pending_out ;
747 wire [31:0] pcim_if_del_addr_in = del_sync_addr_out ;
748 wire [3:0] pcim_if_del_bc_in = del_sync_bc_out ;
749 wire [3:0] pcim_if_del_be_in = del_sync_be_out ;
750 wire pcim_if_del_burst_in = del_sync_burst_out ;
751 wire pcim_if_del_we_in = del_sync_we_out ;
752 wire [7:0] pcim_if_cache_line_size_in = wbu_cache_line_size_in ;
753 wire pcim_if_wait_in = pcim_sm_wait_out ;
754 wire pcim_if_wtransfer_in = pcim_sm_wtransfer_out ;
755 wire pcim_if_rtransfer_in = pcim_sm_rtransfer_out ;
756 wire pcim_if_retry_in = pcim_sm_retry_out ;
757 wire pcim_if_rerror_in = pcim_sm_rerror_out ;
758 wire pcim_if_first_in = pcim_sm_first_out ;
759 wire pcim_if_mabort_in = pcim_sm_mabort_out ;
760
761 pci_master32_sm_if pci_initiator_if
762 (
763 .clk_in (pci_clock_in),
764 .reset_in (reset_in),
765 .address_out (pcim_if_address_out),
766 .bc_out (pcim_if_bc_out),
767 .data_out (pcim_if_data_out),
768 .data_in (pcim_if_data_in),
769 .be_out (pcim_if_be_out),
770 .req_out (pcim_if_req_out),
771 .rdy_out (pcim_if_rdy_out),
772 .last_out (pcim_if_last_out),
773 .wbw_renable_out (pcim_if_wbw_renable_out),
774 .wbw_fifo_addr_data_in (pcim_if_wbw_addr_data_in),
775 .wbw_fifo_cbe_in (pcim_if_wbw_cbe_in),
776 .wbw_fifo_control_in (pcim_if_wbw_control_in),
777 .wbw_fifo_empty_in (pcim_if_wbw_empty_in),
778 .wbw_fifo_transaction_ready_in (pcim_if_wbw_transaction_ready_in),
779 .wbr_fifo_wenable_out (pcim_if_wbr_wenable_out),
780 .wbr_fifo_data_out (pcim_if_wbr_data_out),
781 .wbr_fifo_be_out (pcim_if_wbr_be_out),
782 .wbr_fifo_control_out (pcim_if_wbr_control_out),
783 .del_wdata_in (pcim_if_del_wdata_in),
784 .del_complete_out (pcim_if_del_complete_out),
785 .del_req_in (pcim_if_del_req_in),
786 .del_addr_in (pcim_if_del_addr_in),
787 .del_bc_in (pcim_if_del_bc_in),
788 .del_be_in (pcim_if_del_be_in),
789 .del_burst_in (pcim_if_del_burst_in),
790 .del_error_out (pcim_if_del_error_out),
791 .del_rty_exp_out (pcim_if_del_rty_exp_out),
792 .del_we_in (pcim_if_del_we_in),
793 .err_addr_out (pcim_if_err_addr_out),
794 .err_bc_out (pcim_if_err_bc_out),
795 .err_signal_out (pcim_if_err_signal_out),
796 .err_source_out (pcim_if_err_source_out),
797 .err_rty_exp_out (pcim_if_err_rty_exp_out),
798 .cache_line_size_in (pcim_if_cache_line_size_in),
799 .mabort_received_out (pcim_if_mabort_out),
800 .tabort_received_out (pcim_if_tabort_out),
801 .next_data_out (pcim_if_next_data_out),
802 .next_be_out (pcim_if_next_be_out),
803 .next_last_out (pcim_if_next_last_out),
804 .wait_in (pcim_if_wait_in),
805 .wtransfer_in (pcim_if_wtransfer_in),
806 .rtransfer_in (pcim_if_rtransfer_in),
807 .retry_in (pcim_if_retry_in),
808 .rerror_in (pcim_if_rerror_in),
809 .first_in (pcim_if_first_in),
810 .mabort_in (pcim_if_mabort_in),
811 .posted_write_not_present_out (pcim_if_posted_write_not_present_out)
812 );
813
814 // pci master state machine inputs
815 wire pcim_sm_gnt_in = wbu_pciif_gnt_in ;
816 wire pcim_sm_frame_in = wbu_pciif_frame_in ;
817 wire pcim_sm_irdy_in = wbu_pciif_irdy_in ;
818 wire pcim_sm_trdy_in = wbu_pciif_trdy_in;
819 wire pcim_sm_stop_in = wbu_pciif_stop_in ;
820 wire pcim_sm_devsel_in = wbu_pciif_devsel_in ;
821 wire [31:0] pcim_sm_ad_reg_in = wbu_pciif_ad_reg_in ;
822 wire [31:0] pcim_sm_address_in = pcim_if_address_out ;
823 wire [3:0] pcim_sm_bc_in = pcim_if_bc_out ;
824 wire [31:0] pcim_sm_data_in = pcim_if_data_out ;
825 wire [3:0] pcim_sm_be_in = pcim_if_be_out ;
826 wire pcim_sm_req_in = pcim_if_req_out ;
827 wire pcim_sm_rdy_in = pcim_if_rdy_out ;
828 wire pcim_sm_last_in = pcim_if_last_out ;
829 wire [7:0] pcim_sm_latency_tim_val_in = wbu_latency_tim_val_in ;
830 wire [31:0] pcim_sm_next_data_in = pcim_if_next_data_out ;
831 wire [3:0] pcim_sm_next_be_in = pcim_if_next_be_out ;
832 wire pcim_sm_next_last_in = pcim_if_next_last_out ;
833 wire pcim_sm_trdy_reg_in = wbu_pciif_trdy_reg_in ;
834 wire pcim_sm_stop_reg_in = wbu_pciif_stop_reg_in ;
835 wire pcim_sm_devsel_reg_in = wbu_pciif_devsel_reg_in ;
836 wire pcim_sm_frame_en_in = wbu_pciif_frame_en_in ;
837 wire pcim_sm_frame_out_in = wbu_pciif_frame_out_in ;
838
839 pci_master32_sm pci_initiator_sm
840 (
841 .clk_in (pci_clock_in),
842 .reset_in (reset_in),
843 .pci_req_out (pcim_sm_req_out),
844 .pci_gnt_in (pcim_sm_gnt_in),
845 .pci_frame_in (pcim_sm_frame_in),
846 .pci_frame_out (pcim_sm_frame_out),
847 .pci_frame_en_out (pcim_sm_frame_en_out),
848 .pci_frame_out_in (pcim_sm_frame_out_in),
849 .pci_frame_load_out (pcim_sm_frame_load_out),
850 .pci_frame_en_in (pcim_sm_frame_en_in),
851 .pci_irdy_in (pcim_sm_irdy_in),
852 .pci_irdy_out (pcim_sm_irdy_out),
853 .pci_irdy_en_out (pcim_sm_irdy_en_out),
854 .pci_trdy_in (pcim_sm_trdy_in),
855 .pci_trdy_reg_in (pcim_sm_trdy_reg_in),
856 .pci_stop_in (pcim_sm_stop_in),
857 .pci_stop_reg_in (pcim_sm_stop_reg_in),
858 .pci_devsel_in (pcim_sm_devsel_in),
859 .pci_devsel_reg_in (pcim_sm_devsel_reg_in),
860 .pci_ad_reg_in (pcim_sm_ad_reg_in),
861 .pci_ad_out (pcim_sm_ad_out),
862 .pci_ad_en_out (pcim_sm_ad_en_out),
863 .pci_cbe_out (pcim_sm_cbe_out),
864 .pci_cbe_en_out (pcim_sm_cbe_en_out),
865 .address_in (pcim_sm_address_in),
866 .bc_in (pcim_sm_bc_in),
867 .data_in (pcim_sm_data_in),
868 .data_out (pcim_sm_data_out),
869 .be_in (pcim_sm_be_in),
870 .req_in (pcim_sm_req_in),
871 .rdy_in (pcim_sm_rdy_in),
872 .last_in (pcim_sm_last_in),
873 .latency_tim_val_in (pcim_sm_latency_tim_val_in),
874 .next_data_in (pcim_sm_next_data_in),
875 .next_be_in (pcim_sm_next_be_in),
876 .next_last_in (pcim_sm_next_last_in),
877 .ad_load_out (pcim_sm_ad_load_out),
878 .ad_load_on_transfer_out (pcim_sm_ad_load_on_transfer_out),
879 .wait_out (pcim_sm_wait_out),
880 .wtransfer_out (pcim_sm_wtransfer_out),
881 .rtransfer_out (pcim_sm_rtransfer_out),
882 .retry_out (pcim_sm_retry_out),
883 .rerror_out (pcim_sm_rerror_out),
884 .first_out (pcim_sm_first_out),
885 .mabort_out (pcim_sm_mabort_out)
886 ) ;
887
888 endmodule
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