typos
[raggedstone] / heartbeat / source / top_raggedstone.vhd
1 --+-------------------------------------------------------------------------------------------------+
2 --| |
3 --| File: top.vhd |
4 --| |
5 --| Components: pci32lite.vhd |
6 --| pciwbsequ.vhd |
7 --| pcidmux.vhd |
8 --| pciregs.vhd |
9 --| pcipargen.vhd |
10 --| -- Libs -- |
11 --| ona.vhd |
12 --| |
13 --| Description: RS1 PCI Demo : (TOP) Main file. |
14 --| |
15 --| |
16 --| |
17 --+-------------------------------------------------------------------------------------------------+
18 --| |
19 --| Revision history : |
20 --| Date Version Author Description |
21 --| |
22 --| |
23 --| To do: |
24 --| |
25 --+-------------------------------------------------------------------------------------------------+
26
27
28 --+-----------------------------------------------------------------------------+
29 --| LIBRARIES |
30 --+-----------------------------------------------------------------------------+
31
32 library ieee;
33 use ieee.std_logic_1164.all;
34 use ieee.std_logic_arith.all;
35 use ieee.std_logic_unsigned.all;
36
37 --+-----------------------------------------------------------------------------+
38 --| ENTITY |
39 --+-----------------------------------------------------------------------------+
40
41 entity raggedstone is
42 port (
43
44 -- General
45 PCI_CLK : in std_logic;
46 PCI_nRES : in std_logic;
47
48 -- PCI target 32bits
49 PCI_AD : inout std_logic_vector(31 downto 0);
50 PCI_CBE : in std_logic_vector(3 downto 0);
51 PCI_PAR : out std_logic;
52 PCI_nFRAME : in std_logic;
53 PCI_nIRDY : in std_logic;
54 PCI_nTRDY : out std_logic;
55 PCI_nDEVSEL : out std_logic;
56 PCI_nSTOP : out std_logic;
57 PCI_IDSEL : in std_logic;
58 PCI_nPERR : out std_logic;
59 PCI_nSERR : out std_logic;
60 PCI_nINT : out std_logic;
61
62 -- debug signals
63 LED3 : out std_logic;
64 LED2 : out std_logic;
65 LED4 : out std_logic;
66 LED5 : out std_logic
67
68 );
69 end raggedstone;
70
71
72 --+-----------------------------------------------------------------------------+
73 --| ARCHITECTURE |
74 --+-----------------------------------------------------------------------------+
75
76 architecture raggedstone_arch of raggedstone is
77
78
79 --+-----------------------------------------------------------------------------+
80 --| COMPONENTS |
81 --+-----------------------------------------------------------------------------+
82
83 component pci32tlite
84 port (
85
86 -- General
87 clk33 : in std_logic;
88 nrst : in std_logic;
89
90 -- PCI target 32bits
91 ad : inout std_logic_vector(31 downto 0);
92 cbe : in std_logic_vector(3 downto 0);
93 par : out std_logic;
94 frame : in std_logic;
95 irdy : in std_logic;
96 trdy : out std_logic;
97 devsel : out std_logic;
98 stop : out std_logic;
99 idsel : in std_logic;
100 perr : out std_logic;
101 serr : out std_logic;
102 intb : out std_logic;
103
104 -- Master whisbone
105 wb_adr_o : out std_logic_vector(24 downto 1);
106 wb_dat_i : in std_logic_vector(15 downto 0);
107 wb_dat_o : out std_logic_vector(15 downto 0);
108 wb_sel_o : out std_logic_vector(1 downto 0);
109 wb_we_o : out std_logic;
110 wb_stb_o : out std_logic;
111 wb_cyc_o : out std_logic;
112 wb_ack_i : in std_logic;
113 wb_err_i : in std_logic;
114 wb_int_i : in std_logic;
115
116 -- debug signals
117 debug_init : out std_logic;
118 debug_access : out std_logic
119
120 );
121 end component;
122
123 component heartbeat
124 port (
125 clk_i : in std_logic;
126 nrst_i : in std_logic;
127 led2_o : out std_logic;
128 led3_o : out std_logic;
129 led4_o : out std_logic;
130 led5_o : out std_logic
131 );
132 end component;
133
134
135 --+-----------------------------------------------------------------------------+
136 --| CONSTANTS |
137 --+-----------------------------------------------------------------------------+
138 --+-----------------------------------------------------------------------------+
139 --| SIGNALS |
140 --+-----------------------------------------------------------------------------+
141
142 signal wb_adr : std_logic_vector(24 downto 1);
143 signal wb_dat_out : std_logic_vector(15 downto 0);
144 signal wb_dat_in : std_logic_vector(15 downto 0);
145 signal wb_sel : std_logic_vector(1 downto 0);
146 signal wb_we : std_logic;
147 signal wb_stb : std_logic;
148 signal wb_cyc : std_logic;
149 signal wb_ack : std_logic;
150 signal wb_err : std_logic;
151 signal wb_int : std_logic;
152
153
154 begin
155
156 --+-----------------------------------------+
157 --| PCI Target |
158 --+-----------------------------------------+
159
160 u_pci: component pci32tlite
161 port map(
162 clk33 => PCI_CLK,
163 nrst => PCI_nRES,
164 ad => PCI_AD,
165 cbe => PCI_CBE,
166 par => PCI_PAR,
167 frame => PCI_nFRAME,
168 irdy => PCI_nIRDY,
169 trdy => PCI_nTRDY,
170 devsel => PCI_nDEVSEL,
171 stop => PCI_nSTOP,
172 idsel => PCI_IDSEL,
173 perr => PCI_nPERR,
174 serr => PCI_nSERR,
175 intb => PCI_nINT,
176 wb_adr_o => wb_adr,
177 wb_dat_i => wb_dat_out,
178 wb_dat_o => wb_dat_in,
179 wb_sel_o => wb_sel,
180 wb_we_o => wb_we,
181 wb_stb_o => wb_stb,
182 wb_cyc_o => wb_cyc,
183 wb_ack_i => wb_ack,
184 wb_err_i => wb_err,
185 wb_int_i => wb_int
186 -- debug_init => LED3,
187 -- debug_access => LED2
188 );
189
190 --+-----------------------------------------+
191 --| WB-7seg |
192 --+-----------------------------------------+
193
194 my_heartbeat: component heartbeat
195 port map(
196 clk_i => PCI_CLK,
197 nrst_i => PCI_nRES,
198 led2_o => LED2,
199 led3_o => LED3,
200 led4_o => LED4,
201 led5_o => LED5
202 );
203
204 end raggedstone_arch;
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