rename pci_7seg to raggedstone
[raggedstone] / heartbeat / source / top_raggedstone.vhd
1 --+-------------------------------------------------------------------------------------------------+
2 --| |
3 --| File: top.vhd |
4 --| |
5 --| Components: pci32lite.vhd |
6 --| pciwbsequ.vhd |
7 --| pcidmux.vhd |
8 --| pciregs.vhd |
9 --| pcipargen.vhd |
10 --| -- Libs -- |
11 --| ona.vhd |
12 --| |
13 --| Description: RS1 PCI Demo : (TOP) Main file. |
14 --| |
15 --| |
16 --| |
17 --+-------------------------------------------------------------------------------------------------+
18 --| |
19 --| Revision history : |
20 --| Date Version Author Description |
21 --| |
22 --| |
23 --| To do: |
24 --| |
25 --+-------------------------------------------------------------------------------------------------+
26
27
28 --+-----------------------------------------------------------------------------+
29 --| LIBRARIES |
30 --+-----------------------------------------------------------------------------+
31
32 library ieee;
33 use ieee.std_logic_1164.all;
34 use ieee.std_logic_arith.all;
35 use ieee.std_logic_unsigned.all;
36
37 --+-----------------------------------------------------------------------------+
38 --| ENTITY |
39 --+-----------------------------------------------------------------------------+
40
41 entity raggedstone is
42 port (
43
44 -- General
45 PCI_CLK : in std_logic;
46 PCI_nRES : in std_logic;
47
48 -- PCI target 32bits
49 PCI_AD : inout std_logic_vector(31 downto 0);
50 PCI_CBE : in std_logic_vector(3 downto 0);
51 PCI_PAR : out std_logic;
52 PCI_nFRAME : in std_logic;
53 PCI_nIRDY : in std_logic;
54 PCI_nTRDY : out std_logic;
55 PCI_nDEVSEL : out std_logic;
56 PCI_nSTOP : out std_logic;
57 PCI_IDSEL : in std_logic;
58 PCI_nPERR : out std_logic;
59 PCI_nSERR : out std_logic;
60 PCI_nINT : out std_logic;
61
62 -- debug signals
63 LED_INIT : out std_logic;
64 LED_ACCESS : out std_logic;
65 LED_ALIVE : out std_logic
66
67 );
68 end raggedstone;
69
70
71 --+-----------------------------------------------------------------------------+
72 --| ARCHITECTURE |
73 --+-----------------------------------------------------------------------------+
74
75 architecture raggedstone_arch of raggedstone is
76
77
78 --+-----------------------------------------------------------------------------+
79 --| COMPONENTS |
80 --+-----------------------------------------------------------------------------+
81
82 component pci32tlite
83 port (
84
85 -- General
86 clk33 : in std_logic;
87 nrst : in std_logic;
88
89 -- PCI target 32bits
90 ad : inout std_logic_vector(31 downto 0);
91 cbe : in std_logic_vector(3 downto 0);
92 par : out std_logic;
93 frame : in std_logic;
94 irdy : in std_logic;
95 trdy : out std_logic;
96 devsel : out std_logic;
97 stop : out std_logic;
98 idsel : in std_logic;
99 perr : out std_logic;
100 serr : out std_logic;
101 intb : out std_logic;
102
103 -- Master whisbone
104 wb_adr_o : out std_logic_vector(24 downto 1);
105 wb_dat_i : in std_logic_vector(15 downto 0);
106 wb_dat_o : out std_logic_vector(15 downto 0);
107 wb_sel_o : out std_logic_vector(1 downto 0);
108 wb_we_o : out std_logic;
109 wb_stb_o : out std_logic;
110 wb_cyc_o : out std_logic;
111 wb_ack_i : in std_logic;
112 wb_err_i : in std_logic;
113 wb_int_i : in std_logic;
114
115 -- debug signals
116 debug_init : out std_logic;
117 debug_access : out std_logic
118
119 );
120 end component;
121
122 component heartbeat
123 port (
124 clk_i : in std_logic;
125 nrst_i : in std_logic;
126 led_o : out std_logic
127 );
128 end component;
129
130
131 --+-----------------------------------------------------------------------------+
132 --| CONSTANTS |
133 --+-----------------------------------------------------------------------------+
134 --+-----------------------------------------------------------------------------+
135 --| SIGNALS |
136 --+-----------------------------------------------------------------------------+
137
138 signal wb_adr : std_logic_vector(24 downto 1);
139 signal wb_dat_out : std_logic_vector(15 downto 0);
140 signal wb_dat_in : std_logic_vector(15 downto 0);
141 signal wb_sel : std_logic_vector(1 downto 0);
142 signal wb_we : std_logic;
143 signal wb_stb : std_logic;
144 signal wb_cyc : std_logic;
145 signal wb_ack : std_logic;
146 signal wb_err : std_logic;
147 signal wb_int : std_logic;
148
149
150 begin
151
152 --+-----------------------------------------+
153 --| PCI Target |
154 --+-----------------------------------------+
155
156 u_pci: component pci32tlite
157 port map(
158 clk33 => PCI_CLK,
159 nrst => PCI_nRES,
160 ad => PCI_AD,
161 cbe => PCI_CBE,
162 par => PCI_PAR,
163 frame => PCI_nFRAME,
164 irdy => PCI_nIRDY,
165 trdy => PCI_nTRDY,
166 devsel => PCI_nDEVSEL,
167 stop => PCI_nSTOP,
168 idsel => PCI_IDSEL,
169 perr => PCI_nPERR,
170 serr => PCI_nSERR,
171 intb => PCI_nINT,
172 wb_adr_o => wb_adr,
173 wb_dat_i => wb_dat_out,
174 wb_dat_o => wb_dat_in,
175 wb_sel_o => wb_sel,
176 wb_we_o => wb_we,
177 wb_stb_o => wb_stb,
178 wb_cyc_o => wb_cyc,
179 wb_ack_i => wb_ack,
180 wb_err_i => wb_err,
181 wb_int_i => wb_int,
182 debug_init => LED_INIT,
183 debug_access => LED_ACCESS
184 );
185
186 --+-----------------------------------------+
187 --| WB-7seg |
188 --+-----------------------------------------+
189
190 my_heartbeat: component heartbeat
191 port map(
192 clk_i => PCI_CLK,
193 nrst_i => PCI_nRES,
194 led_o => LED_ALIVE
195 );
196
197 end raggedstone_arch;
Impressum, Datenschutz