?
[raggedstone] / dhwk / source / top.vhd
1 -- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007
2
3
4
5 LIBRARY ieee;
6
7 USE ieee.std_logic_1164.ALL;
8 USE ieee.numeric_std.ALL;
9
10
11 entity dhwk is
12 Port ( KONST_1 : In std_logic;
13 PCI_CBEn : In std_logic_vector (3 downto 0);
14 PCI_CLOCK : In std_logic;
15 PCI_FRAMEn : In std_logic;
16 PCI_IDSEL : In std_logic;
17 PCI_IRDYn : In std_logic;
18 PCI_RSTn : In std_logic;
19 -- SERIAL_IN : In std_logic;
20 -- SPC_RDY_IN : In std_logic;
21 TAST_RESn : In std_logic;
22 TAST_SETn : In std_logic;
23 LED_2 : out std_logic;
24 LED_3 : out std_logic;
25 LED_4 : out std_logic;
26 LED_5 : out std_logic;
27 PCI_AD : InOut std_logic_vector (31 downto 0);
28 PCI_PAR : InOut std_logic;
29 PCI_DEVSELn : Out std_logic;
30 PCI_INTAn : Out std_logic;
31 PCI_PERRn : Out std_logic;
32 PCI_SERRn : Out std_logic;
33 PCI_STOPn : Out std_logic;
34 PCI_TRDYn : Out std_logic;
35 -- SERIAL_OUT : Out std_logic;
36 -- SPC_RDY_OUT : Out std_logic;
37 TB_IDSEL : Out std_logic;
38 TB_nDEVSEL : Out std_logic;
39 TB_nINTA : Out std_logic );
40 end dhwk;
41
42 architecture SCHEMATIC of dhwk is
43
44 SIGNAL gnd : std_logic := '0';
45 SIGNAL vcc : std_logic := '1';
46
47 signal READ_XX7_6 : std_logic;
48 signal RESERVE : std_logic;
49 signal SR_ERROR : std_logic;
50 signal R_ERROR : std_logic;
51 signal S_ERROR : std_logic;
52 signal WRITE_XX3_2 : std_logic;
53 signal WRITE_XX5_4 : std_logic;
54 signal WRITE_XX7_6 : std_logic;
55 signal READ_XX1_0 : std_logic;
56 signal READ_XX3_2 : std_logic;
57 signal INTAn : std_logic;
58 signal TRDYn : std_logic;
59 signal READ_XX5_4 : std_logic;
60 signal DEVSELn : std_logic;
61 signal FIFO_RDn : std_logic;
62 signal WRITE_XX1_0 : std_logic;
63 signal REG_OUT_XX6 : std_logic_vector (7 downto 0);
64 signal SYNC_FLAG : std_logic_vector (7 downto 0);
65 signal INT_REG : std_logic_vector (7 downto 0);
66 signal REVISON_ID : std_logic_vector (7 downto 0);
67 signal VENDOR_ID : std_logic_vector (15 downto 0);
68 signal READ_SEL : std_logic_vector (1 downto 0);
69 signal AD_REG : std_logic_vector (31 downto 0);
70 signal REG_OUT_XX7 : std_logic_vector (7 downto 0);
71 signal R_EFn : std_logic;
72 signal R_FFn : std_logic;
73 signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);
74 signal R_HFn : std_logic;
75 signal S_EFn : std_logic;
76 signal S_FFn : std_logic;
77 signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);
78 signal S_HFn : std_logic;
79 signal R_FIFO_D_IN : std_logic_vector (7 downto 0);
80 signal R_FIFO_READn : std_logic;
81 signal R_FIFO_RESETn : std_logic;
82 signal R_FIFO_RTn : std_logic;
83 signal R_FIFO_WRITEn : std_logic;
84 signal S_FIFO_D_IN : std_logic_vector (7 downto 0);
85 signal S_FIFO_READn : std_logic;
86 signal S_FIFO_RESETn : std_logic;
87 signal S_FIFO_RTn : std_logic;
88 signal S_FIFO_WRITEn : std_logic;
89 signal SERIAL_IN : std_logic;
90 signal SPC_RDY_IN : std_logic;
91 signal SERIAL_OUT : std_logic;
92 signal SPC_RDY_OUT : std_logic;
93 signal watch : std_logic;
94
95 component MESS_1_TB
96 Port ( DEVSELn : In std_logic;
97 INTAn : In std_logic;
98 KONST_1 : In std_logic;
99 PCI_IDSEL : In std_logic;
100 REG_OUT_XX7 : In std_logic_vector (7 downto 0);
101 TB_DEVSELn : Out std_logic;
102 TB_INTAn : Out std_logic;
103 TB_PCI_IDSEL : Out std_logic );
104 end component;
105
106 component VEN_REV_ID
107 Port ( REV_ID : Out std_logic_vector (7 downto 0);
108 VEN_ID : Out std_logic_vector (15 downto 0) );
109 end component;
110
111 component INTERRUPT
112 Port ( INT_IN_0 : In std_logic;
113 INT_IN_1 : In std_logic;
114 INT_IN_2 : In std_logic;
115 INT_IN_3 : In std_logic;
116 INT_IN_4 : In std_logic;
117 INT_IN_5 : In std_logic;
118 INT_IN_6 : In std_logic;
119 INT_IN_7 : In std_logic;
120 INT_MASKE : In std_logic_vector (7 downto 0);
121 INT_RES : In std_logic_vector (7 downto 0);
122 PCI_CLOCK : In std_logic;
123 PCI_RSTn : In std_logic;
124 READ_XX5_4 : In std_logic;
125 RESET : In std_logic;
126 TAST_RESn : In std_logic;
127 TAST_SETn : In std_logic;
128 TRDYn : In std_logic;
129 INT_REG : Out std_logic_vector (7 downto 0);
130 INTAn : Out std_logic;
131 PCI_INTAn : Out std_logic );
132 end component;
133
134 component FIFO_CONTROL
135 Port ( FIFO_RDn : In std_logic;
136 FLAG_IN_0 : In std_logic;
137 FLAG_IN_4 : In std_logic;
138 HOLD : In std_logic;
139 KONST_1 : In std_logic;
140 PCI_CLOCK : In std_logic;
141 PSC_ENABLE : In std_logic;
142 R_EFn : In std_logic;
143 R_FFn : In std_logic;
144 R_HFn : In std_logic;
145 RESET : In std_logic;
146 S_EFn : In std_logic;
147 S_FFn : In std_logic;
148 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
149 S_HFn : In std_logic;
150 SERIAL_IN : In std_logic;
151 SPC_ENABLE : In std_logic;
152 SPC_RDY_IN : In std_logic;
153 WRITE_XX1_0 : In std_logic;
154 R_ERROR : Out std_logic;
155 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
156 R_FIFO_READn : Out std_logic;
157 R_FIFO_RESETn : Out std_logic;
158 R_FIFO_RETRANSMITn : Out std_logic;
159 R_FIFO_WRITEn : Out std_logic;
160 RESERVE : Out std_logic;
161 S_ERROR : Out std_logic;
162 S_FIFO_READn : Out std_logic;
163 S_FIFO_RESETn : Out std_logic;
164 S_FIFO_RETRANSMITn : Out std_logic;
165 S_FIFO_WRITEn : Out std_logic;
166 SERIAL_OUT : Out std_logic;
167 SPC_RDY_OUT : Out std_logic;
168 SR_ERROR : Out std_logic;
169 SYNC_FLAG : Out std_logic_vector (7 downto 0) );
170 end component;
171
172 component PCI_TOP
173 Port ( FLAG : In std_logic_vector (7 downto 0);
174 INT_REG : In std_logic_vector (7 downto 0);
175 PCI_CBEn : In std_logic_vector (3 downto 0);
176 PCI_CLOCK : In std_logic;
177 PCI_FRAMEn : In std_logic;
178 PCI_IDSEL : In std_logic;
179 PCI_IRDYn : In std_logic;
180 PCI_RSTn : In std_logic;
181 R_FIFO_Q : In std_logic_vector (7 downto 0);
182 REVISON_ID : In std_logic_vector (7 downto 0);
183 VENDOR_ID : In std_logic_vector (15 downto 0);
184 PCI_AD : InOut std_logic_vector (31 downto 0);
185 PCI_PAR : InOut std_logic;
186 AD_REG : Out std_logic_vector (31 downto 0);
187 DEVSELn : Out std_logic;
188 FIFO_RDn : Out std_logic;
189 PCI_DEVSELn : Out std_logic;
190 PCI_PERRn : Out std_logic;
191 PCI_SERRn : Out std_logic;
192 PCI_STOPn : Out std_logic;
193 PCI_TRDYn : Out std_logic;
194 READ_SEL : Out std_logic_vector (1 downto 0);
195 READ_XX1_0 : Out std_logic;
196 READ_XX3_2 : Out std_logic;
197 READ_XX5_4 : Out std_logic;
198 READ_XX7_6 : Out std_logic;
199 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
200 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
201 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
202 TRDYn : Out std_logic;
203 WRITE_XX1_0 : Out std_logic;
204 WRITE_XX3_2 : Out std_logic;
205 WRITE_XX5_4 : Out std_logic;
206 WRITE_XX7_6 : Out std_logic );
207 end component;
208
209 component fifo_generator_v3_2
210 port (
211 clk: IN std_logic;
212 din: IN std_logic_VECTOR(7 downto 0);
213 rd_en: IN std_logic;
214 rst: IN std_logic;
215 wr_en: IN std_logic;
216 almost_empty: OUT std_logic;
217 almost_full: OUT std_logic;
218 dout: OUT std_logic_VECTOR(7 downto 0);
219 empty: OUT std_logic;
220 full: OUT std_logic;
221 prog_full: OUT std_logic);
222 end component;
223
224 begin
225 SERIAL_IN <= SERIAL_OUT;
226 SPC_RDY_IN <= SPC_RDY_OUT;
227 LED_2 <= TAST_RESn;
228 LED_3 <= TAST_SETn;
229 LED_4 <= '0';
230 LED_5 <= not watch;
231 PCI_INTAn <= watch;
232
233 I19 : MESS_1_TB
234 Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
235 PCI_IDSEL=>PCI_IDSEL,
236 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
237 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,
238 TB_PCI_IDSEL=>TB_IDSEL );
239 I18 : VEN_REV_ID
240 Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),
241 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );
242 I16 : INTERRUPT
243 Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),
244 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,
245 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,
246 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),
247 INT_RES(7 downto 0)=>AD_REG(7 downto 0),
248 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
249 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
250 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
251 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
252 INTAn=>INTAn, PCI_INTAn=>watch);
253 I14 : FIFO_CONTROL
254 Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
255 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
256 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),
257 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,
258 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,
259 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
260 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,
261 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,
262 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
263 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
264 R_FIFO_READn=>R_FIFO_READn,
265 R_FIFO_RESETn=>R_FIFO_RESETn,
266 R_FIFO_RETRANSMITn=>R_FIFO_RTn,
267 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,
268 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,
269 S_FIFO_RESETn=>S_FIFO_RESETn,
270 S_FIFO_RETRANSMITn=>S_FIFO_RTn,
271 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
272 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
273 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
274 I1 : PCI_TOP
275 Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),
276 INT_REG(7 downto 0)=>INT_REG(7 downto 0),
277 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
278 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
279 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
280 PCI_RSTn=>PCI_RSTn,
281 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),
282 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
283 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
284 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
285 PCI_PAR=>PCI_PAR,
286 AD_REG(31 downto 0)=>AD_REG(31 downto 0),
287 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
288 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
289 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
290 PCI_TRDYn=>PCI_TRDYn,
291 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
292 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
293 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,
294 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),
295 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
296 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
297 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,
298 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
299 WRITE_XX7_6=>WRITE_XX7_6 );
300
301 receive_fifo : fifo_generator_v3_2
302 port map (
303 clk => PCI_CLOCK,
304 din => R_FIFO_D_IN,
305 rd_en => not R_FIFO_READn,
306 rst => not R_FIFO_RESETn,
307 wr_en => not R_FIFO_WRITEn,
308 dout => R_FIFO_Q_OUT,
309 empty => R_EFn,
310 full => R_FFn,
311 prog_full => R_HFn);
312
313 send_fifo : fifo_generator_v3_2
314 port map (
315 clk => PCI_CLOCK,
316 din => S_FIFO_D_IN,
317 rd_en => not S_FIFO_READn,
318 rst => not S_FIFO_RESETn,
319 wr_en => not S_FIFO_WRITEn,
320 dout => S_FIFO_Q_OUT,
321 empty => S_EFn,
322 full => S_FFn,
323 prog_full => S_HFn);
324 end SCHEMATIC;
Impressum, Datenschutz