git.zerfleddert.de Git - raggedstone/blob - dhwk/source/par_ser_con.vhd

   1 -- $Id: par_ser_con.vhd,v 1.4 2007-03-11 13:23:11 sithglan Exp $
   2
   3 library ieee;
   4 use ieee.std_logic_1164.all;
   5 use ieee.std_logic_unsigned.all;
   6
   7 entity  PAR_SER_CON     is
   8         port
   9         (
  10                 PCI_CLOCK               :in     std_logic;
  11                 RESET                           :in     std_logic;
  12                 PSC_ENABLE                      :in     std_logic; -- Parallel Serial Converter Enable
  13                 SYNC_S_FIFO_EFn                 :in     std_logic; -- Empty Flag (low active)
  14                 SPC_RDY_IN                      :in     std_logic; -- Ready to receive data
  15                 PAR_IN                          :in     std_logic_vector(7 downto 0);
  16                 SER_OUT                         :out    std_logic; -- Serial Output
  17                 S_FIFO_READn                    :out    std_logic  -- FIFO Read (low active)
  18         );
  19 end entity      PAR_SER_CON ;
  20
  21 architecture PAR_SER_CON_DESIGN of PAR_SER_CON is
  22
  23         constant STATE_END        :std_logic_vector(3 downto 0) := "0001";
  24         constant STATE_SEND       :std_logic_vector(3 downto 0) := "0010";
  25         constant STATE_SEND_BIT_0 :std_logic_vector(3 downto 0) := "0011";
  26         constant STATE_SEND_BIT_1 :std_logic_vector(3 downto 0) := "0100";
  27         constant STATE_SEND_BIT_2 :std_logic_vector(3 downto 0) := "0101";
  28         constant STATE_SEND_BIT_3 :std_logic_vector(3 downto 0) := "0110";
  29         constant STATE_SEND_BIT_4 :std_logic_vector(3 downto 0) := "0111";
  30         constant STATE_SEND_BIT_5 :std_logic_vector(3 downto 0) := "1000";
  31         constant STATE_SEND_BIT_6 :std_logic_vector(3 downto 0) := "1001";
  32         constant STATE_SEND_BIT_7 :std_logic_vector(3 downto 0) := "1010";
  33
  34         signal COUNT     :std_logic_vector (3 downto 0);
  35         signal STATE     :std_logic_vector (3 downto 0);
  36         signal DATUM     :std_logic_vector (7 downto 0);
  37         signal SYNC                      :std_logic; -- make SPC_RDY_IN stable
  38
  39         attribute syn_state_machine:boolean;
  40         attribute syn_state_machine of STATE: signal is false;
  41         attribute syn_state_machine of COUNT: signal is false;
  42 begin
  43
  44         process(PCI_CLOCK)
  45         begin
  46                 if (rising_edge(PCI_CLOCK)) then
  47                         if ("0000" < COUNT) then
  48                                 COUNT <= COUNT - 1;
  49                         end if;
  50
  51                         if (RESET = '1') then
  52                                 STATE <= STATE_SEND;
  53                                 COUNT <= "0000";
  54                                 SER_OUT <= '0';
  55                                 S_FIFO_READn <= '1';
  56
  57                         elsif (PSC_ENABLE = '1') then
  58                                 if (COUNT = "0000") then
  59                                         COUNT <= "0011";
  60                                         case STATE is
  61                                         when STATE_SEND =>
  62                                                 if(SYNC = '1' and SYNC_S_FIFO_EFn = '1') then
  63                                                         SER_OUT <= '1';
  64                                                         S_FIFO_READn <= '0';
  65                                                         STATE <= STATE_SEND_BIT_0;
  66                                                 end if;
  67
  68                                         when STATE_SEND_BIT_0 =>
  69                                                 DATUM     <= PAR_IN;
  70                                                 S_FIFO_READn <= '1';
  71                                                 SER_OUT <= PAR_IN(0);
  72                                                 STATE <= STATE_SEND_BIT_1;
  73
  74                                         when STATE_SEND_BIT_1 =>
  75                                                 SER_OUT <= DATUM(1);
  76                                                 STATE <= STATE_SEND_BIT_2;
  77
  78                                         when STATE_SEND_BIT_2 =>
  79                                                 SER_OUT <= DATUM(2);
  80                                                 STATE <= STATE_SEND_BIT_3;
  81
  82                                         when STATE_SEND_BIT_3 =>
  83                                                 SER_OUT <= DATUM(3);
  84                                                 STATE <= STATE_SEND_BIT_4;
  85
  86                                         when STATE_SEND_BIT_4 =>
  87                                                 SER_OUT <= DATUM(4);
  88                                                 STATE <= STATE_SEND_BIT_5;
  89
  90                                         when STATE_SEND_BIT_5 =>
  91                                                 SER_OUT <= DATUM(5);
  92                                                 STATE <= STATE_SEND_BIT_6;
  93
  94                                         when STATE_SEND_BIT_6 =>
  95                                                 SER_OUT <= DATUM(6);
  96                                                 STATE <= STATE_SEND_BIT_7;
  97
  98                                         when STATE_SEND_BIT_7 =>
  99                                                 SER_OUT <= DATUM(7);
 100                                                 STATE <= STATE_END;
 101
 102                                         when STATE_END =>
 103                                                 SER_OUT <= '0';
 104                                                 STATE <= STATE_SEND;
 105
 106                                         when others => STATE <= STATE_END;
 107                                         end case;
 108
 109                                 else
 110                                         S_FIFO_READn <= '1';
 111                                 end if; -- COUNT
 112                         end if; -- RESET ... / PSC_ENABLE ...
 113                 end if; -- PCI_CLOCK ...
 114         end process;
 115
 116         process(PCI_CLOCK)
 117         begin
 118                 if (rising_edge(PCI_CLOCK)) then
 119                         SYNC <= SPC_RDY_IN;
 120                 end if;
 121         end process;
 122
 123 end architecture PAR_SER_CON_DESIGN;