increase memory, change pci id
[raggedstone] / ethernet / source / pci / pci_user_constants.v
1 //////////////////////////////////////////////////////////////////////
2 //// ////
3 //// File name "pci_user_constants.v" ////
4 //// ////
5 //// This file is part of the "PCI bridge" project ////
6 //// http://www.opencores.org/cores/pci/ ////
7 //// ////
8 //// Author(s): ////
9 //// - Miha Dolenc (mihad@opencores.org) ////
10 //// - Tadej Markovic (tadej@opencores.org) ////
11 //// ////
12 //////////////////////////////////////////////////////////////////////
13 //// ////
14 //// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
15 //// ////
16 //// This source file may be used and distributed without ////
17 //// restriction provided that this copyright statement is not ////
18 //// removed from the file and that any derivative work contains ////
19 //// the original copyright notice and the associated disclaimer. ////
20 //// ////
21 //// This source file is free software; you can redistribute it ////
22 //// and/or modify it under the terms of the GNU Lesser General ////
23 //// Public License as published by the Free Software Foundation; ////
24 //// either version 2.1 of the License, or (at your option) any ////
25 //// later version. ////
26 //// ////
27 //// This source is distributed in the hope that it will be ////
28 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
29 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
30 //// PURPOSE. See the GNU Lesser General Public License for more ////
31 //// details. ////
32 //// ////
33 //// You should have received a copy of the GNU Lesser General ////
34 //// Public License along with this source; if not, download it ////
35 //// from http://www.opencores.org/lgpl.shtml ////
36 //// ////
37 //////////////////////////////////////////////////////////////////////
38 //
39 // CVS Revision History
40 //
41 // $Log: pci_user_constants.v,v $
42 // Revision 1.3 2007-03-21 11:53:06 sithglan
43 // enable address translation
44 //
45 // Revision 1.2 2007/03/20 20:56:19 sithglan
46 // changes
47 //
48 // Revision 1.1 2007/03/20 17:50:56 sithglan
49 // add shit
50 //
51 // Revision 1.15 2004/08/19 15:27:34 mihad
52 // Changed minimum pci image size to 256 bytes because
53 // of some PC system problems with size of IO images.
54 //
55 // Revision 1.14 2004/07/07 12:45:01 mihad
56 // Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines.
57 // Enabled value loading from serial EEPROM for all of the above + VendorID and DeviceID registers.
58 //
59 // Revision 1.13 2004/01/24 11:54:18 mihad
60 // Update! SPOCI Implemented!
61 //
62 // Revision 1.12 2003/12/28 09:54:48 fr2201
63 // def_wb_imagex_addr_map defined correctly
64 //
65 // Revision 1.11 2003/12/28 09:20:00 fr2201
66 // Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO)
67 //
68 // Revision 1.10 2003/12/19 11:11:30 mihad
69 // Compact PCI Hot Swap support added.
70 // New testcases added.
71 // Specification updated.
72 // Test application changed to support WB B3 cycles.
73 //
74 // Revision 1.9 2003/08/03 18:05:06 mihad
75 // Added limited WISHBONE B3 support for WISHBONE Slave Unit.
76 // Doesn't support full speed bursts yet.
77 //
78 // Revision 1.8 2003/03/14 15:31:57 mihad
79 // Entered the option to disable no response counter in wb master.
80 //
81 // Revision 1.7 2003/01/27 17:05:50 mihad
82 // Updated.
83 //
84 // Revision 1.6 2003/01/27 16:51:19 mihad
85 // Old files with wrong names removed.
86 //
87 // Revision 1.5 2003/01/21 16:06:56 mihad
88 // Bug fixes, testcases added.
89 //
90 // Revision 1.4 2002/09/30 17:22:45 mihad
91 // Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
92 //
93 // Revision 1.3 2002/08/13 11:03:53 mihad
94 // Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
95 //
96 // Revision 1.2 2002/03/05 11:53:47 mihad
97 // Added some testcases, removed un-needed fifo signals
98 //
99 // Revision 1.1 2002/02/01 14:43:31 mihad
100 // *** empty log message ***
101 //
102 //
103
104 // Fifo implementation defines:
105 // If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.
106 // 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),
107 // then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used
108 // If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations )
109 // If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with
110 // width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
111 // in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
112 // If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
113 // WB_FIFO_RAM_ADDR_LENGTH.
114
115 `define WBW_ADDR_LENGTH 4
116 `define WBR_ADDR_LENGTH 4
117 `define PCIW_ADDR_LENGTH 4
118 `define PCIR_ADDR_LENGTH 4
119
120 `define FPGA
121 `define XILINX
122
123 //`define WB_RAM_DONT_SHARE
124 //`define PCI_RAM_DONT_SHARE
125
126 `ifdef FPGA
127 `ifdef XILINX
128 `define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
129 `define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
130 `define PCI_XILINX_RAMB4
131 `define WB_XILINX_RAMB4
132 //`define PCI_XILINX_DIST_RAM
133 //`define WB_XILINX_DIST_RAM
134 `endif
135 `else
136 `define PCI_FIFO_RAM_ADDR_LENGTH 3 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
137 `define WB_FIFO_RAM_ADDR_LENGTH 4 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
138 // `define WB_ARTISAN_SDP
139 // `define PCI_ARTISAN_SDP
140 // `define PCI_VS_STP
141 // `define WB_VS_STP
142 `endif
143
144 // these two defines allow user to select active high or low output enables on PCI bus signals, depending on
145 // output buffers instantiated. Xilinx FPGAs use active low output enables.
146 `define ACTIVE_LOW_OE
147 //`define ACTIVE_HIGH_OE
148
149 // HOST/GUEST implementation selection - see design document and specification for description of each implementation
150 // only one can be defined at same time
151 //`define HOST
152 `define GUEST
153
154 // if NO_CNF_IMAGE is commented out, then READ-ONLY access to configuration space is ENABLED:
155 // - ENABLED Read-Only access from WISHBONE for GUEST bridges
156 // - ENABLED Read-Only access from PCI for HOST bridges
157 // with defining NO_CNF_IMAGE, one decoder and one multiplexer are saved
158 `define NO_CNF_IMAGE
159
160 // number defined here specifies how many MS bits in PCI address are compared with base address, to decode
161 // accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
162 // allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
163 // you have to define a number of minimum sized image and enlarge others by specifying different address mask.
164 // smaller the number here, faster the decoder operation
165 `define PCI_NUM_OF_DEC_ADDR_LINES 19
166
167 // no. of PCI Target IMAGES
168 // - PCI provides 6 base address registers for image implementation.
169 // PCI_IMAGE1 definition is not required and has no effect, since PCI image 1 is always implemented
170 // If GUEST is defined, PCI Image 0 is also always implemented and is used for configuration space
171 // access.
172 // If HOST is defined and NO_CNF_IMAGE is not, then PCI Image 0 is used for Read Only access to configuration
173 // space. If HOST is defined and NO_CNF_IMAGE is defined, then user can define PCI_IMAGE0 as normal image, and there
174 // is no access to Configuration space possible from PCI bus.
175 // Implementation of all other PCI images is selected by defining PCI_IMAGE2 through PCI_IMAGE5 regardles of HOST
176 // or GUEST implementation.
177 `ifdef HOST
178 `ifdef NO_CNF_IMAGE
179 //`define PCI_IMAGE0
180 `endif
181 `endif
182
183 //`define PCI_IMAGE2
184 //`define PCI_IMAGE3
185 //`define PCI_IMAGE4
186 //`define PCI_IMAGE5
187
188 // initial value for PCI image address masks. Address masks can be defined in enabled state,
189 // to allow device independent software to detect size of image and map base addresses to
190 // memory space. If initial mask for an image is defined as 0, then device independent software
191 // won't detect base address implemented and device dependent software will have to configure
192 // address masks as well as base addresses!
193 // Don't define PCI_AMx to 24'hffff_ff for memory images! Use that just for I/O images.
194 `define PCI_AM0 24'hffff_f0
195 `define PCI_AM1 24'hffff_ff
196 `define PCI_AM2 24'hffff_f0
197 `define PCI_AM3 24'hffff_f0
198 `define PCI_AM4 24'hffff_f0
199 `define PCI_AM5 24'hffff_f0
200
201 // initial value for PCI image maping to MEMORY or IO spaces. If initial define is set to 0,
202 // then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D
203 // Device independent software sets the base addresses acording to MEMORY or IO maping!
204 `define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
205 `define PCI_BA1_MEM_IO 1'b1
206 `define PCI_BA2_MEM_IO 1'b0
207 `define PCI_BA3_MEM_IO 1'b0
208 `define PCI_BA4_MEM_IO 1'b0
209 `define PCI_BA5_MEM_IO 1'b0
210
211 // initial value for PCI translation addresses. The initial values
212 // are set after reset. When ADDR_TRAN_IMPL is defined then then Images
213 // are transleted to this adresses whithout access to pci_ta registers.
214 `define PCI_TA0 24'h0000_0
215 `define PCI_TA1 24'h0000_0
216 `define PCI_TA2 24'h0000_0
217 `define PCI_TA3 24'h0000_0
218 `define PCI_TA4 24'h0000_0
219 `define PCI_TA5 24'h0000_0
220
221 `define PCI_AT_EN0 1'b0
222 `define PCI_AT_EN1 1'b0
223 `define PCI_AT_EN2 1'b0
224 `define PCI_AT_EN3 1'b0
225 `define PCI_AT_EN4 1'b0
226 `define PCI_AT_EN5 1'b0
227
228 // number defined here specifies how many MS bits in WB address are compared with base address, to decode
229 // accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
230 // allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
231 // you have to define a number of minimum sized image and enlarge others by specifying different address mask.
232 // smaller the number here, faster the decoder operation
233 `define WB_NUM_OF_DEC_ADDR_LINES 1
234
235 // no. of WISHBONE Slave IMAGES
236 // WB image 0 is always used for access to configuration space. In case configuration space access is not implemented,
237 // ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
238 // WB Image 1 is always implemented and user doesnt need to specify its definition
239 // WB images' 2 through 5 implementation by defining each one.
240 //`define WB_IMAGE2
241 //`define WB_IMAGE3
242 //`define WB_IMAGE4
243 //`define WB_IMAGE5
244
245 //Address bar register defines the base address for each image.
246 //To asccess bus without Software configuration.
247 `define WB_BA1 20'h0000_0
248 `define WB_BA2 20'h8000_0
249 `define WB_BA3 20'h0000_0
250 `define WB_BA4 20'h0000_0
251 `define WB_BA5 20'h0000_0
252
253 // initial value for WB image maping to MEMORY or IO spaces. If initial define is set to 0,
254 // then IMAGE with that base address points to MEMORY space, othervise it points ti IO space.
255 `define WB_BA1_MEM_IO 1'b0
256 `define WB_BA2_MEM_IO 1'b0
257 `define WB_BA3_MEM_IO 1'b0
258 `define WB_BA4_MEM_IO 1'b0
259 `define WB_BA5_MEM_IO 1'b0
260
261 // initial value for WB image address masks.
262 `define WB_AM1 20'h8000_0
263 `define WB_AM2 20'h8000_0
264 `define WB_AM3 20'h0000_0
265 `define WB_AM4 20'h0000_0
266 `define WB_AM5 20'h0000_0
267
268 // initial value for WB translation addresses. The initial values
269 // are set after reset. When ADDR_TRAN_IMPL is defined then then Images
270 // are transleted to this adresses whithout access to pci_ta registers.
271 `define WB_TA1 20'h0000_0
272 `define WB_TA2 20'h0000_0
273 `define WB_TA3 20'h0000_0
274 `define WB_TA4 20'h0000_0
275 `define WB_TA5 20'h0000_0
276
277 `define WB_AT_EN1 1'b0
278 `define WB_AT_EN2 1'b0
279 `define WB_AT_EN3 1'b0
280 `define WB_AT_EN4 1'b0
281 `define WB_AT_EN5 1'b0
282
283 // If this define is commented out, then address translation will not be implemented.
284 // addresses will pass through bridge unchanged, regardles of address translation enable bits.
285 // Address translation also slows down the decoding
286 //When ADDR_TRAN_IMPL this define is present then adress translation is enabled after reset.
287 `define ADDR_TRAN_IMPL
288
289 // decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
290 // slower decode speed can be used, to provide enough time for address to be decoded.
291 `define WB_DECODE_FAST
292 //`define WB_DECODE_MEDIUM
293 //`define WB_DECODE_SLOW
294
295 // Base address for Configuration space access from WB bus. This value cannot be changed during runtime
296 `define WB_CONFIGURATION_BASE 20'h0000_0
297
298 // Turn registered WISHBONE slave outputs on or off
299 // all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
300 // outputs to internals of the core.
301 //`define REGISTER_WBS_OUTPUTS
302
303 /*-----------------------------------------------------------------------------------------------------------
304 Core speed definition - used for simulation and 66MHz Capable bit value in status register indicating 66MHz
305 capable device
306 -----------------------------------------------------------------------------------------------------------*/
307 `define PCI33
308 //`define PCI66
309
310 /*-----------------------------------------------------------------------------------------------------------
311 [000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
312 Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
313 Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
314 together by application.
315 -----------------------------------------------------------------------------------------------------------*/
316 `define HEADER_VENDOR_ID 16'h4242
317 `define HEADER_DEVICE_ID 16'h2323
318 `define HEADER_REVISION_ID 8'h01
319 `define HEADER_SUBSYS_VENDOR_ID 16'h4242
320 `define HEADER_SUBSYS_ID 16'h2323
321 `define HEADER_MAX_LAT 8'h1a
322 `define HEADER_MIN_GNT 8'h08
323
324 // MAX Retry counter value for WISHBONE Master state-machine
325 // This value is 8-bit because of 8-bit retry counter !!!
326 `define WB_RTY_CNT_MAX 8'hff
327
328 // define the macro below to disable internal retry generation in the wishbone master interface
329 // used when wb master accesses extremly slow devices.
330 `define PCI_WBM_NO_RESPONSE_CNT_DISABLE
331
332 `define PCI_WB_REV_B3
333 //`define PCI_WBS_B3_RTY_DISABLE
334
335 `ifdef GUEST
336 // `define PCI_CPCI_HS_IMPLEMENT
337 // `define PCI_SPOCI
338 `endif
339
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