]> git.zerfleddert.de Git - raggedstone/blob - heartbeat/source/new_pciregs.vhd
projects / raggedstone / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
merge config space
[raggedstone] / heartbeat / source / new_pciregs.vhd
1 --+-------------------------------------------------------------------------------------------------+
2 --| |
3 --| File: pciregs.vhd |
4 --| |
5 --| Project: pci32tlite_oc |
6 --| |
7 --| Description: Registros PCI |
8 --| BAR0 is used externally by decoder. |
9 --| |
10 --| +-----------------------------------------------------------------------+ |
11 --| | PCI CONFIGURATION SPACE REGISTERS | |
12 --| +-----------------------------------------------------------------------+ |
13 --| |
14 --| +-------------------------------------------------------------------+ |
15 --| | REGISTER | adr(7..2) | offset | Byte Enable | Size | |
16 --| +-------------------------------------------------------------------+ |
17 --| | VENDORID | 000000 (r) | 00 | 0/1 | 2 | |
18 --| +-------------------------------------------------------------------+ |
19 --| | DERVICEID | 000000 (r) | 02 | 2/3 | 2 | |
20 --| +-------------------------------------------------------------------+ |
21 --| | CMD | 000001 (r/w) | 04 | 0/1 | 2 | |
22 --| +-------------------------------------------------------------------+ |
23 --| | ST | 000001 (r/w*)| 06 | 2/3 | 2 | |
24 --| +-------------------------------------------------------------------+ |
25 --| | REVISIONID | 000010 (r) | 08 | 0 | 1 | |
26 --| +-------------------------------------------------------------------+ |
27 --| | CLASSCODE | 000010 (r) | 09 | 1/2/3 | 3 | |
28 --| +-------------------------------------------------------------------+ |
29 --| | HEADERTYPE | 000011 (r) | 0E | 2 | 1 | |
30 --| +-------------------------------------------------------------------+ |
31 --| | BAR0 | 000100 (r/w) | 10 | 0/1/2/3 | 4 | |
32 --| +-------------------------------------------------------------------+ |
33 --| | SUBSYSTEMID | 001011 (r) | 2C | 0/1 | 2 | |
34 --| +-------------------------------------------------------------------+ |
35 --| | SUBSYSTEMVID | 001011 (r) | 2E | 0/1 | 2 | |
36 --| +-------------------------------------------------------------------+ |
37 --| | INTLINE | 001111 (r/w) | 3C | 0 | 1 | |
38 --| +-------------------------------------------------------------------+ |
39 --| | INTPIN | 001111 (r) | 3D | 1 | 1 | |
40 --| +-------------------------------------------------------------------+ |
41 --| (w*) Reseteable |
42 --| |
43 --| +-----------------------------------------------+ |
44 --| | VENDORID (r) Vendor ID register | |
45 --| +-----------------------------------------------+-----------------------+ |
46 --| | Identifies manufacturer of device. | |
47 --| | VENDORIDr : vendorID (generic) | |
48 --| +-----------------------------------------------------------------------+ |
49 --| |
50 --| +-----------------------------------------------+ |
51 --| | DEVICEID (r) Device ID register | |
52 --| +-----------------------------------------------+-----------------------+ |
53 --| | Identifies the device. | |
54 --| | DEVICEIDr : deviceID (generic) | |
55 --| +-----------------------------------------------------------------------+ |
56 --| |
57 --| +-----------------------------------------------+ |
58 --| | CMD (r/w) CoMmanD register | |
59 --| +-----------------------------------------------+----------------------------+ |
60 --| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SERRENb| (15-8) |
61 --| +----------------------------------------------------------------------------+ |
62 --| | 0 | PERRENb| 0 | 0 | 0 | 0 |MEMSPACEENb| 0 | (7-0) |
63 --| +----------------------------------------------------------------------------+ |
64 --| | SERRENb : System ERRor ENable (1 = Enabled) | |
65 --| | PERRENb : Parity ERRor ENable (1 = Enabled) | |
66 --| | MEMSPACEENb : MEMmory SPACE ENable (1 = Enabled) | |
67 --| +-----------------------------------------------------------------------+ |
68 --| |
69 --| +-----------------------------------------------+ |
70 --| | ST (r/w*) STatus register | |
71 --| +-----------------------------------------------+-------------------------+ |
72 --| | PERRDTb | SERRSIb| -- | -- |TABORTSIb| DEVSELTIMb(1..0)| -- | (15-8) |
73 --| +-------------------------------------------------------------------------+ |
74 --| | -- | -- | -- | -- | -- | -- | -- | -- | (7-0) |
75 --| +-------------------------------------------------------------------------+ |
76 --| | PERRDTb : Parity ERRor DeTected | |
77 --| | SERRSIb : System ERRor SIgnaled | |
78 --| | TABORTSIb : Target ABORT SIgnaled | |
79 --| +-----------------------------------------------------------------------+ |
80 --| |
81 --| +-----------------------------------------------+ |
82 --| | REVISIONID (r) Revision ID register | |
83 --| +-----------------------------------------------+-----------------------+ |
84 --| | Identifies a device revision. | |
85 --| +-----------------------------------------------------------------------+ |
86 --| +-----------------------------------------------+ |
87 --| | CLASSCODE (r) CLASS CODE register | |
88 --| +-----------------------------------------------+-----------------------+ |
89 --| | Identifies the generic funtion of the device. | |
90 --| +-----------------------------------------------------------------------+ |
91 --| +-----------------------------------------------+ |
92 --| | HEADERTYPE (r) Header Type register | |
93 --| +-----------------------------------------------+-----------------------+ |
94 --| | Identifies the layout of the second part of the predefined header. | |
95 --| +-----------------------------------------------------------------------+ |
96 --| |
97 --| +-----------------------------------------------+ |
98 --| | BAR0 (r/w) Base AddRess 0 register | |
99 --| +-----------------------------------------------+-----------------------+ |
100 --| | BAR032MBb(6..0) | -- | (31-24) |
101 --| +-----------------------------------------------------------------------+ |
102 --| | BAR032MBb : Base Address 32MBytes decode space (7 bits) | |
103 --| +-----------------------------------------------------------------------+ |
104 --| |
105 --| +-----------------------------------------------+ |
106 --| | SUBSYSTEMVID (r) SUBSYSTEM Vendor ID register | |
107 --| +-----------------------------------------------+-----------------------+ |
108 --| | Identifies vendor of add-in board or subsystem. | |
109 --| | SUBSYSTEMVIDr : subsystemvID (generic) | |
110 --| +-----------------------------------------------------------------------+ |
111 --| |
112 --| +-----------------------------------------------+ |
113 --| | SUBSYSTEMID (r) SUBSYSTEM ID register | |
114 --| +-----------------------------------------------+-----------------------+ |
115 --| | Vendor specific. | |
116 --| | SUBSYTEMIDr : subsytemID (generic) | |
117 --| +-----------------------------------------------------------------------+ |
118 --| |
119 --| +-----------------------------------------------+ |
120 --| | INTLINE (r/w) INTerrupt LINE register | |
121 --| +-----------------------------------------------+-----------------------+ |
122 --| | INTLINEr(7..0) | (7..0) |
123 --| +-----------------------------------------------------------------------+ |
124 --| | Interrupt Line routing information | |
125 --| +-----------------------------------------------------------------------+ |
126 --| |
127 --| +-----------------------------------------------+ |
128 --| | INTPIN (r) INTerrupt PIN register | |
129 --| +-----------------------------------------------+-----------------------+ |
130 --| | Tells which interrupt pin the device uses: 01=INTA | |
131 --| +-----------------------------------------------------------------------+ |
132 --| |
133 --+-------------------------------------------------------------------------------------------------+
134 --| |
135 --| Revision history : |
136 --| Date Version Author Description |
137 --| 2005-05-13 R00A00 PAU First alfa revision (eng) |
138 --| |
139 --| To do: |
140 --| |
141 --+-------------------------------------------------------------------------------------------------+
142 --+-----------------------------------------------------------------+
143 --| |
144 --| Copyright (C) 2005 Peio Azkarate, peio@opencores.org |
145 --| |
146 --| This source file may be used and distributed without |
147 --| restriction provided that this copyright statement is not |
148 --| removed from the file and that any derivative work contains |
149 --| the original copyright notice and the associated disclaimer. |
150 --| |
151 --| This source file is free software; you can redistribute it |
152 --| and/or modify it under the terms of the GNU Lesser General |
153 --| Public License as published by the Free Software Foundation; |
154 --| either version 2.1 of the License, or (at your option) any |
155 --| later version. |
156 --| |
157 --| This source is distributed in the hope that it will be |
158 --| useful, but WITHOUT ANY WARRANTY; without even the implied |
159 --| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
160 --| PURPOSE. See the GNU Lesser General Public License for more |
161 --| details. |
162 --| |
163 --| You should have received a copy of the GNU Lesser General |
164 --| Public License along with this source; if not, download it |
165 --| from http://www.opencores.org/lgpl.shtml |
166 --| |
167 --+-----------------------------------------------------------------+
168
169
170 --+-----------------------------------------------------------------------------+
171 --| LIBRARIES |
172 --+-----------------------------------------------------------------------------+
173
174 library ieee;
175 use ieee.std_logic_1164.all;
176
177
178 --+-----------------------------------------------------------------------------+
179 --| ENTITY |
180 --+-----------------------------------------------------------------------------+
181
182 entity pciregs is
183 generic (
184
185 vendorID : std_logic_vector(15 downto 0);
186 deviceID : std_logic_vector(15 downto 0);
187 revisionID : std_logic_vector(7 downto 0);
188 subsystemID : std_logic_vector(15 downto 0);
189 subsystemvID : std_logic_vector(15 downto 0);
190 jcarr1ID : std_logic_vector(31 downto 0);
191 jcarr2ID : std_logic_vector(31 downto 0);
192 jcarr3ID : std_logic_vector(31 downto 0);
193 jcarr4ID : std_logic_vector(31 downto 0);
194 jcarr5ID : std_logic_vector(31 downto 0);
195 jcarr6ID : std_logic_vector(31 downto 0);
196 jcarr7ID : std_logic_vector(31 downto 0);
197 jcarr8ID : std_logic_vector(31 downto 0);
198 jcarr9ID : std_logic_vector(31 downto 0);
199 jcarr10ID : std_logic_vector(31 downto 0);
200 jcarr11ID : std_logic_vector(31 downto 0);
201 jcarr12ID : std_logic_vector(31 downto 0);
202 jcarr13ID : std_logic_vector(31 downto 0);
203 jcarr14ID : std_logic_vector(31 downto 0);
204 jcarr15ID : std_logic_vector(31 downto 0);
205 jcarr16ID : std_logic_vector(31 downto 0);
206 jcarr17ID : std_logic_vector(31 downto 0);
207 jcarr18ID : std_logic_vector(31 downto 0);
208 jcarr19ID : std_logic_vector(31 downto 0);
209 jcarr20ID : std_logic_vector(31 downto 0);
210 jcarr21ID : std_logic_vector(31 downto 0);
211 jcarr22ID : std_logic_vector(31 downto 0);
212 jcarr23ID : std_logic_vector(31 downto 0);
213 jcarr24ID : std_logic_vector(31 downto 0);
214 jcarr25ID : std_logic_vector(31 downto 0);
215 jcarr26ID : std_logic_vector(31 downto 0);
216 jcarr27ID : std_logic_vector(31 downto 0);
217 jcarr28ID : std_logic_vector(31 downto 0);
218 jcarr29ID : std_logic_vector(31 downto 0);
219 jcarr30ID : std_logic_vector(31 downto 0);
220 jcarr31ID : std_logic_vector(31 downto 0);
221 jcarr32ID : std_logic_vector(31 downto 0);
222 jcarr33ID : std_logic_vector(31 downto 0);
223 jcarr34ID : std_logic_vector(31 downto 0);
224 jcarr35ID : std_logic_vector(31 downto 0);
225 jcarr36ID : std_logic_vector(31 downto 0);
226 jcarr37ID : std_logic_vector(31 downto 0);
227 jcarr38ID : std_logic_vector(31 downto 0);
228 jcarr39ID : std_logic_vector(31 downto 0);
229 jcarr40ID : std_logic_vector(31 downto 0);
230 jcarr41ID : std_logic_vector(31 downto 0);
231 jcarr42ID : std_logic_vector(31 downto 0)
232
233 );
234 port (
235
236 -- General
237 clk_i : in std_logic;
238 nrst_i : in std_logic;
239 --
240 adr_i : in std_logic_vector(5 downto 0);
241 cbe_i : in std_logic_vector(3 downto 0);
242 dat_i : in std_logic_vector(31 downto 0);
243 dat_o : out std_logic_vector(31 downto 0);
244 --
245 wrcfg_i : in std_logic;
246 rdcfg_i : in std_logic;
247 perr_i : in std_logic;
248 serr_i : in std_logic;
249 tabort_i : in std_logic;
250 --
251 bar0_o : out std_logic_vector(31 downto 25);
252 perrEN_o : out std_logic;
253 serrEN_o : out std_logic;
254 memEN_o : out std_logic
255
256 );
257 end pciregs;
258
259
260 architecture rtl of pciregs is
261
262
263 --+-----------------------------------------------------------------------------+
264 --| COMPONENTS |
265 --+-----------------------------------------------------------------------------+
266 --+-----------------------------------------------------------------------------+
267 --| CONSTANTS |
268 --+-----------------------------------------------------------------------------+
269
270 constant CLASSCODEr : std_logic_vector(23 downto 0) := X"028000"; -- Bridge-OtherBridgeDevice
271 constant REVISIONIDr : std_logic_vector(7 downto 0) := revisionID; -- PR00=80,PR1=81...
272 constant HEADERTYPEr : std_logic_vector(7 downto 0) := X"00";
273 constant DEVSELTIMb : std_logic_vector(1 downto 0) := b"01"; -- DEVSEL TIMing (bits) medium speed
274 constant VENDORIDr : std_logic_vector(15 downto 0) := vendorID;
275 constant DEVICEIDr : std_logic_vector(15 downto 0) := deviceID;
276 constant SUBSYSTEMIDr : std_logic_vector(15 downto 0) := subsystemID;
277 constant SUBSYSTEMVIDr : std_logic_vector(15 downto 0) := subsystemvID;
278 constant JCARR1IDr : std_logic_vector(31 downto 0) := jcarr1ID;
279 constant JCARR2IDr : std_logic_vector(31 downto 0) := jcarr2ID;
280 constant JCARR3IDr : std_logic_vector(31 downto 0) := jcarr3ID;
281 constant JCARR4IDr : std_logic_vector(31 downto 0) := jcarr4ID;
282 constant JCARR5IDr : std_logic_vector(31 downto 0) := jcarr5ID;
283 constant JCARR6IDr : std_logic_vector(31 downto 0) := jcarr6ID;
284 constant JCARR7IDr : std_logic_vector(31 downto 0) := jcarr7ID;
285 constant JCARR8IDr : std_logic_vector(31 downto 0) := jcarr8ID;
286 constant JCARR9IDr : std_logic_vector(31 downto 0) := jcarr9ID;
287 constant JCARR10IDr : std_logic_vector(31 downto 0) := jcarr10ID;
288 constant JCARR11IDr : std_logic_vector(31 downto 0) := jcarr11ID;
289 constant JCARR12IDr : std_logic_vector(31 downto 0) := jcarr12ID;
290 constant JCARR13IDr : std_logic_vector(31 downto 0) := jcarr13ID;
291 constant JCARR14IDr : std_logic_vector(31 downto 0) := jcarr14ID;
292 constant JCARR15IDr : std_logic_vector(31 downto 0) := jcarr15ID;
293 constant JCARR16IDr : std_logic_vector(31 downto 0) := jcarr16ID;
294 constant JCARR17IDr : std_logic_vector(31 downto 0) := jcarr17ID;
295 constant JCARR18IDr : std_logic_vector(31 downto 0) := jcarr18ID;
296 constant JCARR19IDr : std_logic_vector(31 downto 0) := jcarr19ID;
297 constant JCARR20IDr : std_logic_vector(31 downto 0) := jcarr20ID;
298 constant JCARR21IDr : std_logic_vector(31 downto 0) := jcarr21ID;
299 constant JCARR22IDr : std_logic_vector(31 downto 0) := jcarr22ID;
300 constant JCARR23IDr : std_logic_vector(31 downto 0) := jcarr23ID;
301 constant JCARR24IDr : std_logic_vector(31 downto 0) := jcarr24ID;
302 constant JCARR25IDr : std_logic_vector(31 downto 0) := jcarr25ID;
303 constant JCARR26IDr : std_logic_vector(31 downto 0) := jcarr26ID;
304 constant JCARR27IDr : std_logic_vector(31 downto 0) := jcarr27ID;
305 constant JCARR28IDr : std_logic_vector(31 downto 0) := jcarr28ID;
306 constant JCARR29IDr : std_logic_vector(31 downto 0) := jcarr29ID;
307 constant JCARR30IDr : std_logic_vector(31 downto 0) := jcarr30ID;
308 constant JCARR31IDr : std_logic_vector(31 downto 0) := jcarr31ID;
309 constant JCARR32IDr : std_logic_vector(31 downto 0) := jcarr32ID;
310 constant JCARR33IDr : std_logic_vector(31 downto 0) := jcarr33ID;
311 constant JCARR34IDr : std_logic_vector(31 downto 0) := jcarr34ID;
312 constant JCARR35IDr : std_logic_vector(31 downto 0) := jcarr35ID;
313 constant JCARR36IDr : std_logic_vector(31 downto 0) := jcarr36ID;
314 constant JCARR37IDr : std_logic_vector(31 downto 0) := jcarr37ID;
315 constant JCARR38IDr : std_logic_vector(31 downto 0) := jcarr38ID;
316 constant JCARR39IDr : std_logic_vector(31 downto 0) := jcarr39ID;
317 constant JCARR40IDr : std_logic_vector(31 downto 0) := jcarr40ID;
318 constant JCARR41IDr : std_logic_vector(31 downto 0) := jcarr41ID;
319 constant JCARR42IDr : std_logic_vector(31 downto 0) := jcarr42ID;
320 constant INTPINr : std_logic_vector(7 downto 0) := X"01"; -- INTA#
321
322
323 --+-----------------------------------------------------------------------------+
324 --| SIGNALS |
325 --+-----------------------------------------------------------------------------+
326
327 signal dataout : std_logic_vector(31 downto 0);
328 signal tabortPFS : std_logic;
329 signal serrPFS : std_logic;
330 signal perrPFS : std_logic;
331 signal adrSTCMD : std_logic;
332 signal adrBAR0 : std_logic;
333 signal adrINT : std_logic;
334 signal we0CMD : std_logic;
335 signal we1CMD : std_logic;
336 signal we3ST : std_logic;
337 signal we3BAR0 : std_logic;
338 signal we0INT : std_logic;
339 signal we1INT : std_logic;
340 signal st11SEN : std_logic;
341 signal st11REN : std_logic;
342 signal st14SEN : std_logic;
343 signal st14REN : std_logic;
344 signal st15SEN : std_logic;
345 signal st15REN : std_logic;
346
347
348 --+---------------------------------------------------------+
349 --| CONFIGURATION SPACE REGISTERS |
350 --+---------------------------------------------------------+
351
352 -- INTERRUPT LINE register
353 signal INTLINEr : std_logic_vector(7 downto 0);
354 -- COMMAND register bits
355 signal MEMSPACEENb : std_logic; -- Memory SPACE ENable (bit)
356 signal PERRENb : std_logic; -- Parity ERRor ENable (bit)
357 signal SERRENb : std_logic; -- SERR ENable (bit)
358 -- STATUS register bits
359 --signal DEVSELTIMb : std_logic_vector(1 downto 0); -- DEVSEL TIMing (bits)
360 signal TABORTSIb : std_logic; -- TarGet ABORT SIgnaling (bit)
361 signal SERRSIb : std_logic; -- System ERRor SIgnaling (bit)
362 signal PERRDTb : std_logic; -- Parity ERRor DeTected (bit)
363 -- BAR0 register bits
364 signal BAR032MBb : std_logic_vector(6 downto 0); -- BAR0 32MBytes Space (bits)
365
366
367 component pfs
368 port (
369 clk : in std_logic;
370 a : in std_logic;
371 y : out std_logic
372 );
373
374 end component;
375
376 begin
377
378 --+-------------------------------------------------------------------------+
379 --| Component instances |
380 --+-------------------------------------------------------------------------+
381
382 u1: pfs port map ( clk => clk_i, a => tabort_i, y => tabortPFS );
383 u2: pfs port map ( clk => clk_i, a => serr_i, y => serrPFS );
384 u3: pfs port map ( clk => clk_i, a => perr_i, y => perrPFS );
385
386
387 --+-------------------------------------------------------------------------+
388 --| Registers Address Decoder |
389 --+-------------------------------------------------------------------------+
390
391 adrSTCMD <= '1' when ( adr_i(5 downto 0) = b"000001" ) else '0';
392 adrBAR0 <= '1' when ( adr_i(5 downto 0) = b"000100" ) else '0';
393 adrINT <= '1' when ( adr_i(5 downto 0) = b"001111" ) else '0';
394
395
396 --+-------------------------------------------------------------------------+
397 --| WRITE ENABLE REGISTERS |
398 --+-------------------------------------------------------------------------+
399
400 --+-----------------------------------------+
401 --| Write Enable Registers |
402 --+-----------------------------------------+
403
404 we0CMD <= adrSTCMD and wrcfg_i and (not cbe_i(0));
405 we1CMD <= adrSTCMD and wrcfg_i and (not cbe_i(1));
406 --we2ST <= adrSTCMD and wrcfg_i and (not cbe_i(2));
407 we3ST <= adrSTCMD and wrcfg_i and (not cbe_i(3));
408 --we2BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(2));
409 we3BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(3));
410 we0INT <= adrINT and wrcfg_i and (not cbe_i(0));
411 --we1INT <= adrINT and wrcfg_i and (not cbe_i(1));
412
413 --+-----------------------------------------+
414 --| Set Enable & Reset Enable bits |
415 --+-----------------------------------------+
416 st11SEN <= tabortPFS;
417 st11REN <= we3ST and dat_i(27);
418 st14SEN <= serrPFS;
419 st14REN <= we3ST and dat_i(30);
420 st15SEN <= perrPFS;
421 st15REN <= we3ST and dat_i(31);
422
423
424 --+-------------------------------------------------------------------------+
425 --| WRITE REGISTERS |
426 --+-------------------------------------------------------------------------+
427
428 --+---------------------------------------------------------+
429 --| COMMAND REGISTER Write |
430 --+---------------------------------------------------------+
431
432 REGCMDWR: process( clk_i, nrst_i, we0CMD, we1CMD, dat_i )
433 begin
434
435 if( nrst_i = '0' ) then
436 MEMSPACEENb <= '0';
437 PERRENb <= '0';
438 SERRENb <= '0';
439 elsif( rising_edge( clk_i ) ) then
440
441 -- Byte 0
442 if( we0CMD = '1' ) then
443 MEMSPACEENb <= dat_i(1);
444 PERRENb <= dat_i(6);
445 end if;
446
447 -- Byte 1
448 if( we1CMD = '1' ) then
449 SERRENb <= dat_i(8);
450 end if;
451
452 end if;
453
454 end process REGCMDWR;
455
456
457 --+---------------------------------------------------------+
458 --| STATUS REGISTER WRITE (Reset only) |
459 --+---------------------------------------------------------+
460
461 REGSTWR: process( clk_i, nrst_i, st11SEN, st11REN, st14SEN, st14REN, st15SEN, st15REN )
462 begin
463
464 if( nrst_i = '0' ) then
465 TABORTSIb <= '0';
466 SERRSIb <= '0';
467 PERRDTb <= '0';
468 elsif( rising_edge( clk_i ) ) then
469
470 -- TarGet ABORT SIgnaling bit
471 if( st11SEN = '1' ) then
472 TABORTSIb <= '1';
473 elsif ( st11REN = '1' ) then
474 TABORTSIb <= '0';
475 end if;
476
477 -- System ERRor SIgnaling bit
478 if( st14SEN = '1' ) then
479 SERRSIb <= '1';
480 elsif ( st14REN = '1' ) then
481 SERRSIb <= '0';
482 end if;
483
484 -- Parity ERRor DEtected bit
485 if( st15SEN = '1' ) then
486 PERRDTb <= '1';
487 elsif ( st15REN = '1' ) then
488 PERRDTb <= '0';
489 end if;
490
491 end if;
492
493 end process REGSTWR;
494
495
496 --+---------------------------------------------------------+
497 --| INTERRUPT REGISTER Write |
498 --+---------------------------------------------------------+
499
500 REGINTWR: process( clk_i, nrst_i, we0INT, dat_i )
501 begin
502
503 if( nrst_i = '0' ) then
504 INTLINEr <= ( others => '0' );
505 elsif( rising_edge( clk_i ) ) then
506
507 -- Byte 0
508 if( we0INT = '1' ) then
509 INTLINEr <= dat_i(7 downto 0);
510 end if;
511
512
513 end if;
514
515 end process REGINTWR;
516
517
518 --+---------------------------------------------------------+
519 --| BAR0 32MBytes address space (bits 31-25) |
520 --+---------------------------------------------------------+
521
522 REGBAR0WR: process( clk_i, nrst_i, we3BAR0, dat_i )
523 begin
524
525 if( nrst_i = '0' ) then
526 BAR032MBb <= ( others => '1' );
527 elsif( rising_edge( clk_i ) ) then
528
529 -- Byte 3
530 if( we3BAR0 = '1' ) then
531 BAR032MBb <= dat_i(31 downto 25);
532 end if;
533
534 end if;
535
536 end process REGBAR0WR;
537
538
539 --+-------------------------------------------------------------------------+
540 --| Registers MUX (READ) |
541 --+-------------------------------------------------------------------------+
542 --+-------------------------------------------------------------------------------------------------+
543
544 RRMUX: process( adr_i, PERRDTb, SERRSIb, TABORTSIb, SERRENb, PERRENb, MEMSPACEENb, BAR032MBb,
545 INTLINEr, rdcfg_i )
546 begin
547
548 if ( rdcfg_i = '1' ) then
549
550 case adr_i is
551
552 when b"000000" =>
553 dataout <= DEVICEIDr & VENDORIDr;
554 when b"000001" =>
555 dataout <= PERRDTb & SERRSIb & b"00" & TABORTSIb & DEVSELTIMb & b"000000000" &
556 b"0000000" & SERRENb & b"0" & PERRENb & b"0000" & MEMSPACEENb & b"0";
557 when b"000010" =>
558 dataout <= CLASSCODEr & REVISIONIDr;
559 when b"000100" =>
560 dataout <= BAR032MBb & b"0" & b"00000000" & b"00000000" & b"00000000";
561 when b"001011" =>
562 dataout <= SUBSYSTEMIDr & SUBSYSTEMVIDr;
563 when b"001111" =>
564 dataout <= b"0000000000000000" & INTPINr & INTLINEr;
565 when b"010001" =>
566 dataout <= JCARR1IDr;
567 when b"010010" =>
568 dataout <= JCARR2IDr;
569 when b"010011" =>
570 dataout <= JCARR3IDr;
571 when b"010100" =>
572 dataout <= JCARR4IDr;
573 when b"010101" =>
574 dataout <= JCARR5IDr;
575 when b"010110" =>
576 dataout <= JCARR6IDr;
577 when b"010111" =>
578 dataout <= JCARR7IDr;
579 when b"011000" =>
580 dataout <= JCARR8IDr;
581 when b"011001" =>
582 dataout <= JCARR9IDr;
583 when b"011010" =>
584 dataout <= JCARR10IDr;
585 when b"011011" =>
586 dataout <= JCARR11IDr;
587 when b"011100" =>
588 dataout <= JCARR12IDr;
589 when b"011101" =>
590 dataout <= JCARR13IDr;
591 when b"011110" =>
592 dataout <= JCARR14IDr;
593 when b"011111" =>
594 dataout <= JCARR15IDr;
595 when b"100000" =>
596 dataout <= JCARR16IDr;
597 when b"100001" =>
598 dataout <= JCARR17IDr;
599 when b"100010" =>
600 dataout <= JCARR18IDr;
601 when b"100011" =>
602 dataout <= JCARR19IDr;
603 when b"100100" =>
604 dataout <= JCARR20IDr;
605 when b"100101" =>
606 dataout <= JCARR21IDr;
607 when b"100110" =>
608 dataout <= JCARR22IDr;
609 when b"100111" =>
610 dataout <= JCARR23IDr;
611 when b"101000" =>
612 dataout <= JCARR24IDr;
613 when b"101001" =>
614 dataout <= JCARR25IDr;
615 when b"101010" =>
616 dataout <= JCARR26IDr;
617 when b"101011" =>
618 dataout <= JCARR27IDr;
619 when b"101100" =>
620 dataout <= JCARR28IDr;
621 when b"101101" =>
622 dataout <= JCARR29IDr;
623 when b"101110" =>
624 dataout <= JCARR30IDr;
625 when b"101111" =>
626 dataout <= JCARR31IDr;
627 when b"110000" =>
628 dataout <= JCARR32IDr;
629 when b"110001" =>
630 dataout <= JCARR33IDr;
631 when b"110010" =>
632 dataout <= JCARR34IDr;
633 when b"110011" =>
634 dataout <= JCARR35IDr;
635 when b"110100" =>
636 dataout <= JCARR36IDr;
637 when b"110101" =>
638 dataout <= JCARR37IDr;
639 when b"110110" =>
640 dataout <= JCARR38IDr;
641 when b"110111" =>
642 dataout <= JCARR39IDr;
643 when b"111000" =>
644 dataout <= JCARR40IDr;
645 when b"111001" =>
646 dataout <= JCARR41IDr;
647 when b"111010" =>
648 dataout <= JCARR42IDr;
649 when others =>
650 dataout <= ( others => '0' );
651
652 end case;
653
654 else
655
656 dataout <= ( others => '0' );
657
658 end if;
659
660 end process RRMUX;
661
662 dat_o <= dataout;
663
664
665 --+-------------------------------------------------------------------------+
666 --| BAR0 & COMMAND REGS bits outputs |
667 --+-------------------------------------------------------------------------+
668
669 bar0_o <= BAR032MBb;
670 perrEN_o <= PERRENb;
671 serrEN_o <= SERRENb;
672 memEN_o <= MEMSPACEENb;
673
674
675 end rtl;
Raggedstone-1 projects
Impressum, Datenschutz