first import of dhwk.

[raggedstone] / dhwk / source / FLAG_BUS.vhd

diff --git a/dhwk/source/FLAG_BUS.vhd b/dhwk/source/FLAG_BUS.vhd
new file mode 100644 (file)
index 0000000..c312be7
--- /dev/null
+++ b/dhwk/source/FLAG_BUS.vhd
@@ -0,0 +1,98 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: FLAG_BUS.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity FLAG_BUS is\r
+       port\r
+       (\r
+       PCI_CLOCK       :in             std_logic;\r
+       KONS_1          :in             std_logic;\r
+       FLAG_IN_0       :in             std_logic;\r
+       R_EFn                   :in             std_logic;\r
+       R_HFn                   :in             std_logic;\r
+       R_FFn                   :in             std_logic;\r
+       FLAG_IN_4       :in             std_logic;\r
+       S_EFn                   :in             std_logic;\r
+       S_HFn                   :in             std_logic;\r
+       S_FFn                   :in             std_logic;\r
+       HOLD                    :in             std_logic;\r
+       SYNC_FLAG       :out    std_logic_vector (7 downto 0)\r
+       );      \r
+end entity FLAG_BUS;\r
+\r
+architecture FLAG_BUS_DESIGN of FLAG_BUS is\r
+\r
+\r
+signal FF1_S_EFn       :std_logic;     \r
+signal FF1_S_HFn       :std_logic;\r
+signal FF1_S_FFn       :std_logic;\r
+signal FF1_R_EFn       :std_logic;\r
+signal FF1_R_HFn       :std_logic;\r
+signal FF1_R_FFn       :std_logic;\r
+\r
+signal FF2_S_EFn       :std_logic;     \r
+signal FF2_S_HFn       :std_logic;\r
+signal FF2_S_FFn       :std_logic;\r
+signal FF2_R_EFn       :std_logic;\r
+signal FF2_R_HFn       :std_logic;\r
+signal FF2_R_FFn       :std_logic;\r
+\r
+begin\r
+\r
+\r
+       process (PCI_CLOCK) \r
+       begin \r
+               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then \r
+\r
+               FF1_S_EFn       <=      S_EFn;\r
+               FF1_S_HFn       <=      S_HFn;\r
+               FF1_S_FFn       <=      S_FFn;\r
+               FF1_R_EFn       <=      R_EFn;\r
+               FF1_R_HFn       <=      R_HFn;\r
+               FF1_R_FFn       <=      R_FFn;\r
+\r
+               end if;\r
+       end process;    \r
+\r
+\r
+       process (PCI_CLOCK) \r
+       begin \r
+               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then  \r
+\r
+                       if                      HOLD    =       '0'     then\r
+\r
+                                       FF2_S_EFn       <=      FF1_S_EFn;      \r
+                                       FF2_S_HFn       <=      FF1_S_HFn;\r
+                                       FF2_S_FFn       <=      FF1_S_FFn;\r
+                                       FF2_R_EFn       <=      FF1_R_EFn;\r
+                                       FF2_R_HFn       <=      FF1_R_HFn;\r
+                                       FF2_R_FFn       <=      FF1_R_FFn;\r
+\r
+                               elsif   HOLD    =       '1'     then\r
+\r
+                                       FF2_S_EFn       <=      FF2_S_EFn;      \r
+                                       FF2_S_HFn       <=      FF2_S_HFn;\r
+                                       FF2_S_FFn       <=      FF2_S_FFn;\r
+                                       FF2_R_EFn       <=      FF2_R_EFn;\r
+                                       FF2_R_HFn       <=      FF2_R_HFn;\r
+                                       FF2_R_FFn       <=      FF2_R_FFn;\r
+\r
+                       end if;\r
+               end if;\r
+       end process;    \r
+\r
+       SYNC_FLAG(0)    <=      FLAG_IN_0;              \r
+       SYNC_FLAG(1)    <=      FF2_R_EFn;      \r
+       SYNC_FLAG(2)    <=      FF2_R_HFn;\r
+       SYNC_FLAG(3)    <=      FF2_R_FFn;\r
+       SYNC_FLAG(4)    <=      FLAG_IN_4;              \r
+       SYNC_FLAG(5)    <=      FF2_S_EFn;      \r
+       SYNC_FLAG(6)    <=      FF2_S_HFn;\r
+       SYNC_FLAG(7)    <=      FF2_S_FFn;\r
+\r
+end architecture FLAG_BUS_DESIGN;\r
+\r