typos
[raggedstone] / dhwk_old / source / top_dhwk.vhd
index dbb54e9021612558ff3ab5a72581f03c1399840c..5345dce01936381b9a455d37cfb4def0e0f6b13b 100644 (file)
@@ -1,43 +1,8 @@
---+-------------------------------------------------------------------------------------------------+\r
---|                                                                                                                                                                                                    |\r
---|  File:                     top.vhd                                                                         |\r
---|                                                                                                                                                                                                    |\r
---|  Components:       pci32lite.vhd                                                                   |\r
---|                        pciwbsequ.vhd                                                                                                                       |\r
---|                        pcidmux.vhd                                                                                                                                 |\r
---|                        pciregs.vhd                                                                                                                                 |\r
---|                        pcipargen.vhd                                                                                                                               |\r
---|                        -- Libs --                                                                                                                                  |\r
---|                        ona.vhd                                                                                                                                             |\r
---|                                                                                                                                                                                                    |\r
---|     Description:   RS1 PCI Demo : (TOP) Main file.                                                                                 |\r
---|                                                                                                                                                                                            |\r
---|                                                                                                                                                                            |\r
---|                                                                                                                                                                                                    |\r
---+-------------------------------------------------------------------------------------------------+\r
---|                                                                                                                                                                                                    |\r
---|  Revision history :                                                                                                                                                                |\r
---|  Date                Version       Author  Description                                                                                                             |\r
---|                                                                                                                                                                                                    |\r
---|                                                                                                                                                                                                    |\r
---|  To do:                                                                                                                                                                                    |\r
---|                                                                                                                                                                                                    |\r
---+-------------------------------------------------------------------------------------------------+\r
-\r
-\r
---+-----------------------------------------------------------------------------+\r
---|                                                                    LIBRARIES                                                                       |\r
---+-----------------------------------------------------------------------------+\r
-\r
 library ieee;\r
 use ieee.std_logic_1164.all;\r
 use ieee.std_logic_arith.all;\r
 use ieee.std_logic_unsigned.all;\r
 \r
---+-----------------------------------------------------------------------------+\r
---|                                                                    ENTITY                                                                          |\r
---+-----------------------------------------------------------------------------+\r
-\r
 entity dhwk is\r
 port (\r
 \r
@@ -69,17 +34,9 @@ port (
 end dhwk;\r
 \r
 \r
---+-----------------------------------------------------------------------------+\r
---|                                                                    ARCHITECTURE                                                            |\r
---+-----------------------------------------------------------------------------+\r
-\r
 architecture dhwk_arch of dhwk is\r
 \r
 \r
---+-----------------------------------------------------------------------------+\r
---|                                                                    COMPONENTS                                                                      |\r
---+-----------------------------------------------------------------------------+\r
-\r
 component pci32tlite\r
 port (\r
 \r
@@ -152,32 +109,44 @@ port (
 );\r
 end component;\r
 \r
+component wb_fifo\r
+port (\r
+       clk_i           : in std_logic;\r
+       nrst_i          : in std_logic;\r
+       \r
+       wb_adr_i        : in std_logic_vector(24 downto 1);\r
+       wb_dat_o        : out std_logic_vector(15 downto 0);\r
+       wb_dat_i        : in std_logic_vector(15 downto 0);\r
+       wb_sel_i        : in std_logic_vector(1 downto 0);\r
+       wb_we_i         : in std_logic;\r
+       wb_stb_i        : in std_logic;\r
+       wb_cyc_i        : in std_logic;\r
+       wb_ack_o        : out std_logic;\r
+       wb_err_o        : out std_logic;\r
+       wb_int_o        : out std_logic;\r
+       \r
+       fifo_data_i     : in std_logic_vector(7 downto 0);\r
+       fifo_data_o     : out std_logic_vector(7 downto 0);\r
+\r
+       fifo_we_out     : out std_logic;\r
+       fifo_re_out     : out std_logic\r
+);\r
+end component;\r
 \r
---+-----------------------------------------------------------------------------+\r
---|                                                                    CONSTANTS                                                                       |\r
---+-----------------------------------------------------------------------------+\r
---+-----------------------------------------------------------------------------+\r
---|                                                                    SIGNALS                                                                         |\r
---+-----------------------------------------------------------------------------+\r
-\r
-       signal  wb_adr :                std_logic_vector(24 downto 1);   \r
-       signal  wb_dat_out :    std_logic_vector(15 downto 0);\r
-       signal  wb_dat_in :             std_logic_vector(15 downto 0);\r
-       signal  wb_sel :                std_logic_vector(1 downto 0);\r
-       signal  wb_we :                 std_logic;\r
-       signal  wb_stb :                std_logic;\r
-       signal  wb_cyc :                std_logic;\r
-       signal  wb_ack :                std_logic;\r
-       signal  wb_err :                std_logic;\r
-       signal  wb_int :                std_logic;\r
+signal         wb_adr :                std_logic_vector(24 downto 1);   \r
+signal wb_dat_out :    std_logic_vector(15 downto 0);\r
+signal         wb_dat_in :             std_logic_vector(15 downto 0);\r
+signal wb_sel :                std_logic_vector(1 downto 0);\r
+signal  wb_we :                        std_logic;\r
+signal wb_stb :                std_logic;\r
+signal wb_cyc :                std_logic;\r
+signal wb_ack :                std_logic;\r
+signal wb_err :                std_logic;\r
+signal wb_int :                std_logic;\r
 \r
 \r
 begin\r
 \r
---+-----------------------------------------+\r
---|  PCI Target                                                        |\r
---+-----------------------------------------+\r
-\r
 u_pci: component pci32tlite\r
 port map(\r
        clk33 =>                PCI_CLK,\r
@@ -208,10 +177,6 @@ port map(
 --             debug_access => LED2\r
                );\r
 \r
---+-----------------------------------------+\r
---|  WB-7seg                                                   |\r
---+-----------------------------------------+\r
-\r
 my_heartbeat: component heartbeat\r
 port map( \r
        clk_i => PCI_CLK,\r
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