wb_int_o : out std_logic;\r
\r
fifo_data_i : in std_logic_vector(7 downto 0);\r
- fifo_data_o : out std_logic_vector(7 downto 0)\r
+ fifo_data_o : out std_logic_vector(7 downto 0);\r
\r
fifo_we_out : out std_logic;\r
- fifo_re_out : out std_logic;\r
+ fifo_re_out : out std_logic\r
);\r
end component;\r
\r