dos2unix *.vhd

[raggedstone] / dhwk / source / Verg_4.vhd

diff --git a/dhwk/source/Verg_4.vhd b/dhwk/source/Verg_4.vhd
index 6aafdad19588f8994e3f138db2439a959cf02e4c..e3900cf4e2703a75d638ea7fcf679d72332c6155 100644 (file)
--- a/dhwk/source/Verg_4.vhd
+++ b/dhwk/source/Verg_4.vhd
@@ -1,32 +1,32 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: VERG_4.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-\r
-entity VERG_4 is\r
-       port\r
-       (\r
-       IN_A            :in             std_logic_vector(3 downto 0);\r
-       IN_B            :in             std_logic_vector(3 downto 0);\r
-       GLEICH  :out    std_logic\r
-       );\r
-end entity VERG_4 ;\r
-\r
-architecture VERG_4_DESIGN of VERG_4 is\r
-\r
-begin\r
-\r
-       process (IN_A,IN_B) \r
-       begin \r
-\r
-               if                      IN_A    =       IN_B    then    GLEICH  <=      '1';\r
-                       else                                                                                    GLEICH  <=      '0';   \r
-               end if;\r
-\r
-       end process;\r
-\r
-end architecture VERG_4_DESIGN;\r
-\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_4.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_4 is
+       port
+       (
+       IN_A            :in             std_logic_vector(3 downto 0);
+       IN_B            :in             std_logic_vector(3 downto 0);
+       GLEICH  :out    std_logic
+       );
+end entity VERG_4 ;
+
+architecture VERG_4_DESIGN of VERG_4 is
+
+begin
+
+       process (IN_A,IN_B) 
+       begin 
+
+               if                      IN_A    =       IN_B    then    GLEICH  <=      '1';
+                       else                                                                                    GLEICH  <=      '0';   
+               end if;
+
+       end process;
+
+end architecture VERG_4_DESIGN;
+