Adding a test bench back that isn't a test bench. I shouldn't have deleted in
authorsithglan <sithglan>
Sun, 11 Mar 2007 09:05:56 +0000 (09:05 +0000)
committersithglan <sithglan>
Sun, 11 Mar 2007 09:05:56 +0000 (09:05 +0000)
the first place because all real testbenches were gone by yesterday.

dhwk/dhwk.prj
dhwk/source/pci/mess_tb.vhd [new file with mode: 0644]

index 0429c1815114a3e5f7d433cd7b27532ced9433d7..113fec6997e53a7fddcccee7a6ebbf67c745d5a6 100644 (file)
@@ -23,6 +23,7 @@ vhdl work "source/pci/io_mux.vhd"
 vhdl work "source/pci/io_mux_reg.vhd"
 vhdl work "source/pci/io_reg.vhd"
 vhdl work "source/pci/io_rw_sel.vhd"
+vhdl work "source/pci/mess_tb.vhd"
 vhdl work "source/pci/parity.vhd"
 vhdl work "source/pci/parity_4.vhd"
 vhdl work "source/pci/parity_out.vhd"
diff --git a/dhwk/source/pci/mess_tb.vhd b/dhwk/source/pci/mess_tb.vhd
new file mode 100644 (file)
index 0000000..ec9b512
--- /dev/null
@@ -0,0 +1,33 @@
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 29.08.2006
+-- File: MESS_1_TB.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity MESS_1_TB is
+        port
+        (
+                KONST_1 :in std_logic;
+                PCI_IDSEL :in std_logic;
+                DEVSELn :in std_logic;
+                INTAn :in std_logic;
+                REG_OUT_XX7 :in std_logic_vector(7 downto 0);
+                TB_PCI_IDSEL :out std_logic;
+                TB_DEVSELn :out std_logic;
+                TB_INTAn :out std_logic
+        );
+end entity MESS_1_TB;
+
+architecture MESS_1_TB_DESIGN of MESS_1_TB is
+
+begin
+
+        TB_PCI_IDSEL <= PCI_IDSEL and KONST_1;
+
+        TB_INTAn <= INTAn and KONST_1;
+
+        TB_DEVSELn <= DEVSELn when REG_OUT_XX7(7) = '0' else (not REG_OUT_XX7(6));
+
+end architecture MESS_1_TB_DESIGN;
Impressum, Datenschutz