more infra

diff --git a/dhwk_old/source/wb_fifo.v b/dhwk_old/source/wb_fifo.v
index 5f56b648db4e75f326e303a573f99e099b4a53ed..d79cb577d5388bb560df2e2a07741067d8addfa5 100644 (file)
--- a/dhwk_old/source/wb_fifo.v
+++ b/dhwk_old/source/wb_fifo.v
@@ -18,15 +18,15 @@ module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we
         output fifo_we_o;\r
         output fifo_re_o;\r
 \r
         output fifo_we_o;\r
         output fifo_re_o;\r
 \r

-       reg [15:0]      data_reg;\r
+       reg [15:0] data_reg;\r

 \r
        always @(posedge clk_i or negedge nrst_i)\r
        begin\r
                if (nrst_i == 0)\r
 \r
        always @(posedge clk_i or negedge nrst_i)\r
        begin\r
                if (nrst_i == 0)\r

-                       data_reg <= 16'hABCD;\r
+                       data_reg <= 16'h0000;\r

                else \r
                else \r

-                       if (wb_stb_i && wb_we_i)\r
-                               data_reg <= wb_dat_i;\r
+                        if (wb_stb_i && wb_we_i)\r
+                                data_reg <= wb_dat_i;\r

        end\r
 \r
        assign wb_ack_o = wb_stb_i;\r
        end\r
 \r
        assign wb_ack_o = wb_stb_i;\r