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side by side
(parent:
377c024
)
it synthesizes
author
michael
<michael>
Sat, 10 Mar 2007 11:27:06 +0000
(11:27 +0000)
committer
michael
<michael>
Sat, 10 Mar 2007 11:27:06 +0000
(11:27 +0000)
dhwk/Makefile
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dhwk/source/top.vhd
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diff --git
a/dhwk/Makefile
b/dhwk/Makefile
index 0bf5c9800db4b0a44c50d1639b4fb9cecfbc1090..b3cd515c5b61f6626e0c3232633e7c3acb1f7c00 100644
(file)
--- a/
dhwk/Makefile
+++ b/
dhwk/Makefile
@@
-1,3
+1,3
@@
-PROJECT :=
raggedstone
+PROJECT :=
dhwk
include ../common/Makefile.common
diff --git
a/dhwk/source/top.vhd
b/dhwk/source/top.vhd
index 2dc252a89ec17edbe435d0f46d085a09a05f553e..e0ad093580c50e835a82c53b1a1f1ee3afc3aca4 100644
(file)
--- a/
dhwk/source/top.vhd
+++ b/
dhwk/source/top.vhd
@@
-8,7
+8,7
@@
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
\r
\r
\r
-entity
TOP
is
\r
+entity
dhwk
is
\r
Port ( KONST_1 : In std_logic;
\r
PCI_CBEn : In std_logic_vector (3 downto 0);
\r
PCI_CLOCK : In std_logic;
\r
@@
-51,9
+51,9
@@
entity TOP is
TB_IDSEL : Out std_logic;
\r
TB_nDEVSEL : Out std_logic;
\r
TB_nINTA : Out std_logic );
\r
-end
TOP
;
\r
+end
dhwk
;
\r
\r
-architecture SCHEMATIC of
TOP
is
\r
+architecture SCHEMATIC of
dhwk
is
\r
\r
SIGNAL gnd : std_logic := '0';
\r
SIGNAL vcc : std_logic := '1';
\r
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