dos2unix *.vhd

diff --git a/dhwk/source/COMM_DEC.vhd b/dhwk/source/COMM_DEC.vhd
index d2f423ab23a226fa2dd11f7486528b65ada08243..a82d7a530ac349a99caa23a850481bc78f1a3482 100644 (file)
--- a/dhwk/source/COMM_DEC.vhd
+++ b/dhwk/source/COMM_DEC.vhd
@@ -1,141 +1,141 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: COMM_DEC.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all ;\r
-\r
-entity COMM_DEC is\r
-       port\r
-       (\r
-       PCI_CLOCK               :in             std_logic; \r
-       PCI_RSTn                :in             std_logic; \r
-       MY_ADDR                 :in             std_logic;\r
-       IDSEL_REG               :in             std_logic;\r
-       FRAME_REGn      :in             std_logic;\r
-       IO_SPACE                :in             std_logic;\r
-       AD_REG                  :in             std_logic_vector(31 downto 0);\r
-       CBE_REGn                :in             std_logic_vector( 3 downto 0);\r
-       LAR                                     :out    std_logic;--LOAD_ADDR_REG\r
-       IO_READ                 :out    std_logic;\r
-       IO_WRITE                :out    std_logic;\r
-       CONF_READ               :out    std_logic;\r
-       CONF_WRITE      :out    std_logic;\r
-       SERR_CHECK      :out    std_logic\r
-       );\r
-end entity COMM_DEC ;\r
-\r
-architecture COMM_DEC_DESIGN of COMM_DEC is\r
-\r
-\r
---PCI Bus Commands \r
---C/BE[3..0] Command Type\r
---------------------------------------\r
---     0000            Interrupt Acknowledge\r
---     0001            Special Cycle\r
---     0010            I/O Read\r
---     0011            I/O Write\r
---     0100            Reserved\r
---     0101            Reserved\r
---     0110            Memory Read\r
---     0111            Memory Write\r
---\r
---     1000            Reserved\r
---     1001            Reserved\r
---     1010            Configuration Read\r
---     1011            Configuration Write\r
---     1100            Memory Read Multiple \r
---     1101            Dual Address Cycle\r
---     1110            Memory Read Line\r
---     1111            Memory Write and Invalidate\r
-\r
-\r
---PCI Byte Enable \r
---C/BE[3..0] gueltige Datenbits \r
--------------------------------\r
---     0000            AD 31..0\r
---     1000            AD 23..0\r
---     1100            AD 15..0\r
---     1110            AD  7..0\r
-\r
-       constant        cmd_int_ack                     :std_logic_vector(3 downto 0) := "0000";\r
-       constant        cmd_sp_cyc                      :std_logic_vector(3 downto 0) := "0001";\r
-       constant        cmd_io_read                     :std_logic_vector(3 downto 0) := "0010";\r
-       constant        cmd_io_write            :std_logic_vector(3 downto 0) := "0011";\r
-       constant        cmd_res_4                               :std_logic_vector(3 downto 0) := "0100";\r
-       constant        cmd_res_5                               :std_logic_vector(3 downto 0) := "0101";\r
-       constant        cmd_mem_read            :std_logic_vector(3 downto 0) := "0110";\r
-       constant        cmd_mem_write           :std_logic_vector(3 downto 0) := "0111";\r
-       constant        cmd_res_8                               :std_logic_vector(3 downto 0) := "1000";\r
-       constant        cmd_res_9                               :std_logic_vector(3 downto 0) := "1001";\r
-       constant        cmd_conf_read           :std_logic_vector(3 downto 0) := "1010";\r
-       constant        cmd_conf_write  :std_logic_vector(3 downto 0) := "1011";\r
-       constant        cmd_mem_read_m  :std_logic_vector(3 downto 0) := "1100";\r
-       constant        cmd_du_adr_cyc  :std_logic_vector(3 downto 0) := "1101";\r
-       constant        cmd_mem_read_l  :std_logic_vector(3 downto 0) := "1110";\r
-       constant        cmd_mem_write_i :std_logic_vector(3 downto 0) := "1111";\r
-\r
-       signal          START                                           :std_logic; \r
-       signal          FRAME_REG_REGn  :std_logic; \r
-\r
-       signal          SIG_IO_READ                     :std_logic; \r
-       signal          SIG_IO_WRITE            :std_logic; \r
-       signal          SIG_CONF_READ           :std_logic; \r
-       signal          SIG_CONF_WRITE  :std_logic; \r
-\r
-begin\r
-\r
-       process (PCI_CLOCK, PCI_RSTn) \r
-       begin\r
-               if      PCI_RSTn = '0'  then    FRAME_REG_REGn  <=      '1';    \r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-\r
-                       FRAME_REG_REGn  <=      FRAME_REGn; \r
-\r
-               end if;\r
-       end process;\r
-\r
-\r
-       START                   <= (not FRAME_REGn) and FRAME_REG_REGn; \r
-\r
-\r
-\r
-       SIG_IO_READ             <= '1'  when    START                   = '1'\r
-                                                                                               and             IO_SPACE        = '1'\r
-                                                                                               and             CBE_REGn        = cmd_io_read   \r
-                                                                                               and             MY_ADDR         = '1'\r
-                                                       else '0'; \r
-\r
-\r
-       SIG_IO_WRITE    <= '1'  when    START                   = '1'\r
-                                                                                               and             IO_SPACE        = '1'\r
-                                                                                               and             CBE_REGn        = cmd_io_write\r
-                                                                                               and             MY_ADDR         = '1'\r
-                                                       else '0'; \r
-\r
-\r
-       SIG_CONF_READ   <= '1'  when    START                                                           = '1'\r
-                                                                                               and             AD_REG(1 downto 0)      = "00"\r
-                                                                                               and             CBE_REGn                                                = cmd_conf_read\r
-                                                                                               and             IDSEL_REG                                               = '1'\r
-                                                                                               \r
-                                               else '0'; \r
-\r
-\r
-       SIG_CONF_WRITE  <= '1'  when    START                                                           = '1'\r
-                                                                                                       and             AD_REG(1 downto 0)      = "00"\r
-                                                                                                       and             CBE_REGn                                                = cmd_conf_write\r
-                                                                                                       and             IDSEL_REG                                               = '1'\r
-                                                               else '0'; \r
-\r
-       LAR                     <=      START;\r
-\r
-       SERR_CHECK      <= SIG_IO_READ or SIG_IO_WRITE or SIG_CONF_READ or SIG_CONF_WRITE;       \r
-\r
-       IO_READ         <=      SIG_IO_READ;\r
-       IO_WRITE        <=      SIG_IO_WRITE;    \r
-       CONF_READ         <=    SIG_CONF_READ;  \r
-       CONF_WRITE      <=      SIG_CONF_WRITE;\r
-\r
-end architecture COMM_DEC_DESIGN ;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: COMM_DEC.VHD
+
+library ieee;
+use ieee.std_logic_1164.all ;
+
+entity COMM_DEC is
+       port
+       (
+       PCI_CLOCK               :in             std_logic; 
+       PCI_RSTn                :in             std_logic; 
+       MY_ADDR                 :in             std_logic;
+       IDSEL_REG               :in             std_logic;
+       FRAME_REGn      :in             std_logic;
+       IO_SPACE                :in             std_logic;
+       AD_REG                  :in             std_logic_vector(31 downto 0);
+       CBE_REGn                :in             std_logic_vector( 3 downto 0);
+       LAR                                     :out    std_logic;--LOAD_ADDR_REG
+       IO_READ                 :out    std_logic;
+       IO_WRITE                :out    std_logic;
+       CONF_READ               :out    std_logic;
+       CONF_WRITE      :out    std_logic;
+       SERR_CHECK      :out    std_logic
+       );
+end entity COMM_DEC ;
+
+architecture COMM_DEC_DESIGN of COMM_DEC is
+
+
+--PCI Bus Commands 
+--C/BE[3..0] Command Type
+--------------------------------------
+--     0000            Interrupt Acknowledge
+--     0001            Special Cycle
+--     0010            I/O Read
+--     0011            I/O Write
+--     0100            Reserved
+--     0101            Reserved
+--     0110            Memory Read
+--     0111            Memory Write
+--
+--     1000            Reserved
+--     1001            Reserved
+--     1010            Configuration Read
+--     1011            Configuration Write
+--     1100            Memory Read Multiple 
+--     1101            Dual Address Cycle
+--     1110            Memory Read Line
+--     1111            Memory Write and Invalidate
+
+
+--PCI Byte Enable 
+--C/BE[3..0] gueltige Datenbits 
+-------------------------------
+--     0000            AD 31..0
+--     1000            AD 23..0
+--     1100            AD 15..0
+--     1110            AD  7..0
+
+       constant        cmd_int_ack                     :std_logic_vector(3 downto 0) := "0000";
+       constant        cmd_sp_cyc                      :std_logic_vector(3 downto 0) := "0001";
+       constant        cmd_io_read                     :std_logic_vector(3 downto 0) := "0010";
+       constant        cmd_io_write            :std_logic_vector(3 downto 0) := "0011";
+       constant        cmd_res_4                               :std_logic_vector(3 downto 0) := "0100";
+       constant        cmd_res_5                               :std_logic_vector(3 downto 0) := "0101";
+       constant        cmd_mem_read            :std_logic_vector(3 downto 0) := "0110";
+       constant        cmd_mem_write           :std_logic_vector(3 downto 0) := "0111";
+       constant        cmd_res_8                               :std_logic_vector(3 downto 0) := "1000";
+       constant        cmd_res_9                               :std_logic_vector(3 downto 0) := "1001";
+       constant        cmd_conf_read           :std_logic_vector(3 downto 0) := "1010";
+       constant        cmd_conf_write  :std_logic_vector(3 downto 0) := "1011";
+       constant        cmd_mem_read_m  :std_logic_vector(3 downto 0) := "1100";
+       constant        cmd_du_adr_cyc  :std_logic_vector(3 downto 0) := "1101";
+       constant        cmd_mem_read_l  :std_logic_vector(3 downto 0) := "1110";
+       constant        cmd_mem_write_i :std_logic_vector(3 downto 0) := "1111";
+
+       signal          START                                           :std_logic; 
+       signal          FRAME_REG_REGn  :std_logic; 
+
+       signal          SIG_IO_READ                     :std_logic; 
+       signal          SIG_IO_WRITE            :std_logic; 
+       signal          SIG_CONF_READ           :std_logic; 
+       signal          SIG_CONF_WRITE  :std_logic; 
+
+begin
+
+       process (PCI_CLOCK, PCI_RSTn) 
+       begin
+               if      PCI_RSTn = '0'  then    FRAME_REG_REGn  <=      '1';    
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+                       FRAME_REG_REGn  <=      FRAME_REGn; 
+
+               end if;
+       end process;
+
+
+       START                   <= (not FRAME_REGn) and FRAME_REG_REGn; 
+
+
+
+       SIG_IO_READ             <= '1'  when    START                   = '1'
+                                                                                               and             IO_SPACE        = '1'
+                                                                                               and             CBE_REGn        = cmd_io_read   
+                                                                                               and             MY_ADDR         = '1'
+                                                       else '0'; 
+
+
+       SIG_IO_WRITE    <= '1'  when    START                   = '1'
+                                                                                               and             IO_SPACE        = '1'
+                                                                                               and             CBE_REGn        = cmd_io_write
+                                                                                               and             MY_ADDR         = '1'
+                                                       else '0'; 
+
+
+       SIG_CONF_READ   <= '1'  when    START                                                           = '1'
+                                                                                               and             AD_REG(1 downto 0)      = "00"
+                                                                                               and             CBE_REGn                                                = cmd_conf_read
+                                                                                               and             IDSEL_REG                                               = '1'
+                                                                                               
+                                               else '0'; 
+
+
+       SIG_CONF_WRITE  <= '1'  when    START                                                           = '1'
+                                                                                                       and             AD_REG(1 downto 0)      = "00"
+                                                                                                       and             CBE_REGn                                                = cmd_conf_write
+                                                                                                       and             IDSEL_REG                                               = '1'
+                                                               else '0'; 
+
+       LAR                     <=      START;
+
+       SERR_CHECK      <= SIG_IO_READ or SIG_IO_WRITE or SIG_CONF_READ or SIG_CONF_WRITE;       
+
+       IO_READ         <=      SIG_IO_READ;
+       IO_WRITE        <=      SIG_IO_WRITE;    
+       CONF_READ         <=    SIG_CONF_READ;  
+       CONF_WRITE      <=      SIG_CONF_WRITE;
+
+end architecture COMM_DEC_DESIGN ;

diff --git a/dhwk/source/COMM_FSM.vhd b/dhwk/source/COMM_FSM.vhd
index 158426ef6133096fbd29e68a03bf8fe06ea6cab2..86eca013823eeda16e54efe4a8fc1bea8e658be2 100644 (file)
--- a/dhwk/source/COMM_FSM.vhd
+++ b/dhwk/source/COMM_FSM.vhd
@@ -1,98 +1,98 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: COMM_FSM.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all ;\r
-\r
-entity COMM_FSM is\r
-       port\r
-       (\r
-       PCI_CLOCK               :in             std_logic; \r
-       PCI_RSTn                :in             std_logic; \r
-       IO_READ                 :in             std_logic;\r
-       IO_WRITE                :in             std_logic;\r
-       CONF_READ               :in             std_logic;\r
-       CONF_WRITE      :in             std_logic;\r
-       DEVSELn                 :in             std_logic;      \r
-\r
-       IO_RD_COM       :       out     std_logic;--> MUX_SEL(0)                                                      \r
-       CF_RD_COM       :out    std_logic; \r
-       IO_WR_COM               :out    std_logic;     \r
-       CF_WR_COM               :out    std_logic \r
-       );\r
-end entity COMM_FSM ;\r
-\r
-architecture COMM_FSM_DESIGN of COMM_FSM is\r
-\r
-\r
---**********************************************************\r
---***            COMMAND FSM CODIERUNG                   ***\r
---**********************************************************\r
---\r
---\r
---                                                                        |--------- IO_RD_COM                                                    \r
---                                                                        ||-------- CF_RD_COM   \r
---                                                                                    |||------- IO_WR_COM   \r
---                                                                                ||||------ CF_WR_COM   \r
---                                                                            ||||     \r
-       constant        ST_IDLE_COMM    :std_logic_vector (3 downto 0) := "0000" ;-- \r
-       constant        ST_CONF_WRITE   :std_logic_vector (3 downto 0) := "0001" ;-- \r
-       constant        ST_IO_WRITE             :std_logic_vector (3 downto 0) := "0010" ;-- \r
-       constant        ST_CONF_READ    :std_logic_vector (3 downto 0) := "0100" ;-- \r
-       constant        ST_IO_READ              :std_logic_vector (3 downto 0) := "1000" ;--\r
-\r
-       signal          COMM_STATE              :std_logic_vector (3 downto 0);\r
-\r
---************************************************************\r
---***             FSM SPEICHER-AUTOMAT                     ***\r
---************************************************************\r
-\r
-       attribute syn_state_machine : boolean;\r
-       attribute syn_state_machine of COMM_STATE : signal is false;\r
-\r
-begin\r
-\r
---**********************************************************\r
---***                   COMMAND FSM                        ***\r
---**********************************************************\r
-\r
-       process (PCI_CLOCK, PCI_RSTn) \r
-       begin\r
-               if      PCI_RSTn = '0'  then    COMM_STATE      <= "0000";\r
-\r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
- \r
-                       case COMM_STATE is\r
-       \r
-                               when ST_IDLE_COMM => \r
-                                       if              IO_READ                         = '1' then                                                      COMM_STATE <= ST_IO_READ;\r
-\r
-                               elsif   CONF_READ               = '1' then                                                      COMM_STATE <= ST_CONF_READ; \r
-\r
-                                               elsif   IO_WRITE                = '1' then                                                      COMM_STATE <= ST_IO_WRITE;   \r
-  \r
-                               elsif   CONF_WRITE      = '1' then                                                      COMM_STATE <= ST_CONF_WRITE;     \r
-\r
-                   else                                                                                                                                                COMM_STATE <= ST_IDLE_COMM;\r
-                                       end if;                                                 \r
-       \r
-                               when ST_IO_READ                 => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             \r
-                               when ST_CONF_READ               => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             \r
-                               when ST_IO_WRITE                => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             \r
-                               when ST_CONF_WRITE      => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;\r
-       \r
-                               when others =>                                                                                                                          COMM_STATE <= ST_IDLE_COMM; \r
-\r
-                       end case;               -- COMM_STATE    \r
-               end if;                         -- CLOCK   \r
-       end process;            -- PROCESS\r
-\r
-       IO_RD_COM       <=      COMM_STATE(3);                                                     \r
-       CF_RD_COM       <=      COMM_STATE(2);      \r
-       IO_WR_COM       <=      COMM_STATE(1);      \r
-       CF_WR_COM       <=      COMM_STATE(0);      \r
-       \r
-end architecture COMM_FSM_DESIGN ;\r
-\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: COMM_FSM.VHD
+
+library ieee;
+use ieee.std_logic_1164.all ;
+
+entity COMM_FSM is
+       port
+       (
+       PCI_CLOCK               :in             std_logic; 
+       PCI_RSTn                :in             std_logic; 
+       IO_READ                 :in             std_logic;
+       IO_WRITE                :in             std_logic;
+       CONF_READ               :in             std_logic;
+       CONF_WRITE      :in             std_logic;
+       DEVSELn                 :in             std_logic;      
+
+       IO_RD_COM       :       out     std_logic;--> MUX_SEL(0)                                                      
+       CF_RD_COM       :out    std_logic; 
+       IO_WR_COM               :out    std_logic;     
+       CF_WR_COM               :out    std_logic 
+       );
+end entity COMM_FSM ;
+
+architecture COMM_FSM_DESIGN of COMM_FSM is
+
+
+--**********************************************************
+--***            COMMAND FSM CODIERUNG                   ***
+--**********************************************************
+--
+--
+--                                                                        |--------- IO_RD_COM                                                    
+--                                                                        ||-------- CF_RD_COM   
+--                                                                                    |||------- IO_WR_COM   
+--                                                                                ||||------ CF_WR_COM   
+--                                                                            ||||     
+       constant        ST_IDLE_COMM    :std_logic_vector (3 downto 0) := "0000" ;-- 
+       constant        ST_CONF_WRITE   :std_logic_vector (3 downto 0) := "0001" ;-- 
+       constant        ST_IO_WRITE             :std_logic_vector (3 downto 0) := "0010" ;-- 
+       constant        ST_CONF_READ    :std_logic_vector (3 downto 0) := "0100" ;-- 
+       constant        ST_IO_READ              :std_logic_vector (3 downto 0) := "1000" ;--
+
+       signal          COMM_STATE              :std_logic_vector (3 downto 0);
+
+--************************************************************
+--***             FSM SPEICHER-AUTOMAT                     ***
+--************************************************************
+
+       attribute syn_state_machine : boolean;
+       attribute syn_state_machine of COMM_STATE : signal is false;
+
+begin
+
+--**********************************************************
+--***                   COMMAND FSM                        ***
+--**********************************************************
+
+       process (PCI_CLOCK, PCI_RSTn) 
+       begin
+               if      PCI_RSTn = '0'  then    COMM_STATE      <= "0000";
+
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ 
+                       case COMM_STATE is
+       
+                               when ST_IDLE_COMM => 
+                                       if              IO_READ                         = '1' then                                                      COMM_STATE <= ST_IO_READ;
+
+                               elsif   CONF_READ               = '1' then                                                      COMM_STATE <= ST_CONF_READ; 
+
+                                               elsif   IO_WRITE                = '1' then                                                      COMM_STATE <= ST_IO_WRITE;   
+  
+                               elsif   CONF_WRITE      = '1' then                                                      COMM_STATE <= ST_CONF_WRITE;     
+
+                   else                                                                                                                                                COMM_STATE <= ST_IDLE_COMM;
+                                       end if;                                                 
+       
+                               when ST_IO_READ                 => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             
+                               when ST_CONF_READ               => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             
+                               when ST_IO_WRITE                => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             
+                               when ST_CONF_WRITE      => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;
+       
+                               when others =>                                                                                                                          COMM_STATE <= ST_IDLE_COMM; 
+
+                       end case;               -- COMM_STATE    
+               end if;                         -- CLOCK   
+       end process;            -- PROCESS
+
+       IO_RD_COM       <=      COMM_STATE(3);                                                     
+       CF_RD_COM       <=      COMM_STATE(2);      
+       IO_WR_COM       <=      COMM_STATE(1);      
+       CF_WR_COM       <=      COMM_STATE(0);      
+       
+end architecture COMM_FSM_DESIGN ;
+

diff --git a/dhwk/source/CONT_FSM.vhd b/dhwk/source/CONT_FSM.vhd
index 025c1e7a155f82c85b60b7e8647a3614fba7bd3a..2527c8ad31a0450a8a9cdba9815f674ab951cedb 100644 (file)
--- a/dhwk/source/CONT_FSM.vhd
+++ b/dhwk/source/CONT_FSM.vhd
@@ -1,156 +1,156 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONT_FSM.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all ;\r
-\r
-entity CONT_FSM is\r
-       port\r
-       (\r
-       PCI_CLOCK               :in             std_logic; \r
-       PCI_RSTn                :in             std_logic; \r
-       IO_READ                 :in             std_logic;\r
-       IO_WRITE                :in             std_logic;\r
-       CONF_READ               :in             std_logic;\r
-       CONF_WRITE      :in             std_logic;\r
-       FIFO_READ               :in             std_logic;\r
-       READ                            :out    std_logic;--> MUX_SEL(1) , OE_PCI_AD \r
-       PERR_CHECK      :out    std_logic;              \r
-       DEVSELn                 :out    std_logic;\r
-       OE_PCI_PAR      :out    std_logic;\r
-       OE_PCI_PERR     :out    std_logic;\r
-       TRDYn                           :out    std_logic;\r
-       PCI_TRDYn               :out    std_logic;      --      s/t/s\r
-       PCI_STOPn               :out    std_logic;      --      s/t/s   \r
-       PCI_DEVSELn     :out    std_logic;      --      s/t/s   \r
-       FIFO_RDn                :out    std_logic\r
-       );\r
-end entity CONT_FSM ;\r
-\r
-architecture CONT_FSM_DESIGN of CONT_FSM is\r
-\r
-\r
-\r
---**********************************************************\r
---***              CONTROL FSM CODIERUNG                 ***\r
---**********************************************************\r
---\r
---\r
---\r
---                                                           |----------- HELP\r
---                                                           ||---------- FIFO_READn\r
---                                                           |||--------- OE_PCI_PERR          \r
---                                                                                                      ||||-------- PERR_CHECK  \r
---                                                                                                              |||||------- TRDYn   \r
---                                                                                                                ||||||------ STOPn                                                    \r
---                                                                                                              |||||||----- DEVSELn   \r
---                                                                                        ||||||||---- OE_PCI_PAR   \r
---                                                                                                                                                                                                                              |||||||||--- OE_CONTROL   \r
---                                                                                                                                                                                                                                ||||||||||-- READ / MUX_SEL(1) / OE_PCI_AD \r
---                                                                                                                                                                                                                                      ||||||||||               \r
-       constant        ST_IDLE :std_logic_vector (9 downto 0) := "0100111000" ;-- 138\r
-\r
-       constant        ST_READ_1                       :std_logic_vector (9 downto 0) := "0100110011" ;-- 133\r
-       constant        ST_READ_2                       :std_logic_vector (9 downto 0) := "0100000111" ;-- 107\r
-       constant        ST_READ_3                       :std_logic_vector (9 downto 0) := "0100111111" ;-- 13F\r
-\r
-       constant        ST_RD_FIFO_1    :std_logic_vector (9 downto 0) := "0000110011" ;-- 033\r
-       constant        ST_RD_FIFO_2    :std_logic_vector (9 downto 0) := "1100110011" ;-- 233\r
-\r
-\r
-       constant        ST_WRITE_1              :std_logic_vector (9 downto 0) := "0111110010" ;-- 1F2\r
-       constant        ST_WRITE_2              :std_logic_vector (9 downto 0) := "0110000010" ;-- 182\r
-       constant        ST_WRITE_3              :std_logic_vector (9 downto 0) := "0110111010" ;-- 1BA\r
-\r
-       signal          CONTROL_STATE   :std_logic_vector (9 downto 0);\r
-\r
-\r
---signal               DEVSELn                 :std_logic;\r
-       signal          STOPn                   :std_logic;\r
---signal               TRDYn                   :std_logic;\r
-\r
---************************************************************\r
---***             FSM SPEICHER-AUTOMAT                     ***\r
---************************************************************\r
-\r
-       attribute syn_state_machine : boolean;\r
-       attribute syn_state_machine of CONTROL_STATE : signal is false;\r
-\r
-begin\r
-\r
---**********************************************************\r
---***                  CONTROL FSM                       ***\r
---**********************************************************\r
-\r
-       process (PCI_CLOCK, PCI_RSTn) \r
-       begin\r
-               if      PCI_RSTn = '0'  then    CONTROL_STATE   <= ST_IDLE;\r
-\r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
- \r
-                       case CONTROL_STATE is\r
-       \r
-                               when ST_IDLE => \r
-                                       if                      IO_READ         = '1' then\r
-                                                                                                                       CONTROL_STATE <= ST_READ_1;\r
-\r
-                               elsif   CONF_READ       = '1' then\r
-                                                                                                                       CONTROL_STATE <= ST_READ_1; \r
-\r
-                                               elsif   IO_WRITE        = '1' then\r
-                                                                                                                       CONTROL_STATE <= ST_WRITE_1;   \r
-  \r
-                               elsif   CONF_WRITE      = '1' then\r
-                                                                                                                       CONTROL_STATE <= ST_WRITE_1;\r
-     \r
-                       else                                            CONTROL_STATE <= ST_IDLE;\r
-                                       end if; \r
-\r
---                     when    ST_READ_1               =>      CONTROL_STATE   <=      ST_READ_2;\r
-                               when    ST_READ_1               =>      \r
-                                       if                      FIFO_READ       = '1' then\r
-                                                                                                                       CONTROL_STATE <= ST_RD_FIFO_1;\r
-                                               else                                            CONTROL_STATE <= ST_READ_2;\r
-                                       end if; \r
-\r
-\r
-                               when    ST_READ_2               =>      CONTROL_STATE   <=      ST_READ_3;\r
-                               when    ST_READ_3               =>      CONTROL_STATE   <=      ST_IDLE;\r
-\r
-                               when    ST_RD_FIFO_1=>  CONTROL_STATE   <=      ST_RD_FIFO_2;\r
-                               when    ST_RD_FIFO_2=>  CONTROL_STATE   <=      ST_READ_2;\r
-\r
-\r
-        \r
-                               when    ST_WRITE_1      =>      CONTROL_STATE   <=      ST_WRITE_2;\r
-                               when    ST_WRITE_2      =>      CONTROL_STATE   <=      ST_WRITE_3;\r
-                               when    ST_WRITE_3      =>      CONTROL_STATE   <=      ST_IDLE;\r
-\r
-               \r
-                               when others                             =>      CONTROL_STATE   <=      ST_IDLE; \r
-\r
-                       end case;               -- COMM_STATE    \r
-               end if;                         -- CLOCK   \r
-       end process;                    -- PROCESS\r
-\r
-\r
-       READ                            <=      CONTROL_STATE(0);\r
---OE_CONTROL   <=      CONTROL_STATE(1);\r
-       OE_PCI_PAR      <=      CONTROL_STATE(2);\r
-       DEVSELn                 <=      CONTROL_STATE(3);\r
-       STOPn                           <=      CONTROL_STATE(4);\r
-       TRDYn                           <=      CONTROL_STATE(5);\r
-       PERR_CHECK      <=      CONTROL_STATE(6);\r
-       OE_PCI_PERR     <=      CONTROL_STATE(7);\r
-\r
-       FIFO_RDn                <=      CONTROL_STATE(8);\r
-\r
-\r
-       PCI_DEVSELn     <=      CONTROL_STATE(3)        when    CONTROL_STATE(1) = '1' else 'Z';\r
-       PCI_STOPn       <=      STOPn                                   when    CONTROL_STATE(1) = '1' else 'Z';                                                                      \r
-       PCI_TRDYn         <=    CONTROL_STATE(5)        when    CONTROL_STATE(1) = '1' else 'Z';        \r
-\r
-end architecture CONT_FSM_DESIGN ;\r
-\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONT_FSM.VHD
+
+library ieee;
+use ieee.std_logic_1164.all ;
+
+entity CONT_FSM is
+       port
+       (
+       PCI_CLOCK               :in             std_logic; 
+       PCI_RSTn                :in             std_logic; 
+       IO_READ                 :in             std_logic;
+       IO_WRITE                :in             std_logic;
+       CONF_READ               :in             std_logic;
+       CONF_WRITE      :in             std_logic;
+       FIFO_READ               :in             std_logic;
+       READ                            :out    std_logic;--> MUX_SEL(1) , OE_PCI_AD 
+       PERR_CHECK      :out    std_logic;              
+       DEVSELn                 :out    std_logic;
+       OE_PCI_PAR      :out    std_logic;
+       OE_PCI_PERR     :out    std_logic;
+       TRDYn                           :out    std_logic;
+       PCI_TRDYn               :out    std_logic;      --      s/t/s
+       PCI_STOPn               :out    std_logic;      --      s/t/s   
+       PCI_DEVSELn     :out    std_logic;      --      s/t/s   
+       FIFO_RDn                :out    std_logic
+       );
+end entity CONT_FSM ;
+
+architecture CONT_FSM_DESIGN of CONT_FSM is
+
+
+
+--**********************************************************
+--***              CONTROL FSM CODIERUNG                 ***
+--**********************************************************
+--
+--
+--
+--                                                           |----------- HELP
+--                                                           ||---------- FIFO_READn
+--                                                           |||--------- OE_PCI_PERR          
+--                                                                                                      ||||-------- PERR_CHECK  
+--                                                                                                              |||||------- TRDYn   
+--                                                                                                                ||||||------ STOPn                                                    
+--                                                                                                              |||||||----- DEVSELn   
+--                                                                                        ||||||||---- OE_PCI_PAR   
+--                                                                                                                                                                                                                              |||||||||--- OE_CONTROL   
+--                                                                                                                                                                                                                                ||||||||||-- READ / MUX_SEL(1) / OE_PCI_AD 
+--                                                                                                                                                                                                                                      ||||||||||               
+       constant        ST_IDLE :std_logic_vector (9 downto 0) := "0100111000" ;-- 138
+
+       constant        ST_READ_1                       :std_logic_vector (9 downto 0) := "0100110011" ;-- 133
+       constant        ST_READ_2                       :std_logic_vector (9 downto 0) := "0100000111" ;-- 107
+       constant        ST_READ_3                       :std_logic_vector (9 downto 0) := "0100111111" ;-- 13F
+
+       constant        ST_RD_FIFO_1    :std_logic_vector (9 downto 0) := "0000110011" ;-- 033
+       constant        ST_RD_FIFO_2    :std_logic_vector (9 downto 0) := "1100110011" ;-- 233
+
+
+       constant        ST_WRITE_1              :std_logic_vector (9 downto 0) := "0111110010" ;-- 1F2
+       constant        ST_WRITE_2              :std_logic_vector (9 downto 0) := "0110000010" ;-- 182
+       constant        ST_WRITE_3              :std_logic_vector (9 downto 0) := "0110111010" ;-- 1BA
+
+       signal          CONTROL_STATE   :std_logic_vector (9 downto 0);
+
+
+--signal               DEVSELn                 :std_logic;
+       signal          STOPn                   :std_logic;
+--signal               TRDYn                   :std_logic;
+
+--************************************************************
+--***             FSM SPEICHER-AUTOMAT                     ***
+--************************************************************
+
+       attribute syn_state_machine : boolean;
+       attribute syn_state_machine of CONTROL_STATE : signal is false;
+
+begin
+
+--**********************************************************
+--***                  CONTROL FSM                       ***
+--**********************************************************
+
+       process (PCI_CLOCK, PCI_RSTn) 
+       begin
+               if      PCI_RSTn = '0'  then    CONTROL_STATE   <= ST_IDLE;
+
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+ 
+                       case CONTROL_STATE is
+       
+                               when ST_IDLE => 
+                                       if                      IO_READ         = '1' then
+                                                                                                                       CONTROL_STATE <= ST_READ_1;
+
+                               elsif   CONF_READ       = '1' then
+                                                                                                                       CONTROL_STATE <= ST_READ_1; 
+
+                                               elsif   IO_WRITE        = '1' then
+                                                                                                                       CONTROL_STATE <= ST_WRITE_1;   
+  
+                               elsif   CONF_WRITE      = '1' then
+                                                                                                                       CONTROL_STATE <= ST_WRITE_1;
+     
+                       else                                            CONTROL_STATE <= ST_IDLE;
+                                       end if; 
+
+--                     when    ST_READ_1               =>      CONTROL_STATE   <=      ST_READ_2;
+                               when    ST_READ_1               =>      
+                                       if                      FIFO_READ       = '1' then
+                                                                                                                       CONTROL_STATE <= ST_RD_FIFO_1;
+                                               else                                            CONTROL_STATE <= ST_READ_2;
+                                       end if; 
+
+
+                               when    ST_READ_2               =>      CONTROL_STATE   <=      ST_READ_3;
+                               when    ST_READ_3               =>      CONTROL_STATE   <=      ST_IDLE;
+
+                               when    ST_RD_FIFO_1=>  CONTROL_STATE   <=      ST_RD_FIFO_2;
+                               when    ST_RD_FIFO_2=>  CONTROL_STATE   <=      ST_READ_2;
+
+
+        
+                               when    ST_WRITE_1      =>      CONTROL_STATE   <=      ST_WRITE_2;
+                               when    ST_WRITE_2      =>      CONTROL_STATE   <=      ST_WRITE_3;
+                               when    ST_WRITE_3      =>      CONTROL_STATE   <=      ST_IDLE;
+
+               
+                               when others                             =>      CONTROL_STATE   <=      ST_IDLE; 
+
+                       end case;               -- COMM_STATE    
+               end if;                         -- CLOCK   
+       end process;                    -- PROCESS
+
+
+       READ                            <=      CONTROL_STATE(0);
+--OE_CONTROL   <=      CONTROL_STATE(1);
+       OE_PCI_PAR      <=      CONTROL_STATE(2);
+       DEVSELn                 <=      CONTROL_STATE(3);
+       STOPn                           <=      CONTROL_STATE(4);
+       TRDYn                           <=      CONTROL_STATE(5);
+       PERR_CHECK      <=      CONTROL_STATE(6);
+       OE_PCI_PERR     <=      CONTROL_STATE(7);
+
+       FIFO_RDn                <=      CONTROL_STATE(8);
+
+
+       PCI_DEVSELn     <=      CONTROL_STATE(3)        when    CONTROL_STATE(1) = '1' else 'Z';
+       PCI_STOPn       <=      STOPn                                   when    CONTROL_STATE(1) = '1' else 'Z';                                                                      
+       PCI_TRDYn         <=    CONTROL_STATE(5)        when    CONTROL_STATE(1) = '1' else 'Z';        
+
+end architecture CONT_FSM_DESIGN ;
+

diff --git a/dhwk/source/DATA_MUX.vhd b/dhwk/source/DATA_MUX.vhd
index 46632e2a830c7fac63bc5443146b95af7521e9bf..092f12bdf28c9af8d915318e33acc3253a72bde4 100644 (file)
--- a/dhwk/source/DATA_MUX.vhd
+++ b/dhwk/source/DATA_MUX.vhd
@@ -1,77 +1,77 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: DATA_MUX.VHD\r
-\r
-library ieee ;\r
-use ieee.std_logic_1164.all ;\r
- \r
-entity DATA_MUX is\r
-       port\r
-       (\r
-       READ_SEL                :in             std_logic_vector( 1 downto 0);\r
-       ADDR_REG                :in             std_logic_vector(31 downto 0);\r
-       CBE_REGn                :in             std_logic_vector( 3 downto 0);\r
-       MUX_IN_XX0      :in             std_logic_vector( 7 downto 0);\r
-       MUX_IN_XX1      :in             std_logic_vector( 7 downto 0);\r
-       MUX_IN_XX2      :in             std_logic_vector( 7 downto 0);\r
-       MUX_IN_XX3      :in             std_logic_vector( 7 downto 0);\r
-       MUX_IN_XX4      :in             std_logic_vector( 7 downto 0);\r
-       MUX_IN_XX5      :in             std_logic_vector( 7 downto 0);\r
-       MUX_IN_XX6      :in             std_logic_vector( 7 downto 0);\r
-       MUX_IN_XX7      :in             std_logic_vector( 7 downto 0);\r
-       MUX_OUT                 :out    std_logic_vector(31 downto 0);\r
-       READ_XX1_0      :out    std_logic;      \r
-       READ_XX3_2      :out    std_logic;\r
-       READ_XX5_4      :out    std_logic;\r
-       READ_XX7_6      :out    std_logic\r
---READ_FIFO            :out    std_logic\r
-       );\r
-end entity DATA_MUX ;\r
-\r
-architecture DATA_MUX_DESIGN of DATA_MUX is\r
-\r
-       signal  MUX     :std_logic_vector(31 downto 0);\r
-       signal  SEL     :std_logic_vector( 7 downto 0);\r
-\r
-       signal  SIG_READ_XX1_0  :std_logic;\r
-       signal  SIG_READ_XX3_2  :std_logic;\r
-       signal  SIG_READ_XX5_4  :std_logic;\r
-       signal  SIG_READ_XX7_6  :std_logic;\r
-\r
-begin\r
-\r
-       SEL     <= ADDR_REG(3 downto 2) & CBE_REGn      &       READ_SEL ;      \r
-                                                                                                                                                                                                                                                                               \r
-       SIG_READ_XX1_0  <=      '1' when        SEL     =       "00110011"      else    '0';\r
-       SIG_READ_XX3_2  <=      '1' when        SEL     =       "00001111"      else    '0';\r
-       SIG_READ_XX5_4  <=      '1' when        SEL     =       "01110011"      else    '0';\r
-       SIG_READ_XX7_6  <=      '1' when        SEL     =       "01001111"      else    '0';\r
-\r
-\r
-                                                                       \r
-       MUX     <=      (X"00"                  & X"00"                         & MUX_IN_XX1    &       MUX_IN_XX0)     when    SIG_READ_XX1_0  =       '1' else \r
-                                       (MUX_IN_XX3     &       MUX_IN_XX2  &   X"00"                           & X"00"                 )       when    SIG_READ_XX3_2  =       '1' else                                \r
-                                       (X"00"                  & X"00"                         & MUX_IN_XX5    &       MUX_IN_XX4)     when    SIG_READ_XX5_4  =       '1' else \r
-                                       (MUX_IN_XX7     &       MUX_IN_XX6  &   X"00"                           & X"00"                 )       when    SIG_READ_XX7_6  =       '1' else        \r
-                                       (others => '0');                                                                                                                                                                                                                                                                                                \r
-\r
-\r
---     MUX     <=      (X"01"                  & X"23"                         & MUX_IN_XX1    &       MUX_IN_XX0)     when    SIG_READ_XX1_0  =       '1' else \r
---                                     (MUX_IN_XX3     &       MUX_IN_XX2  &   X"45"                           & X"67"                 )       when    SIG_READ_XX3_2  =       '1' else                                \r
---                                     (X"89"                  & X"AB"                         & MUX_IN_XX5    &       MUX_IN_XX4)     when    SIG_READ_XX5_4  =       '1' else \r
---                                     (MUX_IN_XX7     &       MUX_IN_XX6  &   X"CD"                           & X"EF"                 )       when    SIG_READ_XX7_6  =       '1' else        \r
---                                     (others => '0');                                                                                                                                                                                                                                                                                                \r
-\r
-\r
-       MUX_OUT <= MUX ;\r
-\r
-\r
-       READ_XX1_0      <=      SIG_READ_XX1_0;                 \r
-       READ_XX3_2      <=      SIG_READ_XX3_2;\r
-       READ_XX5_4      <=      SIG_READ_XX5_4;\r
-       READ_XX7_6      <=      SIG_READ_XX7_6;\r
-\r
---READ_FIFO            <=      SIG_READ_XX3_2 or SIG_READ_XX5_4;--SIG_READ_XX5_4 nur fuer test\r
-\r
-end architecture DATA_MUX_DESIGN ;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: DATA_MUX.VHD
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+ 
+entity DATA_MUX is
+       port
+       (
+       READ_SEL                :in             std_logic_vector( 1 downto 0);
+       ADDR_REG                :in             std_logic_vector(31 downto 0);
+       CBE_REGn                :in             std_logic_vector( 3 downto 0);
+       MUX_IN_XX0      :in             std_logic_vector( 7 downto 0);
+       MUX_IN_XX1      :in             std_logic_vector( 7 downto 0);
+       MUX_IN_XX2      :in             std_logic_vector( 7 downto 0);
+       MUX_IN_XX3      :in             std_logic_vector( 7 downto 0);
+       MUX_IN_XX4      :in             std_logic_vector( 7 downto 0);
+       MUX_IN_XX5      :in             std_logic_vector( 7 downto 0);
+       MUX_IN_XX6      :in             std_logic_vector( 7 downto 0);
+       MUX_IN_XX7      :in             std_logic_vector( 7 downto 0);
+       MUX_OUT                 :out    std_logic_vector(31 downto 0);
+       READ_XX1_0      :out    std_logic;      
+       READ_XX3_2      :out    std_logic;
+       READ_XX5_4      :out    std_logic;
+       READ_XX7_6      :out    std_logic
+--READ_FIFO            :out    std_logic
+       );
+end entity DATA_MUX ;
+
+architecture DATA_MUX_DESIGN of DATA_MUX is
+
+       signal  MUX     :std_logic_vector(31 downto 0);
+       signal  SEL     :std_logic_vector( 7 downto 0);
+
+       signal  SIG_READ_XX1_0  :std_logic;
+       signal  SIG_READ_XX3_2  :std_logic;
+       signal  SIG_READ_XX5_4  :std_logic;
+       signal  SIG_READ_XX7_6  :std_logic;
+
+begin
+
+       SEL     <= ADDR_REG(3 downto 2) & CBE_REGn      &       READ_SEL ;      
+                                                                                                                                                                                                                                                                               
+       SIG_READ_XX1_0  <=      '1' when        SEL     =       "00110011"      else    '0';
+       SIG_READ_XX3_2  <=      '1' when        SEL     =       "00001111"      else    '0';
+       SIG_READ_XX5_4  <=      '1' when        SEL     =       "01110011"      else    '0';
+       SIG_READ_XX7_6  <=      '1' when        SEL     =       "01001111"      else    '0';
+
+
+                                                                       
+       MUX     <=      (X"00"                  & X"00"                         & MUX_IN_XX1    &       MUX_IN_XX0)     when    SIG_READ_XX1_0  =       '1' else 
+                                       (MUX_IN_XX3     &       MUX_IN_XX2  &   X"00"                           & X"00"                 )       when    SIG_READ_XX3_2  =       '1' else                                
+                                       (X"00"                  & X"00"                         & MUX_IN_XX5    &       MUX_IN_XX4)     when    SIG_READ_XX5_4  =       '1' else 
+                                       (MUX_IN_XX7     &       MUX_IN_XX6  &   X"00"                           & X"00"                 )       when    SIG_READ_XX7_6  =       '1' else        
+                                       (others => '0');                                                                                                                                                                                                                                                                                                
+
+
+--     MUX     <=      (X"01"                  & X"23"                         & MUX_IN_XX1    &       MUX_IN_XX0)     when    SIG_READ_XX1_0  =       '1' else 
+--                                     (MUX_IN_XX3     &       MUX_IN_XX2  &   X"45"                           & X"67"                 )       when    SIG_READ_XX3_2  =       '1' else                                
+--                                     (X"89"                  & X"AB"                         & MUX_IN_XX5    &       MUX_IN_XX4)     when    SIG_READ_XX5_4  =       '1' else 
+--                                     (MUX_IN_XX7     &       MUX_IN_XX6  &   X"CD"                           & X"EF"                 )       when    SIG_READ_XX7_6  =       '1' else        
+--                                     (others => '0');                                                                                                                                                                                                                                                                                                
+
+
+       MUX_OUT <= MUX ;
+
+
+       READ_XX1_0      <=      SIG_READ_XX1_0;                 
+       READ_XX3_2      <=      SIG_READ_XX3_2;
+       READ_XX5_4      <=      SIG_READ_XX5_4;
+       READ_XX7_6      <=      SIG_READ_XX7_6;
+
+--READ_FIFO            <=      SIG_READ_XX3_2 or SIG_READ_XX5_4;--SIG_READ_XX5_4 nur fuer test
+
+end architecture DATA_MUX_DESIGN ;

diff --git a/dhwk/source/FLAG_BUS.vhd b/dhwk/source/FLAG_BUS.vhd
index dd95bb256fd2d77db99dad61fce58f57f3517293..480f48407ef75ac98422cc9fe05ef220f05379f6 100644 (file)
--- a/dhwk/source/FLAG_BUS.vhd
+++ b/dhwk/source/FLAG_BUS.vhd
@@ -1,98 +1,98 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: FLAG_BUS.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity FLAG_BUS is\r
-       port\r
-       (\r
-       PCI_CLOCK       :in             std_logic;\r
-       KONS_1          :in             std_logic;\r
-       FLAG_IN_0       :in             std_logic;\r
-       R_EFn                   :in             std_logic;\r
-       R_HFn                   :in             std_logic;\r
-       R_FFn                   :in             std_logic;\r
-       FLAG_IN_4       :in             std_logic;\r
-       S_EFn                   :in             std_logic;\r
-       S_HFn                   :in             std_logic;\r
-       S_FFn                   :in             std_logic;\r
-       HOLD                    :in             std_logic;\r
-       SYNC_FLAG       :out    std_logic_vector (7 downto 0)\r
-       );      \r
-end entity FLAG_BUS;\r
-\r
-architecture FLAG_BUS_DESIGN of FLAG_BUS is\r
-\r
-\r
-signal FF1_S_EFn       :std_logic;     \r
-signal FF1_S_HFn       :std_logic;\r
-signal FF1_S_FFn       :std_logic;\r
-signal FF1_R_EFn       :std_logic;\r
-signal FF1_R_HFn       :std_logic;\r
-signal FF1_R_FFn       :std_logic;\r
-\r
-signal FF2_S_EFn       :std_logic;     \r
-signal FF2_S_HFn       :std_logic;\r
-signal FF2_S_FFn       :std_logic;\r
-signal FF2_R_EFn       :std_logic;\r
-signal FF2_R_HFn       :std_logic;\r
-signal FF2_R_FFn       :std_logic;\r
-\r
-begin\r
-\r
-\r
-       process (PCI_CLOCK) \r
-       begin \r
-               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then \r
-\r
-               FF1_S_EFn       <=      not S_EFn;\r
-               FF1_S_HFn       <=      not S_HFn;\r
-               FF1_S_FFn       <=      not S_FFn;\r
-               FF1_R_EFn       <=      not R_EFn;\r
-               FF1_R_HFn       <=      not R_HFn;\r
-               FF1_R_FFn       <=      not R_FFn;\r
-\r
-               end if;\r
-       end process;    \r
-\r
-\r
-       process (PCI_CLOCK) \r
-       begin \r
-               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then  \r
-\r
-                       if                      HOLD    =       '0'     then\r
-\r
-                                       FF2_S_EFn       <=      FF1_S_EFn;      \r
-                                       FF2_S_HFn       <=      FF1_S_HFn;\r
-                                       FF2_S_FFn       <=      FF1_S_FFn;\r
-                                       FF2_R_EFn       <=      FF1_R_EFn;\r
-                                       FF2_R_HFn       <=      FF1_R_HFn;\r
-                                       FF2_R_FFn       <=      FF1_R_FFn;\r
-\r
-                               elsif   HOLD    =       '1'     then\r
-\r
-                                       FF2_S_EFn       <=      FF2_S_EFn;      \r
-                                       FF2_S_HFn       <=      FF2_S_HFn;\r
-                                       FF2_S_FFn       <=      FF2_S_FFn;\r
-                                       FF2_R_EFn       <=      FF2_R_EFn;\r
-                                       FF2_R_HFn       <=      FF2_R_HFn;\r
-                                       FF2_R_FFn       <=      FF2_R_FFn;\r
-\r
-                       end if;\r
-               end if;\r
-       end process;    \r
-\r
-       SYNC_FLAG(0)    <=      FLAG_IN_0;              \r
-       SYNC_FLAG(1)    <=      FF2_R_EFn;      \r
-       SYNC_FLAG(2)    <=      FF2_R_HFn;\r
-       SYNC_FLAG(3)    <=      FF2_R_FFn;\r
-       SYNC_FLAG(4)    <=      FLAG_IN_4;              \r
-       SYNC_FLAG(5)    <=      FF2_S_EFn;      \r
-       SYNC_FLAG(6)    <=      FF2_S_HFn;\r
-       SYNC_FLAG(7)    <=      FF2_S_FFn;\r
-\r
-end architecture FLAG_BUS_DESIGN;\r
-\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: FLAG_BUS.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity FLAG_BUS is
+       port
+       (
+       PCI_CLOCK       :in             std_logic;
+       KONS_1          :in             std_logic;
+       FLAG_IN_0       :in             std_logic;
+       R_EFn                   :in             std_logic;
+       R_HFn                   :in             std_logic;
+       R_FFn                   :in             std_logic;
+       FLAG_IN_4       :in             std_logic;
+       S_EFn                   :in             std_logic;
+       S_HFn                   :in             std_logic;
+       S_FFn                   :in             std_logic;
+       HOLD                    :in             std_logic;
+       SYNC_FLAG       :out    std_logic_vector (7 downto 0)
+       );      
+end entity FLAG_BUS;
+
+architecture FLAG_BUS_DESIGN of FLAG_BUS is
+
+
+signal FF1_S_EFn       :std_logic;     
+signal FF1_S_HFn       :std_logic;
+signal FF1_S_FFn       :std_logic;
+signal FF1_R_EFn       :std_logic;
+signal FF1_R_HFn       :std_logic;
+signal FF1_R_FFn       :std_logic;
+
+signal FF2_S_EFn       :std_logic;     
+signal FF2_S_HFn       :std_logic;
+signal FF2_S_FFn       :std_logic;
+signal FF2_R_EFn       :std_logic;
+signal FF2_R_HFn       :std_logic;
+signal FF2_R_FFn       :std_logic;
+
+begin
+
+
+       process (PCI_CLOCK) 
+       begin 
+               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then 
+
+               FF1_S_EFn       <=      not S_EFn;
+               FF1_S_HFn       <=      not S_HFn;
+               FF1_S_FFn       <=      not S_FFn;
+               FF1_R_EFn       <=      not R_EFn;
+               FF1_R_HFn       <=      not R_HFn;
+               FF1_R_FFn       <=      not R_FFn;
+
+               end if;
+       end process;    
+
+
+       process (PCI_CLOCK) 
+       begin 
+               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then  
+
+                       if                      HOLD    =       '0'     then
+
+                                       FF2_S_EFn       <=      FF1_S_EFn;      
+                                       FF2_S_HFn       <=      FF1_S_HFn;
+                                       FF2_S_FFn       <=      FF1_S_FFn;
+                                       FF2_R_EFn       <=      FF1_R_EFn;
+                                       FF2_R_HFn       <=      FF1_R_HFn;
+                                       FF2_R_FFn       <=      FF1_R_FFn;
+
+                               elsif   HOLD    =       '1'     then
+
+                                       FF2_S_EFn       <=      FF2_S_EFn;      
+                                       FF2_S_HFn       <=      FF2_S_HFn;
+                                       FF2_S_FFn       <=      FF2_S_FFn;
+                                       FF2_R_EFn       <=      FF2_R_EFn;
+                                       FF2_R_HFn       <=      FF2_R_HFn;
+                                       FF2_R_FFn       <=      FF2_R_FFn;
+
+                       end if;
+               end if;
+       end process;    
+
+       SYNC_FLAG(0)    <=      FLAG_IN_0;              
+       SYNC_FLAG(1)    <=      FF2_R_EFn;      
+       SYNC_FLAG(2)    <=      FF2_R_HFn;
+       SYNC_FLAG(3)    <=      FF2_R_FFn;
+       SYNC_FLAG(4)    <=      FLAG_IN_4;              
+       SYNC_FLAG(5)    <=      FF2_S_EFn;      
+       SYNC_FLAG(6)    <=      FF2_S_HFn;
+       SYNC_FLAG(7)    <=      FF2_S_FFn;
+
+end architecture FLAG_BUS_DESIGN;
+

diff --git a/dhwk/source/INTERRUPT.vhd b/dhwk/source/INTERRUPT.vhd
index cba393572b11e86209eef3a04c5a51d9fc0ffe94..04136588e3beff7900a39a150a54cf409077cdda 100644 (file)
--- a/dhwk/source/INTERRUPT.vhd
+++ b/dhwk/source/INTERRUPT.vhd
@@ -1,148 +1,148 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: INTERRUPT.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-\r
-entity INTERRUPT is\r
-       port\r
-       (\r
-       PCI_CLOCK               :in             std_logic;\r
-       PCI_RSTn                :in     std_logic; -- PCI reset is asynchron (low active)\r
-       RESET                           :in     std_logic;\r
-       TAST_SETn               :in     std_logic;\r
-       TAST_RESn               :in     std_logic;\r
-       INT_IN_0                :in             std_logic;\r
-       INT_IN_1                :in             std_logic;\r
-       INT_IN_2                :in             std_logic;\r
-       INT_IN_3                :in             std_logic;\r
-       INT_IN_4                :in             std_logic;\r
-       INT_IN_5                :in             std_logic;\r
-       INT_IN_6                :in             std_logic;\r
-       INT_IN_7                :in             std_logic;\r
-       TRDYn                           :in     std_logic;  -- event 1 after read of Interrupt status register (low active)\r
-       READ_XX5_4      :in     std_logic;      -- event 2 after read of Interrupt status register\r
-       INT_RES                 :in             std_logic_vector(7 downto 0); -- clear selected interrupts\r
-       INT_MASKE               :in             std_logic_vector(7 downto 0);   -- interrupt mask register\r
-       INT_REG                 :out    std_logic_vector(7 downto 0); -- interrupt status register\r
-       INTAn                           :out    std_logic;      -- second interrupt line for PCI analyzer\r
-       PCI_INTAn               :out    std_logic               -- PCI interrupt line \r
-       );\r
-\r
-end entity INTERRUPT;\r
-\r
-architecture INTERRUPT_DESIGN of INTERRUPT is\r
-\r
-       signal  SIG_TAST_Q              :std_logic;\r
-       signal  SIG_TAST_Qn             :std_logic;\r
-\r
-\r
-       signal  SIG_INTA                        :std_logic; \r
-\r
-       signal FF_A                     :std_logic_vector(7 downto 0);\r
-       signal FF_B                     :std_logic_vector(7 downto 0);  \r
-       signal SET                      :std_logic_vector(7 downto 0);  \r
-\r
-       signal  SIG_PROPAGATE_INT :std_logic;\r
-       signal  SIG_PROPAGATE_INT_SECOND :std_logic;\r
-       signal  REG :std_logic_vector(7 downto 0);\r
-\r
-begin\r
-\r
-\r
-\r
-\r
-------------------------------------------------------\r
-       process (PCI_CLOCK) \r
-       begin \r
-               if  (PCI_CLOCK'event and PCI_CLOCK ='1')  then  \r
-\r
-                        -- THIS IS BROKEN (it cycles the interrupt)\r
-                       SIG_TAST_Q              <= not (TAST_SETn and SIG_TAST_Qn);\r
-                       SIG_TAST_Qn             <= not (TAST_RESn and SIG_TAST_Q);\r
-       \r
-               end if;\r
-       end process;    \r
-\r
-------------------------------------------------------\r
-\r
-       process (PCI_CLOCK)\r
-       begin\r
-    if (PCI_RSTn = '0') then\r
-                                       SET <= "00000000";\r
-          FF_A <= "00000000";\r
-          FF_B <= "00000000";\r
-\r
-               elsif(PCI_CLOCK'event   and     PCI_CLOCK       =       '1')    then\r
-               if(RESET = '1') then\r
-                                               SET <= "00000000";\r
-            FF_A       <= "00000000";\r
-            FF_B       <= "00000000";\r
-      else     \r
-\r
-                       FF_A(0) <=                      INT_IN_0 ;  -- Receive FIFO Empty Flag\r
-\r
-                       FF_A(1) <=                      INT_IN_1 ;  -- Send FIFO Half Full\r
-                       FF_A(2) <=                      INT_IN_2 ; \r
-                       FF_A(3) <=                      INT_IN_3 ; \r
-\r
-                       FF_A(4) <=                      INT_IN_4 ; \r
-\r
-                       FF_A(5) <=                      INT_IN_5 ; \r
-                       FF_A(6) <=                      INT_IN_6 ; \r
-                       FF_A(7) <=                      INT_IN_7 ; \r
-\r
-                       FF_B    <= FF_A ;\r
-\r
-                       SET <= FF_A AND not FF_B;\r
-               end if;\r
-               end if;\r
-       end process;\r
-\r
-       process (PCI_CLOCK,PCI_RSTn)\r
-       begin\r
-               if (PCI_RSTn = '0') then\r
-                       REG <= "00000000";\r
-\r
-               elsif(PCI_CLOCK'event   and     PCI_CLOCK       =       '1')    then\r
-                               if(RESET = '1') then\r
-                                       REG <= "00000000";\r
-\r
-               -- elsif(SIG_TAST_Q = '1') then\r
-               --      REG <= "00000000" or SET;\r
-               \r
-\r
-        elsif (TRDYn = '0' AND READ_XX5_4 = '1') then\r
-            REG <= (REG AND NOT INT_RES) OR SET;\r
-        else\r
-            REG <= REG OR SET;\r
-        end if;\r
-    end if;\r
-       end process;\r
-\r
-       SIG_PROPAGATE_INT <=\r
-            (REG(0) AND INT_MASKE(0)) \r
-            OR (REG(1) AND INT_MASKE(1))\r
-            OR (REG(2) AND INT_MASKE(2))\r
-            OR (REG(3) AND INT_MASKE(3))\r
-            OR (REG(4) AND INT_MASKE(4))\r
-            OR (REG(5) AND INT_MASKE(5))\r
-            OR (REG(6) AND INT_MASKE(6))\r
-            OR (REG(7) AND INT_MASKE(7));\r
-\r
-       process (PCI_CLOCK)\r
-       begin\r
-               if(PCI_CLOCK'event      and     PCI_CLOCK       =       '1')    then\r
-       SIG_PROPAGATE_INT_SECOND        <= not SIG_PROPAGATE_INT;\r
-    end if;\r
-  end process;\r
-\r
-\r
-         INTAn <= not SIG_PROPAGATE_INT_SECOND;\r
-       PCI_INTAn       <= '0'  when SIG_PROPAGATE_INT_SECOND = '0'     else    'Z';\r
-\r
-       INT_REG <= REG;\r
-\r
-end architecture INTERRUPT_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: INTERRUPT.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity INTERRUPT is
+       port
+       (
+       PCI_CLOCK               :in             std_logic;
+       PCI_RSTn                :in     std_logic; -- PCI reset is asynchron (low active)
+       RESET                           :in     std_logic;
+       TAST_SETn               :in     std_logic;
+       TAST_RESn               :in     std_logic;
+       INT_IN_0                :in             std_logic;
+       INT_IN_1                :in             std_logic;
+       INT_IN_2                :in             std_logic;
+       INT_IN_3                :in             std_logic;
+       INT_IN_4                :in             std_logic;
+       INT_IN_5                :in             std_logic;
+       INT_IN_6                :in             std_logic;
+       INT_IN_7                :in             std_logic;
+       TRDYn                           :in     std_logic;  -- event 1 after read of Interrupt status register (low active)
+       READ_XX5_4      :in     std_logic;      -- event 2 after read of Interrupt status register
+       INT_RES                 :in             std_logic_vector(7 downto 0); -- clear selected interrupts
+       INT_MASKE               :in             std_logic_vector(7 downto 0);   -- interrupt mask register
+       INT_REG                 :out    std_logic_vector(7 downto 0); -- interrupt status register
+       INTAn                           :out    std_logic;      -- second interrupt line for PCI analyzer
+       PCI_INTAn               :out    std_logic               -- PCI interrupt line 
+       );
+
+end entity INTERRUPT;
+
+architecture INTERRUPT_DESIGN of INTERRUPT is
+
+       signal  SIG_TAST_Q              :std_logic;
+       signal  SIG_TAST_Qn             :std_logic;
+
+
+       signal  SIG_INTA                        :std_logic; 
+
+       signal FF_A                     :std_logic_vector(7 downto 0);
+       signal FF_B                     :std_logic_vector(7 downto 0);  
+       signal SET                      :std_logic_vector(7 downto 0);  
+
+       signal  SIG_PROPAGATE_INT :std_logic;
+       signal  SIG_PROPAGATE_INT_SECOND :std_logic;
+       signal  REG :std_logic_vector(7 downto 0);
+
+begin
+
+
+
+
+------------------------------------------------------
+       process (PCI_CLOCK) 
+       begin 
+               if  (PCI_CLOCK'event and PCI_CLOCK ='1')  then  
+
+                        -- THIS IS BROKEN (it cycles the interrupt)
+                       SIG_TAST_Q              <= not (TAST_SETn and SIG_TAST_Qn);
+                       SIG_TAST_Qn             <= not (TAST_RESn and SIG_TAST_Q);
+       
+               end if;
+       end process;    
+
+------------------------------------------------------
+
+       process (PCI_CLOCK)
+       begin
+    if (PCI_RSTn = '0') then
+                                       SET <= "00000000";
+          FF_A <= "00000000";
+          FF_B <= "00000000";
+
+               elsif(PCI_CLOCK'event   and     PCI_CLOCK       =       '1')    then
+               if(RESET = '1') then
+                                               SET <= "00000000";
+            FF_A       <= "00000000";
+            FF_B       <= "00000000";
+      else     
+
+                       FF_A(0) <=                      INT_IN_0 ;  -- Receive FIFO Empty Flag
+
+                       FF_A(1) <=                      INT_IN_1 ;  -- Send FIFO Half Full
+                       FF_A(2) <=                      INT_IN_2 ; 
+                       FF_A(3) <=                      INT_IN_3 ; 
+
+                       FF_A(4) <=                      INT_IN_4 ; 
+
+                       FF_A(5) <=                      INT_IN_5 ; 
+                       FF_A(6) <=                      INT_IN_6 ; 
+                       FF_A(7) <=                      INT_IN_7 ; 
+
+                       FF_B    <= FF_A ;
+
+                       SET <= FF_A AND not FF_B;
+               end if;
+               end if;
+       end process;
+
+       process (PCI_CLOCK,PCI_RSTn)
+       begin
+               if (PCI_RSTn = '0') then
+                       REG <= "00000000";
+
+               elsif(PCI_CLOCK'event   and     PCI_CLOCK       =       '1')    then
+                               if(RESET = '1') then
+                                       REG <= "00000000";
+
+               -- elsif(SIG_TAST_Q = '1') then
+               --      REG <= "00000000" or SET;
+               
+
+        elsif (TRDYn = '0' AND READ_XX5_4 = '1') then
+            REG <= (REG AND NOT INT_RES) OR SET;
+        else
+            REG <= REG OR SET;
+        end if;
+    end if;
+       end process;
+
+       SIG_PROPAGATE_INT <=
+            (REG(0) AND INT_MASKE(0)) 
+            OR (REG(1) AND INT_MASKE(1))
+            OR (REG(2) AND INT_MASKE(2))
+            OR (REG(3) AND INT_MASKE(3))
+            OR (REG(4) AND INT_MASKE(4))
+            OR (REG(5) AND INT_MASKE(5))
+            OR (REG(6) AND INT_MASKE(6))
+            OR (REG(7) AND INT_MASKE(7));
+
+       process (PCI_CLOCK)
+       begin
+               if(PCI_CLOCK'event      and     PCI_CLOCK       =       '1')    then
+       SIG_PROPAGATE_INT_SECOND        <= not SIG_PROPAGATE_INT;
+    end if;
+  end process;
+
+
+         INTAn <= not SIG_PROPAGATE_INT_SECOND;
+       PCI_INTAn       <= '0'  when SIG_PROPAGATE_INT_SECOND = '0'     else    'Z';
+
+       INT_REG <= REG;
+
+end architecture INTERRUPT_DESIGN;

diff --git a/dhwk/source/IO_RW_SEL.vhd b/dhwk/source/IO_RW_SEL.vhd
index 44419d8b181a5b63832fb4a90489a1276b202da8..283e4030d611d1fe0b70eef2231456a8adf951f1 100644 (file)
--- a/dhwk/source/IO_RW_SEL.vhd
+++ b/dhwk/source/IO_RW_SEL.vhd
@@ -1,54 +1,54 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_WR_SEL.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity IO_WR_SEL is\r
-       port\r
-       (\r
-       IO_WR_COM               :in             std_logic;\r
-       IRDY_REGn               :in             std_logic;\r
-       TRDYn                           :in             std_logic;\r
-       ADDR_REG                :in             std_logic_vector(31 downto 0);\r
-       CBE_REGn                :in             std_logic_vector( 3 downto 0);\r
-       WRITE_XX1_0     :out    std_logic;\r
-       WRITE_XX3_2     :out    std_logic;\r
-       WRITE_XX5_4     :out    std_logic;\r
-       WRITE_XX7_6     :out    std_logic \r
-       );\r
-end entity IO_WR_SEL;\r
-\r
---PCI Byte Enable \r
---C/BE[3..0] gueltige Datenbits \r
--------------------------------\r
---     0000            AD 31..0\r
---     1000            AD 23..0\r
---     1100            AD 15..0\r
---     1110            AD  7..0\r
---     0011            AD 31..16\r
-\r
-architecture IO_WR_SEL_DESIGN of IO_WR_SEL is\r
-\r
-       signal  WR_ENA  :std_logic;\r
-       signal  ADDR            :std_logic_vector( 5 downto 0); \r
-\r
-begin\r
-\r
-               WR_ENA  <=      '1' when\r
-                                                                               IO_WR_COM = '1' and\r
-                                                                               IRDY_REGn       =       '0' and\r
-                                                                               TRDYn                   =       '0'     else    '0';\r
-\r
-\r
-               ADDR    <=       ADDR_REG(3) &  ADDR_REG(2)     &       CBE_REGn;\r
-\r
-\r
-               WRITE_XX1_0     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "001100"        else '0';        \r
-               WRITE_XX3_2     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "000011"        else '0';\r
-               WRITE_XX5_4     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "011100"        else '0';        \r
-               WRITE_XX7_6     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "010011"        else '0';\r
-       \r
-end architecture IO_WR_SEL_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_WR_SEL.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity IO_WR_SEL is
+       port
+       (
+       IO_WR_COM               :in             std_logic;
+       IRDY_REGn               :in             std_logic;
+       TRDYn                           :in             std_logic;
+       ADDR_REG                :in             std_logic_vector(31 downto 0);
+       CBE_REGn                :in             std_logic_vector( 3 downto 0);
+       WRITE_XX1_0     :out    std_logic;
+       WRITE_XX3_2     :out    std_logic;
+       WRITE_XX5_4     :out    std_logic;
+       WRITE_XX7_6     :out    std_logic 
+       );
+end entity IO_WR_SEL;
+
+--PCI Byte Enable 
+--C/BE[3..0] gueltige Datenbits 
+-------------------------------
+--     0000            AD 31..0
+--     1000            AD 23..0
+--     1100            AD 15..0
+--     1110            AD  7..0
+--     0011            AD 31..16
+
+architecture IO_WR_SEL_DESIGN of IO_WR_SEL is
+
+       signal  WR_ENA  :std_logic;
+       signal  ADDR            :std_logic_vector( 5 downto 0); 
+
+begin
+
+               WR_ENA  <=      '1' when
+                                                                               IO_WR_COM = '1' and
+                                                                               IRDY_REGn       =       '0' and
+                                                                               TRDYn                   =       '0'     else    '0';
+
+
+               ADDR    <=       ADDR_REG(3) &  ADDR_REG(2)     &       CBE_REGn;
+
+
+               WRITE_XX1_0     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "001100"        else '0';        
+               WRITE_XX3_2     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "000011"        else '0';
+               WRITE_XX5_4     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "011100"        else '0';        
+               WRITE_XX7_6     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "010011"        else '0';
+       
+end architecture IO_WR_SEL_DESIGN;

diff --git a/dhwk/source/Io_mux.vhd b/dhwk/source/Io_mux.vhd
index ba27f4a4395565b5dd89faf75f4fcc48a3742649..5c9537d508cca619a97dd32244a9802d06b602a3 100644 (file)
--- a/dhwk/source/Io_mux.vhd
+++ b/dhwk/source/Io_mux.vhd
@@ -1,36 +1,36 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: IO_MUX.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity IO_MUX is\r
-       port\r
-       (\r
-       READ_SEL                        :in             std_logic_vector ( 1 downto 0);\r
-       USER_DATA                       :in             std_logic_vector (31 downto 0);\r
-       CONFIG_DATA             :in             std_logic_vector (31 downto 0);\r
-       PCI_AD                          :in             std_logic_vector (31 downto 0);\r
-       IO_DATA                         :out    std_logic_vector (31 downto 0)\r
-       );\r
-end entity IO_MUX;\r
-\r
-architecture IO_MUX_DESIGN of IO_MUX is\r
-\r
-       signal  MUX             :std_logic_vector (31 downto 0); \r
-\r
-begin \r
-\r
-       MUX     <=      PCI_AD                  when    READ_SEL        =       "00"    else    -- WRITE_CONFIG \r
-                                       PCI_AD                  when    READ_SEL        =       "01"    else    -- WRITE_IO\r
-                                       CONFIG_DATA     when    READ_SEL        =       "10"    else    -- READ_CONFIG \r
-                                       USER_DATA               when    READ_SEL        =       "11"    else    -- READ_IO      \r
-                                       CONFIG_DATA;\r
-\r
---                                     MUX;\r
-\r
-       IO_DATA <= MUX;\r
-\r
-end architecture IO_MUX_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: IO_MUX.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity IO_MUX is
+       port
+       (
+       READ_SEL                        :in             std_logic_vector ( 1 downto 0);
+       USER_DATA                       :in             std_logic_vector (31 downto 0);
+       CONFIG_DATA             :in             std_logic_vector (31 downto 0);
+       PCI_AD                          :in             std_logic_vector (31 downto 0);
+       IO_DATA                         :out    std_logic_vector (31 downto 0)
+       );
+end entity IO_MUX;
+
+architecture IO_MUX_DESIGN of IO_MUX is
+
+       signal  MUX             :std_logic_vector (31 downto 0); 
+
+begin 
+
+       MUX     <=      PCI_AD                  when    READ_SEL        =       "00"    else    -- WRITE_CONFIG 
+                                       PCI_AD                  when    READ_SEL        =       "01"    else    -- WRITE_IO
+                                       CONFIG_DATA     when    READ_SEL        =       "10"    else    -- READ_CONFIG 
+                                       USER_DATA               when    READ_SEL        =       "11"    else    -- READ_IO      
+                                       CONFIG_DATA;
+
+--                                     MUX;
+
+       IO_DATA <= MUX;
+
+end architecture IO_MUX_DESIGN;

diff --git a/dhwk/source/Io_reg.vhd b/dhwk/source/Io_reg.vhd
index f56df31169a6910ee33ee1f3aa217ddbd27b772f..8b50c2e7543159cf4bf8440f6743579475813fdf 100644 (file)
--- a/dhwk/source/Io_reg.vhd
+++ b/dhwk/source/Io_reg.vhd
@@ -1,74 +1,74 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: IO_MUX.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-\r
-entity IO_REG is\r
-    port\r
-       (\r
-       PCI_CLOCK               :in             std_logic;\r
-       PCI_RSTn                :in             std_logic;\r
-       PCI_FRAMEn      :in             std_logic;\r
-       PCI_IRDYn               :in             std_logic;\r
-       PCI_IDSEL               :in             std_logic;\r
-       PCI_PAR                 :in             std_logic;\r
-       PCI_CBEn                :in             std_logic_vector ( 3 downto 0);\r
-       OE_PCI_AD               :in             std_logic;\r
-       IO_DATA                 :in             std_logic_vector (31 downto 0);\r
-       AD_REG                  :out    std_logic_vector (31 downto 0);\r
-       CBE_REGn                :out    std_logic_vector ( 3 downto 0);\r
-       FRAME_REGn      :out    std_logic;      \r
-       IRDY_REGn               :out    std_logic;      \r
-       IDSEL_REG               :out    std_logic;\r
-       PAR_REG                 :out    std_logic;              \r
-       PCI_AD                  :out    std_logic_vector (31 downto 0)  --      t/s\r
-    );\r
-end entity IO_REG;\r
-\r
-architecture IO_REG_DESIGN of IO_REG is\r
-\r
-       signal  REG_AD                  :std_logic_vector (31 downto 0); \r
-       signal  REG_CBEn                :std_logic_vector ( 3 downto 0);\r
-       signal  REG_FRAMEn      :std_logic;\r
-       signal  REG_IRDYn               :std_logic;\r
-       signal  REG_IDSEL               :std_logic;\r
-       signal  REG_PAR                 :std_logic;\r
-\r
-begin \r
-\r
-       process (PCI_CLOCK, PCI_RSTn) \r
-       begin\r
-               if      PCI_RSTn = '0'  then\r
-\r
-                       REG_AD                  <= X"00000000";\r
-                       REG_CBEn                <= "0000";\r
-                       REG_FRAMEn      <= '1';\r
-                       REG_IRDYn               <= '1';\r
-                       REG_IDSEL               <= '0';\r
-                       REG_PAR                 <= '0';\r
-\r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-\r
-                       REG_AD                  <=      IO_DATA;\r
-                       REG_CBEn                <=      PCI_CBEn;\r
-                       REG_FRAMEn      <=      PCI_FRAMEn;\r
-                       REG_IRDYn               <=      PCI_IRDYn;\r
-                       REG_IDSEL               <=      PCI_IDSEL;\r
-                       REG_PAR                 <=      PCI_PAR;\r
-\r
-               end if;\r
-       end process;\r
-\r
-       PCI_AD                  <=      REG_AD when OE_PCI_AD ='1' else (others => 'Z');\r
-\r
-       AD_REG                  <=      REG_AD;\r
-       CBE_REGn                <=      REG_CBEn;\r
-       FRAME_REGn      <=      REG_FRAMEn;\r
-       IRDY_REGn               <=      REG_IRDYn;\r
-       IDSEL_REG               <=      REG_IDSEL;\r
-       PAR_REG                 <=      REG_PAR;\r
-\r
-end architecture IO_REG_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: IO_MUX.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity IO_REG is
+    port
+       (
+       PCI_CLOCK               :in             std_logic;
+       PCI_RSTn                :in             std_logic;
+       PCI_FRAMEn      :in             std_logic;
+       PCI_IRDYn               :in             std_logic;
+       PCI_IDSEL               :in             std_logic;
+       PCI_PAR                 :in             std_logic;
+       PCI_CBEn                :in             std_logic_vector ( 3 downto 0);
+       OE_PCI_AD               :in             std_logic;
+       IO_DATA                 :in             std_logic_vector (31 downto 0);
+       AD_REG                  :out    std_logic_vector (31 downto 0);
+       CBE_REGn                :out    std_logic_vector ( 3 downto 0);
+       FRAME_REGn      :out    std_logic;      
+       IRDY_REGn               :out    std_logic;      
+       IDSEL_REG               :out    std_logic;
+       PAR_REG                 :out    std_logic;              
+       PCI_AD                  :out    std_logic_vector (31 downto 0)  --      t/s
+    );
+end entity IO_REG;
+
+architecture IO_REG_DESIGN of IO_REG is
+
+       signal  REG_AD                  :std_logic_vector (31 downto 0); 
+       signal  REG_CBEn                :std_logic_vector ( 3 downto 0);
+       signal  REG_FRAMEn      :std_logic;
+       signal  REG_IRDYn               :std_logic;
+       signal  REG_IDSEL               :std_logic;
+       signal  REG_PAR                 :std_logic;
+
+begin 
+
+       process (PCI_CLOCK, PCI_RSTn) 
+       begin
+               if      PCI_RSTn = '0'  then
+
+                       REG_AD                  <= X"00000000";
+                       REG_CBEn                <= "0000";
+                       REG_FRAMEn      <= '1';
+                       REG_IRDYn               <= '1';
+                       REG_IDSEL               <= '0';
+                       REG_PAR                 <= '0';
+
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+                       REG_AD                  <=      IO_DATA;
+                       REG_CBEn                <=      PCI_CBEn;
+                       REG_FRAMEn      <=      PCI_FRAMEn;
+                       REG_IRDYn               <=      PCI_IRDYn;
+                       REG_IDSEL               <=      PCI_IDSEL;
+                       REG_PAR                 <=      PCI_PAR;
+
+               end if;
+       end process;
+
+       PCI_AD                  <=      REG_AD when OE_PCI_AD ='1' else (others => 'Z');
+
+       AD_REG                  <=      REG_AD;
+       CBE_REGn                <=      REG_CBEn;
+       FRAME_REGn      <=      REG_FRAMEn;
+       IRDY_REGn               <=      REG_IRDYn;
+       IDSEL_REG               <=      REG_IDSEL;
+       PAR_REG                 <=      REG_PAR;
+
+end architecture IO_REG_DESIGN;

diff --git a/dhwk/source/MESS_1_TB.vhd b/dhwk/source/MESS_1_TB.vhd
index dbe1f78354e6d36494688b7a3c342853d12f2f06..4476632a8d29d973cf50eb5d5a5ea6b72e132d65 100644 (file)
--- a/dhwk/source/MESS_1_TB.vhd
+++ b/dhwk/source/MESS_1_TB.vhd
@@ -1,33 +1,33 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 29.08.2006\r
--- File: MESS_1_TB.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity MESS_1_TB is\r
-       port\r
-       (\r
-       KONST_1                         :in             std_logic;\r
-       PCI_IDSEL                       :in             std_logic;\r
-       DEVSELn                         :in             std_logic;\r
-       INTAn                                   :in             std_logic;\r
-       REG_OUT_XX7             :in             std_logic_vector(7 downto 0);\r
-       TB_PCI_IDSEL    :out    std_logic;\r
-       TB_DEVSELn              :out    std_logic;\r
-       TB_INTAn                        :out    std_logic\r
-       );\r
-end entity MESS_1_TB;\r
-\r
-architecture MESS_1_TB_DESIGN of MESS_1_TB is\r
- \r
-begin\r
-\r
-       TB_PCI_IDSEL    <=      PCI_IDSEL       and     KONST_1;\r
-\r
-       TB_INTAn                        <=      INTAn                   and     KONST_1;                \r
-        \r
-       TB_DEVSELn              <=      DEVSELn when REG_OUT_XX7(7) = '0' else (not REG_OUT_XX7(6));\r
-\r
-end architecture MESS_1_TB_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 29.08.2006
+-- File: MESS_1_TB.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity MESS_1_TB is
+       port
+       (
+       KONST_1                         :in             std_logic;
+       PCI_IDSEL                       :in             std_logic;
+       DEVSELn                         :in             std_logic;
+       INTAn                                   :in             std_logic;
+       REG_OUT_XX7             :in             std_logic_vector(7 downto 0);
+       TB_PCI_IDSEL    :out    std_logic;
+       TB_DEVSELn              :out    std_logic;
+       TB_INTAn                        :out    std_logic
+       );
+end entity MESS_1_TB;
+
+architecture MESS_1_TB_DESIGN of MESS_1_TB is
+ 
+begin
+
+       TB_PCI_IDSEL    <=      PCI_IDSEL       and     KONST_1;
+
+       TB_INTAn                        <=      INTAn                   and     KONST_1;                
+        
+       TB_DEVSELn              <=      DEVSELn when REG_OUT_XX7(7) = '0' else (not REG_OUT_XX7(6));
+
+end architecture MESS_1_TB_DESIGN;

diff --git a/dhwk/source/PAR_SER_CON.vhd b/dhwk/source/PAR_SER_CON.vhd
index 9d78b2b1deba6732a9e8f437868c9a5e6eaa59d0..2544f682b1d4a3b7f9bb693273a0a93dbd2f02a8 100644 (file)
--- a/dhwk/source/PAR_SER_CON.vhd
+++ b/dhwk/source/PAR_SER_CON.vhd
@@ -1,123 +1,123 @@
--- $Id: PAR_SER_CON.vhd,v 1.2 2007-03-10 16:08:48 michael Exp $\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.std_logic_unsigned.all;\r
-\r
-entity PAR_SER_CON     is\r
-       port\r
-       (\r
-       PCI_CLOCK               :in     std_logic; \r
-       RESET                           :in     std_logic; \r
-       PSC_ENABLE                      :in     std_logic; -- Parallel Serial Converter Enable\r
-       SYNC_S_FIFO_EFn                 :in     std_logic; -- Empty Flag (low active)\r
-       SPC_RDY_IN                      :in     std_logic; -- Ready to receive data\r
-       PAR_IN                          :in     std_logic_vector(7 downto 0);\r
-       SER_OUT                         :out    std_logic; -- Serial Output\r
-       S_FIFO_READn                    :out    std_logic  -- FIFO Read (low active)\r
-       );                      \r
-end entity     PAR_SER_CON ;\r
-\r
-architecture PAR_SER_CON_DESIGN        of PAR_SER_CON is\r
-\r
-constant STATE_END        :std_logic_vector(3 downto 0) := "0001";\r
-constant STATE_SEND       :std_logic_vector(3 downto 0) := "0010";\r
-constant STATE_SEND_BIT_0 :std_logic_vector(3 downto 0) := "0011";\r
-constant STATE_SEND_BIT_1 :std_logic_vector(3 downto 0) := "0100";\r
-constant STATE_SEND_BIT_2 :std_logic_vector(3 downto 0) := "0101";\r
-constant STATE_SEND_BIT_3 :std_logic_vector(3 downto 0) := "0110";\r
-constant STATE_SEND_BIT_4 :std_logic_vector(3 downto 0) := "0111";\r
-constant STATE_SEND_BIT_5 :std_logic_vector(3 downto 0) := "1000";\r
-constant STATE_SEND_BIT_6 :std_logic_vector(3 downto 0) := "1001";\r
-constant STATE_SEND_BIT_7 :std_logic_vector(3 downto 0) := "1010";\r
-\r
-signal COUNT     :std_logic_vector (3 downto 0);\r
-signal STATE     :std_logic_vector (3 downto 0); \r
-signal DATUM     :std_logic_vector (7 downto 0);\r
-signal SYNC                     :std_logic; -- make SPC_RDY_IN stable\r
-\r
-attribute syn_state_machine:boolean;\r
-attribute syn_state_machine of STATE: signal is false;\r
-attribute syn_state_machine of COUNT: signal is false;\r
-begin\r
-\r
-process(PCI_CLOCK)\r
-begin\r
-        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-                                       if ("0000" < COUNT) then\r
-                                               COUNT <= COUNT - 1;\r
-                                       end if;\r
-\r
-                if (RESET = '1') then\r
-                        STATE <= STATE_SEND;\r
-                        COUNT <= "0000";\r
-                        SER_OUT <= '0';\r
-                        S_FIFO_READn <= '1';\r
-\r
-                elsif (PSC_ENABLE = '1') then\r
-               if (COUNT = "0000") then\r
-                        COUNT <= "0011";\r
-                        case STATE is\r
-                                when STATE_SEND =>\r
-                                        if(SYNC = '1' and SYNC_S_FIFO_EFn = '1') then\r
-                                                SER_OUT <= '1';\r
-                                                S_FIFO_READn <= '0';\r
-                                                STATE <= STATE_SEND_BIT_0;\r
-                                        end if;\r
-\r
-                                when STATE_SEND_BIT_0 =>\r
-                                                DATUM     <= PAR_IN;\r
-                                                S_FIFO_READn <= '1';\r
-                                                SER_OUT <= PAR_IN(0); \r
-                                                STATE <= STATE_SEND_BIT_1;\r
-                                  \r
-                                when STATE_SEND_BIT_1 =>\r
-                                        SER_OUT <= DATUM(1); \r
-                                        STATE <= STATE_SEND_BIT_2;\r
-\r
-                                when STATE_SEND_BIT_2 =>\r
-                                        SER_OUT <= DATUM(2); \r
-                                        STATE <= STATE_SEND_BIT_3;\r
-\r
-                                when STATE_SEND_BIT_3 =>\r
-                                        SER_OUT <= DATUM(3); \r
-                                        STATE <= STATE_SEND_BIT_4;\r
-\r
-                                when STATE_SEND_BIT_4 =>\r
-                                        SER_OUT <= DATUM(4); \r
-                                        STATE <= STATE_SEND_BIT_5;\r
-                                        \r
-                                when STATE_SEND_BIT_5 =>\r
-                                        SER_OUT <= DATUM(5); \r
-                                        STATE <= STATE_SEND_BIT_6;\r
-\r
-                                when STATE_SEND_BIT_6 =>\r
-                                        SER_OUT <= DATUM(6); \r
-                                        STATE <= STATE_SEND_BIT_7;\r
-                                        \r
-                                when STATE_SEND_BIT_7 =>\r
-                                        SER_OUT <= DATUM(7); \r
-                                        STATE <= STATE_END;\r
-\r
-                                when STATE_END =>\r
-                                        SER_OUT <= '0';\r
-                                        STATE <= STATE_SEND;\r
-\r
-                                when others => STATE <= STATE_END;\r
-                        end case;\r
-                   else\r
-                       S_FIFO_READn <= '1';\r
-                    end if; -- COUNT\r
-                end if; -- RESET ... / PSC_ENABLE ...\r
-        end if; -- PCI_CLOCK ...\r
-end process;\r
-\r
-process(PCI_CLOCK)\r
-begin\r
-        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-                                               SYNC <= SPC_RDY_IN;\r
-                               end if;\r
-end process;\r
-\r
-\r
-end architecture PAR_SER_CON_DESIGN;\r
+-- $Id: PAR_SER_CON.vhd,v 1.3 2007-03-11 08:04:56 sithglan Exp $
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity PAR_SER_CON     is
+       port
+       (
+       PCI_CLOCK               :in     std_logic; 
+       RESET                           :in     std_logic; 
+       PSC_ENABLE                      :in     std_logic; -- Parallel Serial Converter Enable
+       SYNC_S_FIFO_EFn                 :in     std_logic; -- Empty Flag (low active)
+       SPC_RDY_IN                      :in     std_logic; -- Ready to receive data
+       PAR_IN                          :in     std_logic_vector(7 downto 0);
+       SER_OUT                         :out    std_logic; -- Serial Output
+       S_FIFO_READn                    :out    std_logic  -- FIFO Read (low active)
+       );                      
+end entity     PAR_SER_CON ;
+
+architecture PAR_SER_CON_DESIGN        of PAR_SER_CON is
+
+constant STATE_END        :std_logic_vector(3 downto 0) := "0001";
+constant STATE_SEND       :std_logic_vector(3 downto 0) := "0010";
+constant STATE_SEND_BIT_0 :std_logic_vector(3 downto 0) := "0011";
+constant STATE_SEND_BIT_1 :std_logic_vector(3 downto 0) := "0100";
+constant STATE_SEND_BIT_2 :std_logic_vector(3 downto 0) := "0101";
+constant STATE_SEND_BIT_3 :std_logic_vector(3 downto 0) := "0110";
+constant STATE_SEND_BIT_4 :std_logic_vector(3 downto 0) := "0111";
+constant STATE_SEND_BIT_5 :std_logic_vector(3 downto 0) := "1000";
+constant STATE_SEND_BIT_6 :std_logic_vector(3 downto 0) := "1001";
+constant STATE_SEND_BIT_7 :std_logic_vector(3 downto 0) := "1010";
+
+signal COUNT     :std_logic_vector (3 downto 0);
+signal STATE     :std_logic_vector (3 downto 0); 
+signal DATUM     :std_logic_vector (7 downto 0);
+signal SYNC                     :std_logic; -- make SPC_RDY_IN stable
+
+attribute syn_state_machine:boolean;
+attribute syn_state_machine of STATE: signal is false;
+attribute syn_state_machine of COUNT: signal is false;
+begin
+
+process(PCI_CLOCK)
+begin
+        if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                                       if ("0000" < COUNT) then
+                                               COUNT <= COUNT - 1;
+                                       end if;
+
+                if (RESET = '1') then
+                        STATE <= STATE_SEND;
+                        COUNT <= "0000";
+                        SER_OUT <= '0';
+                        S_FIFO_READn <= '1';
+
+                elsif (PSC_ENABLE = '1') then
+               if (COUNT = "0000") then
+                        COUNT <= "0011";
+                        case STATE is
+                                when STATE_SEND =>
+                                        if(SYNC = '1' and SYNC_S_FIFO_EFn = '1') then
+                                                SER_OUT <= '1';
+                                                S_FIFO_READn <= '0';
+                                                STATE <= STATE_SEND_BIT_0;
+                                        end if;
+
+                                when STATE_SEND_BIT_0 =>
+                                                DATUM     <= PAR_IN;
+                                                S_FIFO_READn <= '1';
+                                                SER_OUT <= PAR_IN(0); 
+                                                STATE <= STATE_SEND_BIT_1;
+                                  
+                                when STATE_SEND_BIT_1 =>
+                                        SER_OUT <= DATUM(1); 
+                                        STATE <= STATE_SEND_BIT_2;
+
+                                when STATE_SEND_BIT_2 =>
+                                        SER_OUT <= DATUM(2); 
+                                        STATE <= STATE_SEND_BIT_3;
+
+                                when STATE_SEND_BIT_3 =>
+                                        SER_OUT <= DATUM(3); 
+                                        STATE <= STATE_SEND_BIT_4;
+
+                                when STATE_SEND_BIT_4 =>
+                                        SER_OUT <= DATUM(4); 
+                                        STATE <= STATE_SEND_BIT_5;
+                                        
+                                when STATE_SEND_BIT_5 =>
+                                        SER_OUT <= DATUM(5); 
+                                        STATE <= STATE_SEND_BIT_6;
+
+                                when STATE_SEND_BIT_6 =>
+                                        SER_OUT <= DATUM(6); 
+                                        STATE <= STATE_SEND_BIT_7;
+                                        
+                                when STATE_SEND_BIT_7 =>
+                                        SER_OUT <= DATUM(7); 
+                                        STATE <= STATE_END;
+
+                                when STATE_END =>
+                                        SER_OUT <= '0';
+                                        STATE <= STATE_SEND;
+
+                                when others => STATE <= STATE_END;
+                        end case;
+                   else
+                       S_FIFO_READn <= '1';
+                    end if; -- COUNT
+                end if; -- RESET ... / PSC_ENABLE ...
+        end if; -- PCI_CLOCK ...
+end process;
+
+process(PCI_CLOCK)
+begin
+        if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                                               SYNC <= SPC_RDY_IN;
+                               end if;
+end process;
+
+
+end architecture PAR_SER_CON_DESIGN;

diff --git a/dhwk/source/Parity_4.vhd b/dhwk/source/Parity_4.vhd
index 768816038e74c2d2dde11280e46f8cdd43be63da..4f06bd623c9203b7d6accd0df6e0508e546fdf3d 100644 (file)
--- a/dhwk/source/Parity_4.vhd
+++ b/dhwk/source/Parity_4.vhd
@@ -1,23 +1,23 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: PARITY_4.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-\r
-entity PARITY_4 is\r
-       port\r
-       (\r
-       PAR_IN  :in             std_logic_vector(3 downto 0);   \r
-       PAR_OUT :out    std_logic\r
-       );\r
-end entity PARITY_4 ; \r
-\r
-architecture PARITY_4_DESIGN of PARITY_4 is\r
-\r
-begin\r
-\r
-       PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) ;\r
-\r
-end architecture PARITY_4_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: PARITY_4.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity PARITY_4 is
+       port
+       (
+       PAR_IN  :in             std_logic_vector(3 downto 0);   
+       PAR_OUT :out    std_logic
+       );
+end entity PARITY_4 ; 
+
+architecture PARITY_4_DESIGN of PARITY_4 is
+
+begin
+
+       PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) ;
+
+end architecture PARITY_4_DESIGN;

diff --git a/dhwk/source/REG.vhd b/dhwk/source/REG.vhd
index 0c91d25e33050060b1e9cbe122a01c1e839f73c7..10a25a8268f6885cff15c86fd5867be7cd5c25d7 100644 (file)
--- a/dhwk/source/REG.vhd
+++ b/dhwk/source/REG.vhd
@@ -1,38 +1,38 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: REG.VHD\r
-\r
-library ieee ;\r
-use ieee.std_logic_1164.all ;\r
-\r
-entity REG is\r
-       port\r
-       (\r
-       CLOCK           :in             std_logic; \r
-       RESET           :in             std_logic; \r
-       WRITE           :in             std_logic;   \r
-       REG_IN  :in             std_logic_vector(7 downto 0);\r
-       REG_OUT :out    std_logic_vector(7 downto 0) \r
-       );\r
-end entity REG ;\r
-\r
-architecture REG_DESIGN of REG is\r
-\r
-       signal SIG_REG  :std_logic_vector (7 downto 0);\r
-\r
-begin\r
-\r
-       process (CLOCK) \r
-       begin\r
-               if (CLOCK'event and CLOCK = '1') then\r
-                       if                      RESET   =       '1'     then    SIG_REG <= X"00";\r
-                               elsif   WRITE   =       '1'     then    SIG_REG <= REG_IN;\r
-                               else                                                                            SIG_REG <= SIG_REG;\r
-               end if;\r
-               end if;\r
-       end process;\r
-\r
-       REG_OUT <= SIG_REG;\r
-\r
-end architecture REG_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: REG.VHD
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity REG is
+       port
+       (
+       CLOCK           :in             std_logic; 
+       RESET           :in             std_logic; 
+       WRITE           :in             std_logic;   
+       REG_IN  :in             std_logic_vector(7 downto 0);
+       REG_OUT :out    std_logic_vector(7 downto 0) 
+       );
+end entity REG ;
+
+architecture REG_DESIGN of REG is
+
+       signal SIG_REG  :std_logic_vector (7 downto 0);
+
+begin
+
+       process (CLOCK) 
+       begin
+               if (CLOCK'event and CLOCK = '1') then
+                       if                      RESET   =       '1'     then    SIG_REG <= X"00";
+                               elsif   WRITE   =       '1'     then    SIG_REG <= REG_IN;
+                               else                                                                            SIG_REG <= SIG_REG;
+               end if;
+               end if;
+       end process;
+
+       REG_OUT <= SIG_REG;
+
+end architecture REG_DESIGN;

diff --git a/dhwk/source/SER_PAR_CON.vhd b/dhwk/source/SER_PAR_CON.vhd
index a030eaa6a63775e4e9690075e524be0819610419..a6a2606a6db5f71fe2b9fc61676c54ab66b5a5fe 100644 (file)
--- a/dhwk/source/SER_PAR_CON.vhd
+++ b/dhwk/source/SER_PAR_CON.vhd
@@ -1,154 +1,154 @@
--- $Id: SER_PAR_CON.vhd,v 1.1 2007-03-10 11:24:03 sithglan Exp $\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.std_logic_unsigned.all;\r
-\r
-entity SER_PAR_CON is\r
-       port\r
-       (\r
-       PCI_CLOCK                       :in     std_logic; \r
-       RESET                           :in     std_logic; \r
-       SPC_ENABLE                      :in     std_logic; -- Driver Enable Sender/Receiver\r
-       SYNC_R_FIFO_FFn                 :in     std_logic; -- FIFO Full Flag (low active)\r
-       SERIAL_IN                       :in     std_logic; -- Serial Input\r
-       R_FIFO_WRITEn                   :out    std_logic; -- FIFO Write (low active)\r
-       SPC_RDY_OUT                     :out    std_logic; -- Ready to Receive Data\r
-       PAR_OUT                         :out    std_logic_vector(7 downto 0)\r
-       );\r
-end entity SER_PAR_CON ;\r
-\r
-\r
-architecture SER_PAR_CON_DESIGN of SER_PAR_CON is\r
-\r
--- constant STATE_RECV            :std_logic_vector(3 downto 0) := "0001";\r
-constant STATE_RECV_START_BIT  :std_logic_vector(3 downto 0) := "0010";\r
-constant STATE_RECV_BIT_0      :std_logic_vector(3 downto 0) := "0011";\r
-constant STATE_RECV_BIT_1      :std_logic_vector(3 downto 0) := "0100";\r
-constant STATE_RECV_BIT_2      :std_logic_vector(3 downto 0) := "0101";\r
-constant STATE_RECV_BIT_3      :std_logic_vector(3 downto 0) := "0110";\r
-constant STATE_RECV_BIT_4      :std_logic_vector(3 downto 0) := "0111";\r
-constant STATE_RECV_BIT_5      :std_logic_vector(3 downto 0) := "1000";\r
-constant STATE_RECV_BIT_6      :std_logic_vector(3 downto 0) := "1001";\r
-constant STATE_RECV_BIT_7      :std_logic_vector(3 downto 0) := "1010";\r
-constant STATE_RECV_FIFOFULL   :std_logic_vector(3 downto 0) := "1011";\r
-\r
-signal COUNT     :std_logic_vector (3 downto 0);\r
-signal STATE     :std_logic_vector (3 downto 0);\r
-signal STARTBIT  :std_logic_vector (3 downto 0);\r
-\r
-\r
-attribute syn_state_machine:boolean;\r
-attribute syn_state_machine of STATE: signal is false;\r
-attribute syn_state_machine of COUNT: signal is false;\r
-\r
-begin\r
-\r
-process(PCI_CLOCK)\r
-begin\r
-        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-                                               if ("0000" < COUNT) then\r
-                                               COUNT <= COUNT - 1;\r
-                                       end if;\r
-\r
--- war nicht das Problem des Datenverlusts\r
---        if (R_FIFO_WRITEn = '0' and COUNT = "0000") then\r
---            R_FIFO_WRITEn <= '1';\r
----      end if;\r
-\r
-                if (RESET = '1') then\r
-                        STATE <= STATE_RECV_START_BIT;\r
-                        COUNT <= "0000";\r
-                        R_FIFO_WRITEn <= '1';\r
-\r
-                elsif (SPC_ENABLE = '1') then\r
-                       \r
-                                                                                        if (STATE = STATE_RECV_START_BIT) then\r
-                              R_FIFO_WRITEn <= '1';\r
-                                                                                               if (STARTBIT = "0011") then\r
-                                                                                                                               COUNT <= "0011";\r
-                                   STATE <= STATE_RECV_BIT_0;\r
-                              end if;\r
-\r
-                       elsif (STATE = STATE_RECV_FIFOFULL) then\r
-                              if (SYNC_R_FIFO_FFn = '1') then\r
-                                      R_FIFO_WRITEn <= '0';\r
-                                      STATE <= STATE_RECV_START_BIT;\r
-                              end if;\r
-\r
-                       elsif (COUNT = "0000") then\r
-                        COUNT <= "0011";\r
-                        case STATE is\r
-                                                                                                                               \r
-                                when STATE_RECV_BIT_0 =>\r
-                                        PAR_OUT(0) <= STARTBIT(0);\r
-                                        STATE <= STATE_RECV_BIT_1;\r
-\r
-                                when STATE_RECV_BIT_1 =>\r
-                                        PAR_OUT(1) <= STARTBIT(0);\r
-                                        STATE <= STATE_RECV_BIT_2;\r
-                                        \r
-                                when STATE_RECV_BIT_2 =>\r
-                                        PAR_OUT(2) <= STARTBIT(0);\r
-                                        STATE <= STATE_RECV_BIT_3;\r
-                                        \r
-                                when STATE_RECV_BIT_3 =>\r
-                                        PAR_OUT(3) <= STARTBIT(0);\r
-                                        STATE <= STATE_RECV_BIT_4;\r
-                                        \r
-                                when STATE_RECV_BIT_4 =>\r
-                                        PAR_OUT(4) <= STARTBIT(0);\r
-                                        STATE <= STATE_RECV_BIT_5;\r
-                                        \r
-                                when STATE_RECV_BIT_5 =>\r
-                                        PAR_OUT(5) <= STARTBIT(0);\r
-                                        STATE <= STATE_RECV_BIT_6;\r
-                                        \r
-                                when STATE_RECV_BIT_6 =>\r
-                                        PAR_OUT(6) <= STARTBIT(0);\r
-                                        STATE <= STATE_RECV_BIT_7;\r
-                                        \r
-                                when STATE_RECV_BIT_7 =>\r
-                                        PAR_OUT(7) <= STARTBIT(0);\r
-\r
-                                        if (SYNC_R_FIFO_FFn = '1') then\r
-                                             STATE <= STATE_RECV_START_BIT;\r
-                                             R_FIFO_WRITEn <= '0';\r
-                                        else \r
-                                             STATE <= STATE_RECV_FIFOFULL;\r
-                                        end if;\r
-\r
-                                                                                                                               when others =>\r
-                                                                                                                                                               STATE <= STATE_RECV_START_BIT;\r
-\r
-                        end case;\r
-                     end if; -- COUNT\r
-                end if; -- RESET ... / SPC_ENABLE ...\r
-        end if; -- PCI_CLOCK ...\r
-end process;\r
-\r
-process(PCI_CLOCK)\r
-begin\r
-               if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-      SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;\r
-               end if;\r
-end process;\r
-\r
-\r
-process(PCI_CLOCK)\r
-begin\r
-        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-                                       if (RESET = '1') then\r
-                                               STARTBIT <= "0000";\r
-                                       else\r
-                                       STARTBIT(0) <= SERIAL_IN;\r
-                                       STARTBIT(1) <= STARTBIT(0);\r
-                                       STARTBIT(2) <= STARTBIT(1);\r
-                                       STARTBIT(3) <= STARTBIT(2);\r
-                                       end if;                           \r
-                       end if;\r
-end process;\r
-\r
-\r
-\r
-end architecture SER_PAR_CON_DESIGN;\r
+-- $Id: SER_PAR_CON.vhd,v 1.2 2007-03-11 08:04:56 sithglan Exp $
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity SER_PAR_CON is
+       port
+       (
+       PCI_CLOCK                       :in     std_logic; 
+       RESET                           :in     std_logic; 
+       SPC_ENABLE                      :in     std_logic; -- Driver Enable Sender/Receiver
+       SYNC_R_FIFO_FFn                 :in     std_logic; -- FIFO Full Flag (low active)
+       SERIAL_IN                       :in     std_logic; -- Serial Input
+       R_FIFO_WRITEn                   :out    std_logic; -- FIFO Write (low active)
+       SPC_RDY_OUT                     :out    std_logic; -- Ready to Receive Data
+       PAR_OUT                         :out    std_logic_vector(7 downto 0)
+       );
+end entity SER_PAR_CON ;
+
+
+architecture SER_PAR_CON_DESIGN of SER_PAR_CON is
+
+-- constant STATE_RECV            :std_logic_vector(3 downto 0) := "0001";
+constant STATE_RECV_START_BIT  :std_logic_vector(3 downto 0) := "0010";
+constant STATE_RECV_BIT_0      :std_logic_vector(3 downto 0) := "0011";
+constant STATE_RECV_BIT_1      :std_logic_vector(3 downto 0) := "0100";
+constant STATE_RECV_BIT_2      :std_logic_vector(3 downto 0) := "0101";
+constant STATE_RECV_BIT_3      :std_logic_vector(3 downto 0) := "0110";
+constant STATE_RECV_BIT_4      :std_logic_vector(3 downto 0) := "0111";
+constant STATE_RECV_BIT_5      :std_logic_vector(3 downto 0) := "1000";
+constant STATE_RECV_BIT_6      :std_logic_vector(3 downto 0) := "1001";
+constant STATE_RECV_BIT_7      :std_logic_vector(3 downto 0) := "1010";
+constant STATE_RECV_FIFOFULL   :std_logic_vector(3 downto 0) := "1011";
+
+signal COUNT     :std_logic_vector (3 downto 0);
+signal STATE     :std_logic_vector (3 downto 0);
+signal STARTBIT  :std_logic_vector (3 downto 0);
+
+
+attribute syn_state_machine:boolean;
+attribute syn_state_machine of STATE: signal is false;
+attribute syn_state_machine of COUNT: signal is false;
+
+begin
+
+process(PCI_CLOCK)
+begin
+        if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                                               if ("0000" < COUNT) then
+                                               COUNT <= COUNT - 1;
+                                       end if;
+
+-- war nicht das Problem des Datenverlusts
+--        if (R_FIFO_WRITEn = '0' and COUNT = "0000") then
+--            R_FIFO_WRITEn <= '1';
+---      end if;
+
+                if (RESET = '1') then
+                        STATE <= STATE_RECV_START_BIT;
+                        COUNT <= "0000";
+                        R_FIFO_WRITEn <= '1';
+
+                elsif (SPC_ENABLE = '1') then
+                       
+                                                                                        if (STATE = STATE_RECV_START_BIT) then
+                              R_FIFO_WRITEn <= '1';
+                                                                                               if (STARTBIT = "0011") then
+                                                                                                                               COUNT <= "0011";
+                                   STATE <= STATE_RECV_BIT_0;
+                              end if;
+
+                       elsif (STATE = STATE_RECV_FIFOFULL) then
+                              if (SYNC_R_FIFO_FFn = '1') then
+                                      R_FIFO_WRITEn <= '0';
+                                      STATE <= STATE_RECV_START_BIT;
+                              end if;
+
+                       elsif (COUNT = "0000") then
+                        COUNT <= "0011";
+                        case STATE is
+                                                                                                                               
+                                when STATE_RECV_BIT_0 =>
+                                        PAR_OUT(0) <= STARTBIT(0);
+                                        STATE <= STATE_RECV_BIT_1;
+
+                                when STATE_RECV_BIT_1 =>
+                                        PAR_OUT(1) <= STARTBIT(0);
+                                        STATE <= STATE_RECV_BIT_2;
+                                        
+                                when STATE_RECV_BIT_2 =>
+                                        PAR_OUT(2) <= STARTBIT(0);
+                                        STATE <= STATE_RECV_BIT_3;
+                                        
+                                when STATE_RECV_BIT_3 =>
+                                        PAR_OUT(3) <= STARTBIT(0);
+                                        STATE <= STATE_RECV_BIT_4;
+                                        
+                                when STATE_RECV_BIT_4 =>
+                                        PAR_OUT(4) <= STARTBIT(0);
+                                        STATE <= STATE_RECV_BIT_5;
+                                        
+                                when STATE_RECV_BIT_5 =>
+                                        PAR_OUT(5) <= STARTBIT(0);
+                                        STATE <= STATE_RECV_BIT_6;
+                                        
+                                when STATE_RECV_BIT_6 =>
+                                        PAR_OUT(6) <= STARTBIT(0);
+                                        STATE <= STATE_RECV_BIT_7;
+                                        
+                                when STATE_RECV_BIT_7 =>
+                                        PAR_OUT(7) <= STARTBIT(0);
+
+                                        if (SYNC_R_FIFO_FFn = '1') then
+                                             STATE <= STATE_RECV_START_BIT;
+                                             R_FIFO_WRITEn <= '0';
+                                        else 
+                                             STATE <= STATE_RECV_FIFOFULL;
+                                        end if;
+
+                                                                                                                               when others =>
+                                                                                                                                                               STATE <= STATE_RECV_START_BIT;
+
+                        end case;
+                     end if; -- COUNT
+                end if; -- RESET ... / SPC_ENABLE ...
+        end if; -- PCI_CLOCK ...
+end process;
+
+process(PCI_CLOCK)
+begin
+               if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+      SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;
+               end if;
+end process;
+
+
+process(PCI_CLOCK)
+begin
+        if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                                       if (RESET = '1') then
+                                               STARTBIT <= "0000";
+                                       else
+                                       STARTBIT(0) <= SERIAL_IN;
+                                       STARTBIT(1) <= STARTBIT(0);
+                                       STARTBIT(2) <= STARTBIT(1);
+                                       STARTBIT(3) <= STARTBIT(2);
+                                       end if;                           
+                       end if;
+end process;
+
+
+
+end architecture SER_PAR_CON_DESIGN;

diff --git a/dhwk/source/Verg_2.vhd b/dhwk/source/Verg_2.vhd
index 39d51acc147504371f2b2156232c049cf4107a74..94aa714cee8b6e863dbaf10f7e27899a6eff6f95 100644 (file)
--- a/dhwk/source/Verg_2.vhd
+++ b/dhwk/source/Verg_2.vhd
@@ -1,31 +1,31 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: VERG_2.VHD\r
-\r
-library ieee ;\r
-use ieee.std_logic_1164.all ;\r
-\r
-entity VERG_2  is\r
-       port\r
-       (\r
-       IN_A            :in             std_logic_vector(1 downto 0);\r
-       IN_B            :in             std_logic_vector(1 downto 0);\r
-       GLEICH  :out    std_logic\r
-       );\r
-end entity VERG_2 ;\r
-\r
-architecture VERG_2_DESIGN of VERG_2 is\r
-\r
-begin\r
-\r
-       process (IN_A,IN_B) \r
-       begin \r
-\r
-               if                      IN_A    =       IN_B    then    GLEICH  <=      '1';\r
-                       else                                                                                    GLEICH  <=      '0';   \r
-               end if;\r
-\r
-       end process;\r
-\r
-end architecture VERG_2_DESIGN ;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_2.VHD
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity VERG_2  is
+       port
+       (
+       IN_A            :in             std_logic_vector(1 downto 0);
+       IN_B            :in             std_logic_vector(1 downto 0);
+       GLEICH  :out    std_logic
+       );
+end entity VERG_2 ;
+
+architecture VERG_2_DESIGN of VERG_2 is
+
+begin
+
+       process (IN_A,IN_B) 
+       begin 
+
+               if                      IN_A    =       IN_B    then    GLEICH  <=      '1';
+                       else                                                                                    GLEICH  <=      '0';   
+               end if;
+
+       end process;
+
+end architecture VERG_2_DESIGN ;

diff --git a/dhwk/source/Verg_4.vhd b/dhwk/source/Verg_4.vhd
index 6aafdad19588f8994e3f138db2439a959cf02e4c..e3900cf4e2703a75d638ea7fcf679d72332c6155 100644 (file)
--- a/dhwk/source/Verg_4.vhd
+++ b/dhwk/source/Verg_4.vhd
@@ -1,32 +1,32 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: VERG_4.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-\r
-entity VERG_4 is\r
-       port\r
-       (\r
-       IN_A            :in             std_logic_vector(3 downto 0);\r
-       IN_B            :in             std_logic_vector(3 downto 0);\r
-       GLEICH  :out    std_logic\r
-       );\r
-end entity VERG_4 ;\r
-\r
-architecture VERG_4_DESIGN of VERG_4 is\r
-\r
-begin\r
-\r
-       process (IN_A,IN_B) \r
-       begin \r
-\r
-               if                      IN_A    =       IN_B    then    GLEICH  <=      '1';\r
-                       else                                                                                    GLEICH  <=      '0';   \r
-               end if;\r
-\r
-       end process;\r
-\r
-end architecture VERG_4_DESIGN;\r
-\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_4.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_4 is
+       port
+       (
+       IN_A            :in             std_logic_vector(3 downto 0);
+       IN_B            :in             std_logic_vector(3 downto 0);
+       GLEICH  :out    std_logic
+       );
+end entity VERG_4 ;
+
+architecture VERG_4_DESIGN of VERG_4 is
+
+begin
+
+       process (IN_A,IN_B) 
+       begin 
+
+               if                      IN_A    =       IN_B    then    GLEICH  <=      '1';
+                       else                                                                                    GLEICH  <=      '0';   
+               end if;
+
+       end process;
+
+end architecture VERG_4_DESIGN;
+

diff --git a/dhwk/source/config_00h.vhd b/dhwk/source/config_00h.vhd
index 0346aebac03047add609be4c693b09e5db7d3f10..a0c6ea4fe7775d1e378f8f6b36aab9edd29ab1a2 100644 (file)
--- a/dhwk/source/config_00h.vhd
+++ b/dhwk/source/config_00h.vhd
@@ -1,28 +1,28 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_00H.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_00H is\r
-       port\r
-       (\r
-       VENDOR_ID                       :in             std_logic_vector (15 downto 0);\r
-       CONF_DATA_00H   :out    std_logic_vector (31 downto 0)\r
-       );\r
-end entity CONFIG_00H;\r
-\r
-architecture CONFIG_00H_DESIGN of CONFIG_00H is\r
-\r
--- PCI Configuration Space Header Addr : HEX 00 --\r
-\r
-       constant        CONF_DEVICE_ID          :std_logic_vector(31 downto 16) := X"AFFE";--???? \r
---constant     CONF_VENDOR_ID          :std_logic_vector(15 downto  0) := X"BAFF";--???? \r
-\r
-begin\r
-\r
-       CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;\r
-\r
-end architecture CONFIG_00H_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_00H.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_00H is
+       port
+       (
+       VENDOR_ID                       :in             std_logic_vector (15 downto 0);
+       CONF_DATA_00H   :out    std_logic_vector (31 downto 0)
+       );
+end entity CONFIG_00H;
+
+architecture CONFIG_00H_DESIGN of CONFIG_00H is
+
+-- PCI Configuration Space Header Addr : HEX 00 --
+
+       constant        CONF_DEVICE_ID          :std_logic_vector(31 downto 16) := X"AFFE";--???? 
+--constant     CONF_VENDOR_ID          :std_logic_vector(15 downto  0) := X"BAFF";--???? 
+
+begin
+
+       CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
+
+end architecture CONFIG_00H_DESIGN;

diff --git a/dhwk/source/config_04h.vhd b/dhwk/source/config_04h.vhd
index 2dbacf1152e66ecce76eb09a6c3f01adbfec3328..906a9ca21f65244d6d8488cfe3e0256b82578c71 100644 (file)
--- a/dhwk/source/config_04h.vhd
+++ b/dhwk/source/config_04h.vhd
@@ -1,115 +1,115 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_04H.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_04H is\r
-       port\r
-       (\r
-       PCI_CLOCK                       :in             std_logic;\r
-       PCI_RSTn                        :in             std_logic;\r
-       SERR                                    :in             std_logic;\r
-       PERR                                    :in             std_logic;\r
-       AD_REG                          :in             std_logic_vector(31 downto 0);\r
-       CBE_REGn                        :in             std_logic_vector( 3 downto 0);\r
-       CONF_WR_04H             :in             std_logic;\r
-       CONF_DATA_04H   :out    std_logic_vector(31 downto 0)\r
-       );\r
-end entity CONFIG_04H;\r
-\r
-architecture CONFIG_04H_DESIGN of CONFIG_04H is\r
-\r
-       signal          CONF_STATUS             :std_logic_vector(31 downto 16);\r
-       signal          CONF_COMMAND    :std_logic_vector(15 downto  0);\r
-\r
-\r
-begin\r
-\r
---*******************************************************************\r
---************* PCI Configuration Space Header "STATUS" *************\r
---*******************************************************************\r
-\r
-       CONF_STATUS(20 downto 16)       <= "00000"      ;-- Reserved\r
-       CONF_STATUS(21          )       <= '0'                  ;-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz\r
-       CONF_STATUS(22                                  )       <= '0'                  ;-- MAS/TAR: "R_O" \r
-       CONF_STATUS(23          )       <= '0'                  ;-- ???/???: "R_O" : fast back-to-back\r
-       CONF_STATUS(24          )       <= '0'                  ;-- Master :\r
---CONF_STATUS(26 downto 25)    <= "00"                 ;-- Mas/Tar: "R_O" : timing fast   for "DEVSEL"\r
-       CONF_STATUS(26 downto 25)       <= "01"                 ;-- Mas/Tar: "R_O" : timing medium for "DEVSEL"\r
---CONF_STATUS(26 downto 25)    <= "10"                 ;-- Mas/Tar: "R_O" : timing slow   for "DEVSEL"\r
---CONF_STATUS(26 downto 25)    <= "11"                 ;-- Mas/Tar: "R_O" : reserved\r
-       CONF_STATUS(27          )       <= '0'                  ;-- Target : "R_W" : Taget-Abort\r
-       CONF_STATUS(28                                  )       <= '0'                  ;-- Master : "R_W" : Taget-Abort\r
-       CONF_STATUS(29          )       <= '0'                  ;-- Master : "R_W" : Master-Abort\r
---CONF_STATUS(30                                       )       <= SERR                 ;-- Mas/Tar: "R_W" : SERR\r
---CONF_STATUS(31                                       )       <= PERR                 ;-- Mas/Tar: "R_W" : PERR\r
-\r
-       process (PCI_CLOCK,PCI_RSTn) \r
-       begin\r
-               if PCI_RSTn = '0' then  CONF_STATUS(30) <= '0';\r
-                                                                                                               CONF_STATUS(31) <= '0';\r
-\r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-\r
-                       if                      CONF_WR_04H     = '1' and CBE_REGn(3) = '0' then \r
-\r
-                                                       CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30)); \r
-                                                       CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));\r
-\r
-                               else    CONF_STATUS(30) <= SERR or CONF_STATUS(30);\r
-                                                       CONF_STATUS(31) <= PERR or CONF_STATUS(31);\r
-\r
-                       end if; \r
-               end if; \r
-       end process;\r
-\r
---*******************************************************************\r
---*********** PCI Configuration Space Header "COMMAND" **************\r
---*******************************************************************\r
-\r
---     CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???\r
---     CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???\r
---     CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus \r
---     CONF_COMMAND( 3) <= '0';-- Special Cycle ???\r
---     CONF_COMMAND( 4) <= '0';-- Master ??? \r
---     CONF_COMMAND( 5) <= '0';-- VGA    ???\r
---     CONF_COMMAND( 6) <= '0';-- Party checking enable/disable\r
-               CONF_COMMAND( 7) <= '0';-- address/data stepping ???\r
---     CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"\r
---     CONF_COMMAND( 9) <= '0';-- fast back-to-back\r
---     CONF_COMMAND(10) <= '0';-- Reserved\r
---     CONF_COMMAND(11) <= '0';-- Reserved\r
---     CONF_COMMAND(12) <= '0';-- Reserved\r
---     CONF_COMMAND(13) <= '0';-- Reserved\r
---     CONF_COMMAND(14) <= '0';-- Reserved\r
---     CONF_COMMAND(15) <= '0';-- Reserved\r
-\r
-       process (PCI_CLOCK,PCI_RSTn) \r
-       begin\r
-               if PCI_RSTn = '0' then  CONF_COMMAND(15 downto 8) <= (others =>'0');\r
-                                                                                                               CONF_COMMAND( 6 downto 0) <= (others =>'0');\r
-\r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-\r
-                       if              CONF_WR_04H      = '1'and CBE_REGn(1) = '0' then \r
-\r
-                                                       CONF_COMMAND(15 downto 8)       <=                              AD_REG(15 downto 8);\r
-                               else    CONF_COMMAND(15 downto 8)       <=      CONF_COMMAND(15 downto 8);\r
-                       end if;\r
-\r
-\r
-                       if              CONF_WR_04H      = '1'and CBE_REGn(0) = '0' then \r
-\r
-                                                       CONF_COMMAND( 6 downto 0) <=                            AD_REG( 6 downto 0);\r
-                               else    CONF_COMMAND( 6 downto 0) <=    CONF_COMMAND( 6 downto 0);\r
-                       end if;\r
-\r
-               end if;\r
-       end process;\r
-\r
-       CONF_DATA_04H   <= CONF_STATUS & CONF_COMMAND;  \r
-\r
-end architecture CONFIG_04H_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_04H.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_04H is
+       port
+       (
+       PCI_CLOCK                       :in             std_logic;
+       PCI_RSTn                        :in             std_logic;
+       SERR                                    :in             std_logic;
+       PERR                                    :in             std_logic;
+       AD_REG                          :in             std_logic_vector(31 downto 0);
+       CBE_REGn                        :in             std_logic_vector( 3 downto 0);
+       CONF_WR_04H             :in             std_logic;
+       CONF_DATA_04H   :out    std_logic_vector(31 downto 0)
+       );
+end entity CONFIG_04H;
+
+architecture CONFIG_04H_DESIGN of CONFIG_04H is
+
+       signal          CONF_STATUS             :std_logic_vector(31 downto 16);
+       signal          CONF_COMMAND    :std_logic_vector(15 downto  0);
+
+
+begin
+
+--*******************************************************************
+--************* PCI Configuration Space Header "STATUS" *************
+--*******************************************************************
+
+       CONF_STATUS(20 downto 16)       <= "00000"      ;-- Reserved
+       CONF_STATUS(21          )       <= '0'                  ;-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz
+       CONF_STATUS(22                                  )       <= '0'                  ;-- MAS/TAR: "R_O" 
+       CONF_STATUS(23          )       <= '0'                  ;-- ???/???: "R_O" : fast back-to-back
+       CONF_STATUS(24          )       <= '0'                  ;-- Master :
+--CONF_STATUS(26 downto 25)    <= "00"                 ;-- Mas/Tar: "R_O" : timing fast   for "DEVSEL"
+       CONF_STATUS(26 downto 25)       <= "01"                 ;-- Mas/Tar: "R_O" : timing medium for "DEVSEL"
+--CONF_STATUS(26 downto 25)    <= "10"                 ;-- Mas/Tar: "R_O" : timing slow   for "DEVSEL"
+--CONF_STATUS(26 downto 25)    <= "11"                 ;-- Mas/Tar: "R_O" : reserved
+       CONF_STATUS(27          )       <= '0'                  ;-- Target : "R_W" : Taget-Abort
+       CONF_STATUS(28                                  )       <= '0'                  ;-- Master : "R_W" : Taget-Abort
+       CONF_STATUS(29          )       <= '0'                  ;-- Master : "R_W" : Master-Abort
+--CONF_STATUS(30                                       )       <= SERR                 ;-- Mas/Tar: "R_W" : SERR
+--CONF_STATUS(31                                       )       <= PERR                 ;-- Mas/Tar: "R_W" : PERR
+
+       process (PCI_CLOCK,PCI_RSTn) 
+       begin
+               if PCI_RSTn = '0' then  CONF_STATUS(30) <= '0';
+                                                                                                               CONF_STATUS(31) <= '0';
+
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+                       if                      CONF_WR_04H     = '1' and CBE_REGn(3) = '0' then 
+
+                                                       CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30)); 
+                                                       CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));
+
+                               else    CONF_STATUS(30) <= SERR or CONF_STATUS(30);
+                                                       CONF_STATUS(31) <= PERR or CONF_STATUS(31);
+
+                       end if; 
+               end if; 
+       end process;
+
+--*******************************************************************
+--*********** PCI Configuration Space Header "COMMAND" **************
+--*******************************************************************
+
+--     CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???
+--     CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???
+--     CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus 
+--     CONF_COMMAND( 3) <= '0';-- Special Cycle ???
+--     CONF_COMMAND( 4) <= '0';-- Master ??? 
+--     CONF_COMMAND( 5) <= '0';-- VGA    ???
+--     CONF_COMMAND( 6) <= '0';-- Party checking enable/disable
+               CONF_COMMAND( 7) <= '0';-- address/data stepping ???
+--     CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"
+--     CONF_COMMAND( 9) <= '0';-- fast back-to-back
+--     CONF_COMMAND(10) <= '0';-- Reserved
+--     CONF_COMMAND(11) <= '0';-- Reserved
+--     CONF_COMMAND(12) <= '0';-- Reserved
+--     CONF_COMMAND(13) <= '0';-- Reserved
+--     CONF_COMMAND(14) <= '0';-- Reserved
+--     CONF_COMMAND(15) <= '0';-- Reserved
+
+       process (PCI_CLOCK,PCI_RSTn) 
+       begin
+               if PCI_RSTn = '0' then  CONF_COMMAND(15 downto 8) <= (others =>'0');
+                                                                                                               CONF_COMMAND( 6 downto 0) <= (others =>'0');
+
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+                       if              CONF_WR_04H      = '1'and CBE_REGn(1) = '0' then 
+
+                                                       CONF_COMMAND(15 downto 8)       <=                              AD_REG(15 downto 8);
+                               else    CONF_COMMAND(15 downto 8)       <=      CONF_COMMAND(15 downto 8);
+                       end if;
+
+
+                       if              CONF_WR_04H      = '1'and CBE_REGn(0) = '0' then 
+
+                                                       CONF_COMMAND( 6 downto 0) <=                            AD_REG( 6 downto 0);
+                               else    CONF_COMMAND( 6 downto 0) <=    CONF_COMMAND( 6 downto 0);
+                       end if;
+
+               end if;
+       end process;
+
+       CONF_DATA_04H   <= CONF_STATUS & CONF_COMMAND;  
+
+end architecture CONFIG_04H_DESIGN;

diff --git a/dhwk/source/config_08h.vhd b/dhwk/source/config_08h.vhd
index b400eabaefcf316dbae8cb3a4a1670cbe7625dd8..fe9e6c456a3d14d94bb39a5429159ef732e4cb34 100644 (file)
--- a/dhwk/source/config_08h.vhd
+++ b/dhwk/source/config_08h.vhd
@@ -1,28 +1,28 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_08H.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_08H is\r
-       port\r
-       (\r
-       REVISION_ID             :in             std_logic_vector ( 7 downto 0);\r
-       CONF_DATA_08H   :out    std_logic_vector (31 downto 0)\r
-       );\r
-end entity CONFIG_08H;\r
-\r
-architecture CONFIG_08H_DESIGN of CONFIG_08H is\r
-\r
--- PCI Configuration Space Header Addr : HEX 08 --\r
-\r
-       constant        CONF_CLASS_CODE         :std_logic_vector (31 downto  8) := X"078000";--other comm. device              \r
---constant     CONF_REVISION_ID        :std_logic_vector ( 7 downto  0) := X"00";                      \r
-\r
-begin\r
-\r
-       CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;\r
-\r
-end architecture CONFIG_08H_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_08H.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_08H is
+       port
+       (
+       REVISION_ID             :in             std_logic_vector ( 7 downto 0);
+       CONF_DATA_08H   :out    std_logic_vector (31 downto 0)
+       );
+end entity CONFIG_08H;
+
+architecture CONFIG_08H_DESIGN of CONFIG_08H is
+
+-- PCI Configuration Space Header Addr : HEX 08 --
+
+       constant        CONF_CLASS_CODE         :std_logic_vector (31 downto  8) := X"078000";--other comm. device              
+--constant     CONF_REVISION_ID        :std_logic_vector ( 7 downto  0) := X"00";                      
+
+begin
+
+       CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
+
+end architecture CONFIG_08H_DESIGN;

diff --git a/dhwk/source/config_10h.vhd b/dhwk/source/config_10h.vhd
index 6621607092f9ac8d2463fb9eb4852c6a9699f3f3..9e807fa51342a4b1f7c22f1f97b5d98fde126acc 100644 (file)
--- a/dhwk/source/config_10h.vhd
+++ b/dhwk/source/config_10h.vhd
@@ -1,87 +1,87 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_10H.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_10H is\r
-       port\r
-       (\r
-       PCI_CLOCK                       :in             std_logic;\r
-       PCI_RSTn                        :in             std_logic;\r
-       AD_REG                          :in             std_logic_vector(31 downto 0);\r
-       CBE_REGn                        :in             std_logic_vector( 3 downto 0);\r
-       CONF_WR_10H             :in             std_logic;\r
-       CONF_DATA_10H   :out    std_logic_vector(31 downto 0)\r
-       );\r
-end entity CONFIG_10H;\r
-\r
-architecture CONFIG_10H_DESIGN of CONFIG_10H is\r
-\r
-       signal          CONF_BAS_ADDR_REG       :std_logic_vector(31 downto  0);\r
-\r
-begin\r
-\r
---*******************************************************************\r
---***** PCI Configuration Space Header "BASE ADDRESS REGISTER" ******\r
---*******************************************************************\r
-\r
-       CONF_BAS_ADDR_REG(1 downto 0) <= "01"   ;-- Base Address Register for "I/O"\r
-       CONF_BAS_ADDR_REG(3 downto 2)   <= "00" ;-- IO Bereich = 16 BYTE\r
-\r
-       process (PCI_CLOCK,PCI_RSTn) \r
-       begin\r
-\r
---     if PCI_RSTn = '0' then  CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');\r
-               if PCI_RSTn = '0' then  CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');\r
-                                                               \r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-\r
-                       if                      CONF_WR_10H      = '1'and CBE_REGn(3) = '0' then \r
-\r
-                                                       CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);\r
-\r
-                               else    CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);\r
-                       end if;\r
-\r
-                       if                      CONF_WR_10H      = '1'and CBE_REGn(2) = '0' then \r
-\r
-                                                       CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);\r
-\r
-                               else    CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);\r
-                       end if;\r
-\r
-                       if                      CONF_WR_10H      = '1'and CBE_REGn(1) = '0' then \r
-\r
-                                                       CONF_BAS_ADDR_REG(15 downto  8) <= AD_REG(15 downto  8);\r
-\r
-                               else    CONF_BAS_ADDR_REG(15 downto  8) <= CONF_BAS_ADDR_REG(15 downto  8);\r
-                       end if;\r
-\r
---                     if                      CONF_WR_10H      = '1'and CBE_REGn(0) = '0' then \r
---\r
---                                                     CONF_BAS_ADDR_REG( 7 downto  2) <= AD_REG( 7 downto  2);\r
---\r
---                             else    CONF_BAS_ADDR_REG( 7 downto  2) <= CONF_BAS_ADDR_REG( 7 downto  2);\r
---                     end if;\r
-\r
-                       if                      CONF_WR_10H      = '1'and CBE_REGn(0) = '0' then \r
-\r
-                                                       CONF_BAS_ADDR_REG( 7 downto  4) <= AD_REG( 7 downto  4);\r
-\r
-                               else    CONF_BAS_ADDR_REG( 7 downto  4) <= CONF_BAS_ADDR_REG( 7 downto  4);\r
-                       end if;\r
-\r
-\r
-               end if;\r
-\r
-       end process;\r
-\r
-       CONF_DATA_10H   <= CONF_BAS_ADDR_REG;\r
-\r
-end architecture CONFIG_10H_DESIGN;\r
-\r
-\r
-\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_10H.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_10H is
+       port
+       (
+       PCI_CLOCK                       :in             std_logic;
+       PCI_RSTn                        :in             std_logic;
+       AD_REG                          :in             std_logic_vector(31 downto 0);
+       CBE_REGn                        :in             std_logic_vector( 3 downto 0);
+       CONF_WR_10H             :in             std_logic;
+       CONF_DATA_10H   :out    std_logic_vector(31 downto 0)
+       );
+end entity CONFIG_10H;
+
+architecture CONFIG_10H_DESIGN of CONFIG_10H is
+
+       signal          CONF_BAS_ADDR_REG       :std_logic_vector(31 downto  0);
+
+begin
+
+--*******************************************************************
+--***** PCI Configuration Space Header "BASE ADDRESS REGISTER" ******
+--*******************************************************************
+
+       CONF_BAS_ADDR_REG(1 downto 0) <= "01"   ;-- Base Address Register for "I/O"
+       CONF_BAS_ADDR_REG(3 downto 2)   <= "00" ;-- IO Bereich = 16 BYTE
+
+       process (PCI_CLOCK,PCI_RSTn) 
+       begin
+
+--     if PCI_RSTn = '0' then  CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');
+               if PCI_RSTn = '0' then  CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');
+                                                               
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(3) = '0' then 
+
+                                                       CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
+
+                               else    CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);
+                       end if;
+
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(2) = '0' then 
+
+                                                       CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);
+
+                               else    CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);
+                       end if;
+
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(1) = '0' then 
+
+                                                       CONF_BAS_ADDR_REG(15 downto  8) <= AD_REG(15 downto  8);
+
+                               else    CONF_BAS_ADDR_REG(15 downto  8) <= CONF_BAS_ADDR_REG(15 downto  8);
+                       end if;
+
+--                     if                      CONF_WR_10H      = '1'and CBE_REGn(0) = '0' then 
+--
+--                                                     CONF_BAS_ADDR_REG( 7 downto  2) <= AD_REG( 7 downto  2);
+--
+--                             else    CONF_BAS_ADDR_REG( 7 downto  2) <= CONF_BAS_ADDR_REG( 7 downto  2);
+--                     end if;
+
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(0) = '0' then 
+
+                                                       CONF_BAS_ADDR_REG( 7 downto  4) <= AD_REG( 7 downto  4);
+
+                               else    CONF_BAS_ADDR_REG( 7 downto  4) <= CONF_BAS_ADDR_REG( 7 downto  4);
+                       end if;
+
+
+               end if;
+
+       end process;
+
+       CONF_DATA_10H   <= CONF_BAS_ADDR_REG;
+
+end architecture CONFIG_10H_DESIGN;
+
+
+

diff --git a/dhwk/source/config_3Ch.vhd b/dhwk/source/config_3Ch.vhd
index 1cc7f8077a3a34ac966c59e656475f3ac2ba2cf2..fd71b59e5084176c5ad61ded4214d9a6ac448ba9 100644 (file)
--- a/dhwk/source/config_3Ch.vhd
+++ b/dhwk/source/config_3Ch.vhd
@@ -1,59 +1,59 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_3CH.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_3CH is\r
-        port (\r
-                PCI_CLOCK      :in std_logic;\r
-                PCI_RSTn       :in std_logic;\r
-                AD_REG         :in std_logic_vector (31 downto 0);\r
-                CBE_REGn       :in std_logic_vector ( 3 downto 0);\r
-                CONF_WR_3CH    :in std_logic;\r
-                CONF_DATA_3CH  :out std_logic_vector (31 downto 0)\r
-        );\r
-end entity CONFIG_3CH;\r
-\r
-architecture CONFIG_3CH_DESIGN of CONFIG_3CH is\r
-\r
--- PCI Configuration Space Header Addr : HEX 3C --\r
-\r
-       signal CONF_MAX_LAT :std_logic_vector (31 downto 24);\r
-       signal CONF_MIN_GNT :std_logic_vector (23 downto 16);  \r
-       signal CONF_INT_PIN :std_logic_vector (15 downto  8);\r
-       signal CONF_INT_LINE :std_logic_vector ( 7 downto  0);  \r
-\r
-       constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011";\r
-begin \r
-\r
---*******************************************************************\r
---*********** PCI Configuration Space Header "INTERRUPT" ************\r
---*******************************************************************\r
-\r
-               CONF_MAX_LAT    <= X"00";\r
-               CONF_MIN_GNT    <= X"00";\r
---     CONF_INT_PIN    <= X"00";                               -- Interrupt -\r
-               CONF_INT_PIN    <= X"01";                               -- Interrupt A\r
---     CONF_INT_PIN    <= X"02";                               -- Interrupt B\r
---     CONF_INT_PIN    <= X"03";                               -- Interrupt C \r
---     CONF_INT_PIN    <= X"04";                               -- Interrupt D\r
---     CONF_INT_PIN    <= X"05 - FF0"; -- Reserviert\r
-\r
-process (PCI_CLOCK,PCI_RSTn) \r
-begin\r
-        if PCI_RSTn = '0' then\r
-                CONF_INT_LINE <= (others => '0');\r
-\r
-        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-                if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then \r
-                        CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);\r
-                end if;\r
-        end if;\r
-end process;\r
-\r
-CONF_DATA_3CH  <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;\r
-\r
-end architecture CONFIG_3CH_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_3CH.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_3CH is
+        port (
+                PCI_CLOCK      :in std_logic;
+                PCI_RSTn       :in std_logic;
+                AD_REG         :in std_logic_vector (31 downto 0);
+                CBE_REGn       :in std_logic_vector ( 3 downto 0);
+                CONF_WR_3CH    :in std_logic;
+                CONF_DATA_3CH  :out std_logic_vector (31 downto 0)
+        );
+end entity CONFIG_3CH;
+
+architecture CONFIG_3CH_DESIGN of CONFIG_3CH is
+
+-- PCI Configuration Space Header Addr : HEX 3C --
+
+       signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
+       signal CONF_MIN_GNT :std_logic_vector (23 downto 16);  
+       signal CONF_INT_PIN :std_logic_vector (15 downto  8);
+       signal CONF_INT_LINE :std_logic_vector ( 7 downto  0);  
+
+       constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011";
+begin 
+
+--*******************************************************************
+--*********** PCI Configuration Space Header "INTERRUPT" ************
+--*******************************************************************
+
+               CONF_MAX_LAT    <= X"00";
+               CONF_MIN_GNT    <= X"00";
+--     CONF_INT_PIN    <= X"00";                               -- Interrupt -
+               CONF_INT_PIN    <= X"01";                               -- Interrupt A
+--     CONF_INT_PIN    <= X"02";                               -- Interrupt B
+--     CONF_INT_PIN    <= X"03";                               -- Interrupt C 
+--     CONF_INT_PIN    <= X"04";                               -- Interrupt D
+--     CONF_INT_PIN    <= X"05 - FF0"; -- Reserviert
+
+process (PCI_CLOCK,PCI_RSTn) 
+begin
+        if PCI_RSTn = '0' then
+                CONF_INT_LINE <= (others => '0');
+
+        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then 
+                        CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
+                end if;
+        end if;
+end process;
+
+CONF_DATA_3CH  <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
+
+end architecture CONFIG_3CH_DESIGN;

diff --git a/dhwk/source/config_mux_0.vhd b/dhwk/source/config_mux_0.vhd
index 64e2560bc1ff786977651c383372193cbeb3f3fc..771b3d702eafae12b83f5e38a89f6d7382a9c898 100644 (file)
--- a/dhwk/source/config_mux_0.vhd
+++ b/dhwk/source/config_mux_0.vhd
@@ -1,44 +1,44 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_MUX_0.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_MUX_0 is\r
-       port\r
-       (\r
-       READ_SEL                        :in             std_logic_vector( 2 downto 0);\r
-       CONF_DATA_00H   :in             std_logic_vector(31 downto 0);\r
-       CONF_DATA_04H   :in             std_logic_vector(31 downto 0);\r
-       CONF_DATA_08H   :in             std_logic_vector(31 downto 0);\r
-       CONF_DATA_10H   :in             std_logic_vector(31 downto 0);\r
-       CONF_DATA_3CH   :in             std_logic_vector(31 downto 0);\r
---CONF_DATA_40H        :in             std_logic_vector(31 downto 0);\r
-       CONF_DATA                       :out    std_logic_vector(31 downto 0)\r
-    );\r
-end entity CONFIG_MUX_0;\r
-\r
-architecture CONFIG_MUX_0_DESIGN of CONFIG_MUX_0 is\r
-\r
-       signal  MUX     :std_logic_vector (31 downto  0); \r
-\r
-begin\r
-\r
---*******************************************************************\r
---******************* PCI Read  Config-MUX **************************\r
---*******************************************************************\r
-\r
-       MUX <=  CONF_DATA_00H   when READ_SEL <= "000" else \r
-                                       CONF_DATA_04H   when READ_SEL <= "001" else\r
-                                       CONF_DATA_08H   when READ_SEL <= "010" else\r
-                                       CONF_DATA_10H   when READ_SEL <= "011" else\r
-                                       CONF_DATA_3CH   when READ_SEL <= "100" else\r
---                             CONF_DATA_40H   when READ_SEL <= "101" else\r
-                                       X"00000000"     ;\r
-\r
-       CONF_DATA <= MUX ;\r
-\r
-\r
-end architecture CONFIG_MUX_0_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_MUX_0.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_MUX_0 is
+       port
+       (
+       READ_SEL                        :in             std_logic_vector( 2 downto 0);
+       CONF_DATA_00H   :in             std_logic_vector(31 downto 0);
+       CONF_DATA_04H   :in             std_logic_vector(31 downto 0);
+       CONF_DATA_08H   :in             std_logic_vector(31 downto 0);
+       CONF_DATA_10H   :in             std_logic_vector(31 downto 0);
+       CONF_DATA_3CH   :in             std_logic_vector(31 downto 0);
+--CONF_DATA_40H        :in             std_logic_vector(31 downto 0);
+       CONF_DATA                       :out    std_logic_vector(31 downto 0)
+    );
+end entity CONFIG_MUX_0;
+
+architecture CONFIG_MUX_0_DESIGN of CONFIG_MUX_0 is
+
+       signal  MUX     :std_logic_vector (31 downto  0); 
+
+begin
+
+--*******************************************************************
+--******************* PCI Read  Config-MUX **************************
+--*******************************************************************
+
+       MUX <=  CONF_DATA_00H   when READ_SEL <= "000" else 
+                                       CONF_DATA_04H   when READ_SEL <= "001" else
+                                       CONF_DATA_08H   when READ_SEL <= "010" else
+                                       CONF_DATA_10H   when READ_SEL <= "011" else
+                                       CONF_DATA_3CH   when READ_SEL <= "100" else
+--                             CONF_DATA_40H   when READ_SEL <= "101" else
+                                       X"00000000"     ;
+
+       CONF_DATA <= MUX ;
+
+
+end architecture CONFIG_MUX_0_DESIGN;

diff --git a/dhwk/source/config_rd_0.vhd b/dhwk/source/config_rd_0.vhd
index 1b19b633ffc988b74af151ab70e7a31225b46d4c..42f9d247adeac63ed880d5555b8d9e75b54835a0 100644 (file)
--- a/dhwk/source/config_rd_0.vhd
+++ b/dhwk/source/config_rd_0.vhd
@@ -1,122 +1,122 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_RD_0.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_RD_0 is\r
-    port\r
-       (\r
-       ADDR_REG        :in             std_logic_vector (31 downto 0);\r
-       CF_RD_COM       :in             std_logic;\r
-       READ_SEL        :out    std_logic_vector ( 2 downto 0)\r
-    );\r
-end entity CONFIG_RD_0;\r
-\r
-architecture CONFIG_RD_0_DESIGN of CONFIG_RD_0 is\r
-\r
---\r
---\r
---\r
---\r
---\r
---                            PCI Configuration Space Header\r
---\r
---            \                        Bit\r
---                        \\r
---Address              |31               24|23           16|15            8|7             0|      \r
------------------------------------------------------------------\r
---00                   |Device ID                              |Vendor ID                              |                                       \r
---04                   |Status                                 |Command                                |\r
---08                   |Class Code                                                     |Revision ID|\r
---0C                   |BIST           |Header Type|Latency T. |Cache L.S.     |\r
---10-24                        |Base Address Register                                                  |\r
---28                   |Cardbus CIS Pointer                                                    |\r
---2C                   |Subsystem ID                   |Subsystem Vendor ID    |\r
---30                   |Expansion ROM Base Address                                             |\r
---34                   |Reserved                                                                               |\r
---38                   |Reserved                                                                               |\r
---3C                   |Max_Lat        |Min_Gnt        |Int_Pin        |Int_Line       |\r
---40-FF                        |                                                                                               |\r
------------------------------------------------------------------\r
-\r
-\r
---PCI Bus Commands \r
---C/BE[3..0] Command Type\r
---------------------------------------\r
---     0000            Interrupt Acknowledge\r
---     0001            Special Cycle\r
---     0010            I/O Read\r
---     0011            I/O Write\r
---     0100            Reserved\r
---     0101            Reserved\r
---     0110            Memory Read\r
---     0111            Memory Write\r
---\r
---     1000            Reserved\r
---     1001            Reserved\r
---     1010            Configuration Read\r
---     1011            Configuration Write\r
---     1100            Memory Read Multiple \r
---     1101            Dual Address Cycle\r
---     1110            Memory Read Line\r
---     1111            Memory Write and Invalidate\r
-\r
-\r
---PCI Byte Enable \r
---C/BE[3..0] gueltige Datenbits \r
--------------------------------\r
---     0000            AD 31..0\r
---     1000            AD 23..0\r
---     1100            AD 15..0\r
---     1110            AD  7..0\r
-\r
-       constant        CMD_INT_ACK                     :std_logic_vector(3 downto 0) := "0000";\r
-       constant        CMD_SP_CYC                      :std_logic_vector(3 downto 0) := "0001";\r
-       constant        CMD_IO_READ                     :std_logic_vector(3 downto 0) := "0010";\r
-       constant        CMD_IO_WRITE            :std_logic_vector(3 downto 0) := "0011";\r
-       constant        CMD_RES_4                               :std_logic_vector(3 downto 0) := "0100";\r
-       constant        CMD_RES_5                               :std_logic_vector(3 downto 0) := "0101";\r
-       constant        CMD_MEM_READ            :std_logic_vector(3 downto 0) := "0110";\r
-       constant        CMD_MEM_WRITE           :std_logic_vector(3 downto 0) := "0111";\r
-       constant        CMD_RES_8                               :std_logic_vector(3 downto 0) := "1000";\r
-       constant        CMD_RES_9                               :std_logic_vector(3 downto 0) := "1001";\r
-       constant        CMD_CONF_READ           :std_logic_vector(3 downto 0) := "1010";\r
-       constant        CMD_CONF_WRITE  :std_logic_vector(3 downto 0) := "1011";\r
-       constant        CMD_MEM_READ_M  :std_logic_vector(3 downto 0) := "1100";\r
-       constant        CMD_DU_ADR_CYC  :std_logic_vector(3 downto 0) := "1101";\r
-       constant        CMD_MEN_READ_L  :std_logic_vector(3 downto 0) := "1110";\r
-       constant        CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";\r
-\r
-       signal          MUX                                                     :std_logic_vector(31 downto 0); \r
-       signal          CONFIG_ADDR                     :std_logic_vector( 7 downto 0); \r
-\r
-begin\r
-\r
-       CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);\r
-\r
---*******************************************************************\r
---*********************** PCI Read Address **************************\r
---*******************************************************************\r
-\r
-       process (CF_RD_COM, CONFIG_ADDR) \r
-       begin\r
-\r
-               if      CF_RD_COM = '1' then\r
-\r
-                       if              CONFIG_ADDR = X"00"     then    READ_SEL <= "000";\r
-                       elsif   CONFIG_ADDR = X"04"     then    READ_SEL <= "001";\r
-                       elsif   CONFIG_ADDR = X"08"     then    READ_SEL <= "010";\r
-                       elsif   CONFIG_ADDR = X"10"     then    READ_SEL <= "011";\r
-                       elsif   CONFIG_ADDR = X"3C"     then    READ_SEL <= "100";\r
-                       elsif   CONFIG_ADDR = X"40"     then    READ_SEL <= "101";\r
-                       else                                                            READ_SEL <= "111";\r
-                       end if;\r
-               else                                                                    READ_SEL <= "111";\r
-               end if;\r
-       end process;\r
-\r
-end architecture CONFIG_RD_0_DESIGN;\r
-\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_RD_0.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_RD_0 is
+    port
+       (
+       ADDR_REG        :in             std_logic_vector (31 downto 0);
+       CF_RD_COM       :in             std_logic;
+       READ_SEL        :out    std_logic_vector ( 2 downto 0)
+    );
+end entity CONFIG_RD_0;
+
+architecture CONFIG_RD_0_DESIGN of CONFIG_RD_0 is
+
+--
+--
+--
+--
+--
+--                            PCI Configuration Space Header
+--
+--            \                        Bit
+--                        \
+--Address              |31               24|23           16|15            8|7             0|      
+-----------------------------------------------------------------
+--00                   |Device ID                              |Vendor ID                              |                                       
+--04                   |Status                                 |Command                                |
+--08                   |Class Code                                                     |Revision ID|
+--0C                   |BIST           |Header Type|Latency T. |Cache L.S.     |
+--10-24                        |Base Address Register                                                  |
+--28                   |Cardbus CIS Pointer                                                    |
+--2C                   |Subsystem ID                   |Subsystem Vendor ID    |
+--30                   |Expansion ROM Base Address                                             |
+--34                   |Reserved                                                                               |
+--38                   |Reserved                                                                               |
+--3C                   |Max_Lat        |Min_Gnt        |Int_Pin        |Int_Line       |
+--40-FF                        |                                                                                               |
+-----------------------------------------------------------------
+
+
+--PCI Bus Commands 
+--C/BE[3..0] Command Type
+--------------------------------------
+--     0000            Interrupt Acknowledge
+--     0001            Special Cycle
+--     0010            I/O Read
+--     0011            I/O Write
+--     0100            Reserved
+--     0101            Reserved
+--     0110            Memory Read
+--     0111            Memory Write
+--
+--     1000            Reserved
+--     1001            Reserved
+--     1010            Configuration Read
+--     1011            Configuration Write
+--     1100            Memory Read Multiple 
+--     1101            Dual Address Cycle
+--     1110            Memory Read Line
+--     1111            Memory Write and Invalidate
+
+
+--PCI Byte Enable 
+--C/BE[3..0] gueltige Datenbits 
+-------------------------------
+--     0000            AD 31..0
+--     1000            AD 23..0
+--     1100            AD 15..0
+--     1110            AD  7..0
+
+       constant        CMD_INT_ACK                     :std_logic_vector(3 downto 0) := "0000";
+       constant        CMD_SP_CYC                      :std_logic_vector(3 downto 0) := "0001";
+       constant        CMD_IO_READ                     :std_logic_vector(3 downto 0) := "0010";
+       constant        CMD_IO_WRITE            :std_logic_vector(3 downto 0) := "0011";
+       constant        CMD_RES_4                               :std_logic_vector(3 downto 0) := "0100";
+       constant        CMD_RES_5                               :std_logic_vector(3 downto 0) := "0101";
+       constant        CMD_MEM_READ            :std_logic_vector(3 downto 0) := "0110";
+       constant        CMD_MEM_WRITE           :std_logic_vector(3 downto 0) := "0111";
+       constant        CMD_RES_8                               :std_logic_vector(3 downto 0) := "1000";
+       constant        CMD_RES_9                               :std_logic_vector(3 downto 0) := "1001";
+       constant        CMD_CONF_READ           :std_logic_vector(3 downto 0) := "1010";
+       constant        CMD_CONF_WRITE  :std_logic_vector(3 downto 0) := "1011";
+       constant        CMD_MEM_READ_M  :std_logic_vector(3 downto 0) := "1100";
+       constant        CMD_DU_ADR_CYC  :std_logic_vector(3 downto 0) := "1101";
+       constant        CMD_MEN_READ_L  :std_logic_vector(3 downto 0) := "1110";
+       constant        CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";
+
+       signal          MUX                                                     :std_logic_vector(31 downto 0); 
+       signal          CONFIG_ADDR                     :std_logic_vector( 7 downto 0); 
+
+begin
+
+       CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
+
+--*******************************************************************
+--*********************** PCI Read Address **************************
+--*******************************************************************
+
+       process (CF_RD_COM, CONFIG_ADDR) 
+       begin
+
+               if      CF_RD_COM = '1' then
+
+                       if              CONFIG_ADDR = X"00"     then    READ_SEL <= "000";
+                       elsif   CONFIG_ADDR = X"04"     then    READ_SEL <= "001";
+                       elsif   CONFIG_ADDR = X"08"     then    READ_SEL <= "010";
+                       elsif   CONFIG_ADDR = X"10"     then    READ_SEL <= "011";
+                       elsif   CONFIG_ADDR = X"3C"     then    READ_SEL <= "100";
+                       elsif   CONFIG_ADDR = X"40"     then    READ_SEL <= "101";
+                       else                                                            READ_SEL <= "111";
+                       end if;
+               else                                                                    READ_SEL <= "111";
+               end if;
+       end process;
+
+end architecture CONFIG_RD_0_DESIGN;
+

diff --git a/dhwk/source/config_space_header.vhd b/dhwk/source/config_space_header.vhd
index 8f6160209568aaf71fa6384af07674f722a04296..4e3092d158440fc9ef089321ca2f4bb5b6bc83e5 100644 (file)
--- a/dhwk/source/config_space_header.vhd
+++ b/dhwk/source/config_space_header.vhd
@@ -1,157 +1,157 @@
--- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007\r
-\r
-\r
-\r
-LIBRARY ieee;\r
-\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-\r
-entity CONFIG_SPACE_HEADER is\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             ADDR_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-             CF_RD_COM : In    std_logic;\r
-             CF_WR_COM : In    std_logic;\r
-             IRDY_REGn : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-                PERR : In    std_logic;\r
-             REVISION_ID : In    std_logic_vector (7 downto 0);\r
-                SERR : In    std_logic;\r
-               TRDYn : In    std_logic;\r
-             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
-             CONF_DATA : Out   std_logic_vector (31 downto 0);\r
-             CONF_DATA_04H : Out   std_logic_vector (31 downto 0);\r
-             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );\r
-end CONFIG_SPACE_HEADER;\r
-\r
-architecture SCHEMATIC of CONFIG_SPACE_HEADER is\r
-\r
-   SIGNAL gnd : std_logic := '0';\r
-   SIGNAL vcc : std_logic := '1';\r
-\r
-   signal CONF_WR_04H : std_logic;\r
-   signal CONF_WR_10H : std_logic;\r
-   signal CONF_WR_3CH : std_logic;\r
-   signal CONF_READ_SEL : std_logic_vector (2 downto 0);\r
-   signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);\r
-   signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);\r
-   signal CONF_DATA_3CH : std_logic_vector (31 downto 0);\r
-   signal CONF_DATA_08H : std_logic_vector (31 downto 0);\r
-   signal CONF_DATA_00H : std_logic_vector (31 downto 0);\r
-\r
-   component CONFIG_MUX_0\r
-      Port ( CONF_DATA_00H : In    std_logic_vector (31 downto 0);\r
-             CONF_DATA_04H : In    std_logic_vector (31 downto 0);\r
-             CONF_DATA_08H : In    std_logic_vector (31 downto 0);\r
-             CONF_DATA_10H : In    std_logic_vector (31 downto 0);\r
-             CONF_DATA_3CH : In    std_logic_vector (31 downto 0);\r
-             READ_SEL : In    std_logic_vector (2 downto 0);\r
-             CONF_DATA : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-   component CONFIG_RD_0\r
-      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);\r
-             CF_RD_COM : In    std_logic;\r
-             READ_SEL : Out   std_logic_vector (2 downto 0) );\r
-   end component;\r
-\r
-   component CONFIG_WR_0\r
-      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);\r
-             CF_WR_COM : In    std_logic;\r
-             IRDY_REGn : In    std_logic;\r
-               TRDYn : In    std_logic;\r
-             CONF_WR_04H : Out   std_logic;\r
-             CONF_WR_10H : Out   std_logic;\r
-             CONF_WR_3CH : Out   std_logic );\r
-   end component;\r
-\r
-   component CONFIG_3CH\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-             CONF_WR_3CH : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             CONF_DATA_3CH : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-   component CONFIG_10H\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-             CONF_WR_10H : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-   component CONFIG_08H\r
-      Port ( REVISION_ID : In    std_logic_vector (7 downto 0);\r
-             CONF_DATA_08H : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-   component CONFIG_00H\r
-      Port ( VENDOR_ID : In    std_logic_vector (15 downto 0);\r
-             CONF_DATA_00H : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-   component CONFIG_04H\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-             CONF_WR_04H : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-                PERR : In    std_logic;\r
-                SERR : In    std_logic;\r
-             CONF_DATA_04H : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-begin\r
-\r
-   CONF_DATA_04H <= CONF_DATA_04H_DUMMY;\r
-   CONF_DATA_10H <= CONF_DATA_10H_DUMMY;\r
-\r
-   I10 : CONFIG_MUX_0\r
-      Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),\r
-                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),\r
-                 CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),\r
-                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),\r
-                 CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),\r
-                 READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),\r
-                 CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );\r
-   I9 : CONFIG_RD_0\r
-      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
-                 CF_RD_COM=>CF_RD_COM,\r
-                 READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );\r
-   I8 : CONFIG_WR_0\r
-      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
-                 CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,\r
-                 TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,\r
-                 CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );\r
-   I6 : CONFIG_3CH\r
-      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
-                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
-                 CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,\r
-                 PCI_RSTn=>PCI_RSTn,\r
-                 CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );\r
-   I5 : CONFIG_10H\r
-      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
-                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
-                 CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,\r
-                 PCI_RSTn=>PCI_RSTn,\r
-                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );\r
-   I4 : CONFIG_08H\r
-      Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),\r
-                 CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );\r
-   I3 : CONFIG_00H\r
-      Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
-                 CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );\r
-   I2 : CONFIG_04H\r
-      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
-                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
-                 CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,\r
-                 PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,\r
-                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );\r
-\r
-end SCHEMATIC;\r
+-- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007
+
+
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity CONFIG_SPACE_HEADER is
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             ADDR_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+             CF_RD_COM : In    std_logic;
+             CF_WR_COM : In    std_logic;
+             IRDY_REGn : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+                PERR : In    std_logic;
+             REVISION_ID : In    std_logic_vector (7 downto 0);
+                SERR : In    std_logic;
+               TRDYn : In    std_logic;
+             VENDOR_ID : In    std_logic_vector (15 downto 0);
+             CONF_DATA : Out   std_logic_vector (31 downto 0);
+             CONF_DATA_04H : Out   std_logic_vector (31 downto 0);
+             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );
+end CONFIG_SPACE_HEADER;
+
+architecture SCHEMATIC of CONFIG_SPACE_HEADER is
+
+   SIGNAL gnd : std_logic := '0';
+   SIGNAL vcc : std_logic := '1';
+
+   signal CONF_WR_04H : std_logic;
+   signal CONF_WR_10H : std_logic;
+   signal CONF_WR_3CH : std_logic;
+   signal CONF_READ_SEL : std_logic_vector (2 downto 0);
+   signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);
+   signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
+   signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
+   signal CONF_DATA_08H : std_logic_vector (31 downto 0);
+   signal CONF_DATA_00H : std_logic_vector (31 downto 0);
+
+   component CONFIG_MUX_0
+      Port ( CONF_DATA_00H : In    std_logic_vector (31 downto 0);
+             CONF_DATA_04H : In    std_logic_vector (31 downto 0);
+             CONF_DATA_08H : In    std_logic_vector (31 downto 0);
+             CONF_DATA_10H : In    std_logic_vector (31 downto 0);
+             CONF_DATA_3CH : In    std_logic_vector (31 downto 0);
+             READ_SEL : In    std_logic_vector (2 downto 0);
+             CONF_DATA : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+   component CONFIG_RD_0
+      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);
+             CF_RD_COM : In    std_logic;
+             READ_SEL : Out   std_logic_vector (2 downto 0) );
+   end component;
+
+   component CONFIG_WR_0
+      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);
+             CF_WR_COM : In    std_logic;
+             IRDY_REGn : In    std_logic;
+               TRDYn : In    std_logic;
+             CONF_WR_04H : Out   std_logic;
+             CONF_WR_10H : Out   std_logic;
+             CONF_WR_3CH : Out   std_logic );
+   end component;
+
+   component CONFIG_3CH
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+             CONF_WR_3CH : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             CONF_DATA_3CH : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+   component CONFIG_10H
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+             CONF_WR_10H : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+   component CONFIG_08H
+      Port ( REVISION_ID : In    std_logic_vector (7 downto 0);
+             CONF_DATA_08H : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+   component CONFIG_00H
+      Port ( VENDOR_ID : In    std_logic_vector (15 downto 0);
+             CONF_DATA_00H : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+   component CONFIG_04H
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+             CONF_WR_04H : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+                PERR : In    std_logic;
+                SERR : In    std_logic;
+             CONF_DATA_04H : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+begin
+
+   CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
+   CONF_DATA_10H <= CONF_DATA_10H_DUMMY;
+
+   I10 : CONFIG_MUX_0
+      Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),
+                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),
+                 CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),
+                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),
+                 CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),
+                 READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),
+                 CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );
+   I9 : CONFIG_RD_0
+      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+                 CF_RD_COM=>CF_RD_COM,
+                 READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );
+   I8 : CONFIG_WR_0
+      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+                 CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
+                 TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
+                 CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
+   I6 : CONFIG_3CH
+      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+                 CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,
+                 PCI_RSTn=>PCI_RSTn,
+                 CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );
+   I5 : CONFIG_10H
+      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+                 CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,
+                 PCI_RSTn=>PCI_RSTn,
+                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );
+   I4 : CONFIG_08H
+      Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),
+                 CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );
+   I3 : CONFIG_00H
+      Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
+                 CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );
+   I2 : CONFIG_04H
+      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+                 CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,
+                 PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,
+                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );
+
+end SCHEMATIC;

diff --git a/dhwk/source/config_wr_0.vhd b/dhwk/source/config_wr_0.vhd
index 4c7b96c195a631479553ce4e3e8581ebfe4bb3ed..2df596dd694b4f463cde436c5b3817f1cec8bc5f 100644 (file)
--- a/dhwk/source/config_wr_0.vhd
+++ b/dhwk/source/config_wr_0.vhd
@@ -1,139 +1,139 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONFIG_WR_0.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity CONFIG_WR_0 is\r
-    port\r
-       (\r
-       ADDR_REG                        :in             std_logic_vector(31 downto 0);\r
-       CF_WR_COM                       :in             std_logic;\r
-       IRDY_REGn                       :in             std_logic;\r
-       TRDYn                                   :in             std_logic;\r
-       CONF_WR_04H             :out    std_logic; \r
-       CONF_WR_10H             :out    std_logic; \r
-       CONF_WR_3CH             :out    std_logic\r
---CONF_WR_40H          :out    std_logic \r
-    );\r
-end entity CONFIG_WR_0;\r
-\r
-architecture CONFIG_WR_0_DESIGN of CONFIG_WR_0 is\r
-\r
---\r
---\r
---\r
---\r
---\r
---                            PCI Configuration Space Header\r
---\r
---       \                        Bit\r
---                       \\r
---Address      |31                                     24|23                             16|15                    8|7                           0|      \r
------------------------------------------------------------------\r
---00                   |Device ID                                                                      |Vendor ID                                                      |                                       \r
---04                   |Status                                                                                 |Command                                                                |\r
---08                   |Class Code                                                                     |Revision ID                                            |\r
---0C                   |BIST                           |Header Type            |Latency T.     |Cache L.S.     |\r
---10-24                |Base Address Register                                                                                                                  |\r
---28                   |Cardbus CIS Pointer                                                                                                                            |\r
---2C                   |Subsystem ID                                                           |Subsystem Vendor ID            |\r
---30                   |Expansion ROM Base Address                                                                                                     |\r
---34                   |Reserved                                                                                                                                                                               |\r
---38                   |Reserved                                                                                                                                                                               |\r
---3C                   |Max_Lat                |Min_Gnt                                |Int_Pin                |Int_Line               |\r
---40-FF                |                                                                                                                                                                                                               |\r
------------------------------------------------------------------\r
-\r
-\r
---PCI Bus Commands \r
---C/BE[3..0] Command Type\r
---------------------------------------\r
---     0000            Interrupt Acknowledge\r
---     0001            Special Cycle\r
---     0010            I/O Read\r
---     0011            I/O Write\r
---     0100            Reserved\r
---     0101            Reserved\r
---     0110            Memory Read\r
---     0111            Memory Write\r
---\r
---     1000            Reserved\r
---     1001            Reserved\r
---     1010            Configuration Read\r
---     1011            Configuration Write\r
---     1100            Memory Read Multiple \r
---     1101            Dual Address Cycle\r
---     1110            Memory Read Line\r
---     1111            Memory Write and Invalidate\r
-\r
-\r
---PCI Byte Enable \r
---C/BE[3..0] gueltige Datenbits \r
--------------------------------\r
---     0000            AD 31..0\r
---     1000            AD 23..0\r
---     1100            AD 15..0\r
---     1110            AD  7..0\r
-\r
-       constant        CMD_INT_ACK                     :std_logic_vector(3 downto 0) := "0000";\r
-       constant        CMD_SP_CYC                      :std_logic_vector(3 downto 0) := "0001";\r
-       constant        CMD_IO_READ                     :std_logic_vector(3 downto 0) := "0010";\r
-       constant        CMD_IO_WRITE            :std_logic_vector(3 downto 0) := "0011";\r
-       constant        CMD_RES_4                               :std_logic_vector(3 downto 0) := "0100";\r
-       constant        CMD_RES_5                               :std_logic_vector(3 downto 0) := "0101";\r
-       constant        CMD_MEM_READ            :std_logic_vector(3 downto 0) := "0110";\r
-       constant        CMD_MEM_WRITE           :std_logic_vector(3 downto 0) := "0111";\r
-       constant        CMD_RES_8                               :std_logic_vector(3 downto 0) := "1000";\r
-       constant        CMD_RES_9                               :std_logic_vector(3 downto 0) := "1001";\r
-       constant        CMD_CONF_READ           :std_logic_vector(3 downto 0) := "1010";\r
-       constant        CMD_CONF_WRITE  :std_logic_vector(3 downto 0) := "1011";\r
-       constant        CMD_MEM_READ_M  :std_logic_vector(3 downto 0) := "1100";\r
-       constant        CMD_DU_ADR_CYC  :std_logic_vector(3 downto 0) := "1101";\r
-       constant        CMD_MEN_READ_L  :std_logic_vector(3 downto 0) := "1110";\r
-       constant        CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";\r
-\r
-       signal          CONFIG_ADDR :std_logic_vector(7 downto 0); \r
-       signal          CONFIG_WRITE :std_logic_vector(3 downto 0); \r
-\r
-\r
-begin\r
-\r
---*******************************************************************\r
---******************* PCI Write Configuration Address ***************\r
---*******************************************************************\r
-\r
-       CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);\r
-\r
-\r
-       process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR) \r
-       begin\r
-\r
-               if      CF_WR_COM = '1' and     IRDY_REGn = '0' and     TRDYn = '0'     then\r
-\r
-                       if CONFIG_ADDR = X"04" then\r
-                                CONFIG_WRITE   <= "0001";\r
-\r
-                        elsif CONFIG_ADDR = X"10" then\r
-                                CONFIG_WRITE   <= "0010";\r
-\r
-                        elsif  CONFIG_ADDR = X"3C" then\r
-                                CONFIG_WRITE   <= "0100";\r
-\r
---                     elsif   CONFIG_ADDR = X"40"     then    CONFIG_WRITE    <= "1000";\r
-                        else\r
-                                CONFIG_WRITE   <= "0000";\r
-                       end if;\r
-               else            \r
-                        CONFIG_WRITE   <= "0000";\r
-               end if;\r
-       end process;\r
-\r
-       CONF_WR_04H     <=      CONFIG_WRITE(0); \r
-       CONF_WR_10H     <=      CONFIG_WRITE(1);         \r
-       CONF_WR_3CH     <=      CONFIG_WRITE(2);        \r
---CONF_WR_40H  <=      CONFIG_WRITE(3);        \r
-\r
-end architecture CONFIG_WR_0_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONFIG_WR_0.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity CONFIG_WR_0 is
+    port
+       (
+       ADDR_REG                        :in             std_logic_vector(31 downto 0);
+       CF_WR_COM                       :in             std_logic;
+       IRDY_REGn                       :in             std_logic;
+       TRDYn                                   :in             std_logic;
+       CONF_WR_04H             :out    std_logic; 
+       CONF_WR_10H             :out    std_logic; 
+       CONF_WR_3CH             :out    std_logic
+--CONF_WR_40H          :out    std_logic 
+    );
+end entity CONFIG_WR_0;
+
+architecture CONFIG_WR_0_DESIGN of CONFIG_WR_0 is
+
+--
+--
+--
+--
+--
+--                            PCI Configuration Space Header
+--
+--       \                        Bit
+--                       \
+--Address      |31                                     24|23                             16|15                    8|7                           0|      
+-----------------------------------------------------------------
+--00                   |Device ID                                                                      |Vendor ID                                                      |                                       
+--04                   |Status                                                                                 |Command                                                                |
+--08                   |Class Code                                                                     |Revision ID                                            |
+--0C                   |BIST                           |Header Type            |Latency T.     |Cache L.S.     |
+--10-24                |Base Address Register                                                                                                                  |
+--28                   |Cardbus CIS Pointer                                                                                                                            |
+--2C                   |Subsystem ID                                                           |Subsystem Vendor ID            |
+--30                   |Expansion ROM Base Address                                                                                                     |
+--34                   |Reserved                                                                                                                                                                               |
+--38                   |Reserved                                                                                                                                                                               |
+--3C                   |Max_Lat                |Min_Gnt                                |Int_Pin                |Int_Line               |
+--40-FF                |                                                                                                                                                                                                               |
+-----------------------------------------------------------------
+
+
+--PCI Bus Commands 
+--C/BE[3..0] Command Type
+--------------------------------------
+--     0000            Interrupt Acknowledge
+--     0001            Special Cycle
+--     0010            I/O Read
+--     0011            I/O Write
+--     0100            Reserved
+--     0101            Reserved
+--     0110            Memory Read
+--     0111            Memory Write
+--
+--     1000            Reserved
+--     1001            Reserved
+--     1010            Configuration Read
+--     1011            Configuration Write
+--     1100            Memory Read Multiple 
+--     1101            Dual Address Cycle
+--     1110            Memory Read Line
+--     1111            Memory Write and Invalidate
+
+
+--PCI Byte Enable 
+--C/BE[3..0] gueltige Datenbits 
+-------------------------------
+--     0000            AD 31..0
+--     1000            AD 23..0
+--     1100            AD 15..0
+--     1110            AD  7..0
+
+       constant        CMD_INT_ACK                     :std_logic_vector(3 downto 0) := "0000";
+       constant        CMD_SP_CYC                      :std_logic_vector(3 downto 0) := "0001";
+       constant        CMD_IO_READ                     :std_logic_vector(3 downto 0) := "0010";
+       constant        CMD_IO_WRITE            :std_logic_vector(3 downto 0) := "0011";
+       constant        CMD_RES_4                               :std_logic_vector(3 downto 0) := "0100";
+       constant        CMD_RES_5                               :std_logic_vector(3 downto 0) := "0101";
+       constant        CMD_MEM_READ            :std_logic_vector(3 downto 0) := "0110";
+       constant        CMD_MEM_WRITE           :std_logic_vector(3 downto 0) := "0111";
+       constant        CMD_RES_8                               :std_logic_vector(3 downto 0) := "1000";
+       constant        CMD_RES_9                               :std_logic_vector(3 downto 0) := "1001";
+       constant        CMD_CONF_READ           :std_logic_vector(3 downto 0) := "1010";
+       constant        CMD_CONF_WRITE  :std_logic_vector(3 downto 0) := "1011";
+       constant        CMD_MEM_READ_M  :std_logic_vector(3 downto 0) := "1100";
+       constant        CMD_DU_ADR_CYC  :std_logic_vector(3 downto 0) := "1101";
+       constant        CMD_MEN_READ_L  :std_logic_vector(3 downto 0) := "1110";
+       constant        CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";
+
+       signal          CONFIG_ADDR :std_logic_vector(7 downto 0); 
+       signal          CONFIG_WRITE :std_logic_vector(3 downto 0); 
+
+
+begin
+
+--*******************************************************************
+--******************* PCI Write Configuration Address ***************
+--*******************************************************************
+
+       CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
+
+
+       process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR) 
+       begin
+
+               if      CF_WR_COM = '1' and     IRDY_REGn = '0' and     TRDYn = '0'     then
+
+                       if CONFIG_ADDR = X"04" then
+                                CONFIG_WRITE   <= "0001";
+
+                        elsif CONFIG_ADDR = X"10" then
+                                CONFIG_WRITE   <= "0010";
+
+                        elsif  CONFIG_ADDR = X"3C" then
+                                CONFIG_WRITE   <= "0100";
+
+--                     elsif   CONFIG_ADDR = X"40"     then    CONFIG_WRITE    <= "1000";
+                        else
+                                CONFIG_WRITE   <= "0000";
+                       end if;
+               else            
+                        CONFIG_WRITE   <= "0000";
+               end if;
+       end process;
+
+       CONF_WR_04H     <=      CONFIG_WRITE(0); 
+       CONF_WR_10H     <=      CONFIG_WRITE(1);         
+       CONF_WR_3CH     <=      CONFIG_WRITE(2);        
+--CONF_WR_40H  <=      CONFIG_WRITE(3);        
+
+end architecture CONFIG_WR_0_DESIGN;

diff --git a/dhwk/source/connecting_fsm.vhd b/dhwk/source/connecting_fsm.vhd
index ab8f54f3154d6540151980515974ad48409af1fc..c7e7340eec745eb9940addbf2b703213d397285e 100644 (file)
--- a/dhwk/source/connecting_fsm.vhd
+++ b/dhwk/source/connecting_fsm.vhd
@@ -1,136 +1,136 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: CONNECTING_FSM.VHD\r
-\r
-library ieee ;\r
-use ieee.std_logic_1164.all ;\r
-\r
-entity CONNECTING_FSM is\r
-       port\r
-       (\r
-       PCI_CLOCK                               :in             std_logic; \r
-       RESET                                           :in             std_logic; \r
-       PSC_ENABLE                      :in             std_logic;\r
-       SYNC_S_FIFO_EFn :in             std_logic;\r
-       SPC_ENABLE                      :in             std_logic;\r
-       SYNC_R_FIFO_FFn :in             std_logic;\r
-       S_FIFO_Q_OUT            :in             std_logic_vector(7 downto 0);\r
-       S_FIFO_READn            :out    std_logic;\r
-       R_FIFO_WRITEn           :out    std_logic;\r
-       R_FIFO_D_IN                     :out    std_logic_vector(7 downto 0) \r
-       );\r
-end entity CONNECTING_FSM;\r
-\r
-architecture CONNECTING_FSM_DESIGN of CONNECTING_FSM is\r
-\r
-       signal REG                                              :std_logic_vector(7 downto 0);\r
-       signal HELP_0,HELP_1    :std_logic;\r
-       signal SIG_LOAD                         :std_logic;\r
-\r
-\r
---**********************************************************\r
---***         CONNECTING FSM CODIERUNG                   ***\r
---**********************************************************\r
---\r
---\r
---                                                 ---------- HELP_0\r
---                                                      |--------- HELP_1   \r
---                                                      ||-------- LOAD   \r
---                                                        |||------- WRITE   \r
---                                                                                                                                                                                        ||||------ READ   \r
---                                                                                                                                                                                              |||||     \r
-       constant        S0      :std_logic_vector(4 downto 0)   :=      "00011";--\r
-       constant        S1      :std_logic_vector(4 downto 0)   :=      "01010";--READ\r
-       constant        S2      :std_logic_vector(4 downto 0) :=        "10010";--READ\r
-       constant        S3      :std_logic_vector(4 downto 0) :=        "11110";--READ,LOAD\r
-       constant        S4      :std_logic_vector(4 downto 0) :=        "11011";--\r
-       constant        S5      :std_logic_vector(4 downto 0) :=        "01001";--WRITE\r
-       constant        S6      :std_logic_vector(4 downto 0) :=        "10001";--WRITE\r
-       constant        S7      :std_logic_vector(4 downto 0) :=        "11001";--WRITE\r
-\r
-       signal STATES   :std_logic_vector(4 downto 0);\r
-\r
---************************************************************\r
---***             FSM SPEICHER-AUTOMAT                     ***\r
---************************************************************\r
-\r
-       attribute       syn_state_machine       :       boolean;\r
-       attribute       syn_state_machine       of      STATES  :       signal  is      false;\r
-\r
---************************************************************\r
---***                          REGISTER BESCHREIBUNG                  ***\r
---************************************************************\r
-\r
-begin\r
-\r
-       process (PCI_CLOCK) \r
-       begin\r
-               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then\r
-                       if                      SIG_LOAD        =       '1'     then    REG     <=      S_FIFO_Q_OUT;\r
-                               elsif   SIG_LOAD        =       '0'     then    REG     <=      REG;   \r
-                       end if;\r
-               end if;\r
-       end process;\r
-\r
---************************************************************\r
---***                          FSM BESCHREIBUNG                                 ***\r
---************************************************************\r
-\r
-       process (PCI_CLOCK)\r
-       begin  \r
-               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then\r
-  \r
-                       if      RESET   =       '1'     then    STATES <= S0;\r
-                               else\r
-  \r
-                                       case    STATES is\r
-\r
-                                       when    S0      => \r
-                                               if      PSC_ENABLE                      = '1'   and\r
-                                                               SPC_ENABLE                      =       '1'     and\r
-                                                               SYNC_S_FIFO_EFn =       '1'     then\r
-\r
-                                                                                               STATES  <=      S1;\r
-                                                       else  \r
-                                                                                               STATES  <=      S0;\r
-                                               end if;\r
-\r
-                                       when    S1      =>      STATES  <=      S2;\r
-                                       when    S2      =>      STATES  <=      S3;\r
-                                       when    S3      =>      STATES  <=      S4;\r
-\r
-                                       when    S4      => \r
-                                               if      SYNC_R_FIFO_FFn =       '1'     then\r
-\r
-                                                                                               STATES  <=      S5;\r
-                                               else  \r
-                               STATES  <=      S4;\r
-                                               end if;\r
-\r
-                                       when    S5      =>      STATES  <=      S6;\r
-                                       when    S6      =>      STATES  <=      S7;\r
-                                       when    S7      =>      STATES  <=      S0;\r
-\r
-                                       when others => \r
-\r
-                                                                                               STATES  <=      S0; \r
-\r
-                               end case;               -- STATES    \r
-                       end if;                         -- RESET \r
-               end if;                                 -- PCI_CLOCK   \r
-       end process;                    -- PROCESS\r
-\r
---************************************************************\r
---***          ZUWEISUNG       signal/out      <=      STATES             ***\r
---************************************************************\r
-\r
-       HELP_0                          <=      STATES(4);  \r
-       HELP_1                          <=      STATES(3);\r
-       SIG_LOAD                        <=      STATES(2);\r
-       R_FIFO_WRITEn   <=      STATES(1);\r
-       S_FIFO_READn    <=      STATES(0);\r
-\r
-       R_FIFO_D_IN             <=      REG;\r
-\r
-end architecture CONNECTING_FSM_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: CONNECTING_FSM.VHD
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity CONNECTING_FSM is
+       port
+       (
+       PCI_CLOCK                               :in             std_logic; 
+       RESET                                           :in             std_logic; 
+       PSC_ENABLE                      :in             std_logic;
+       SYNC_S_FIFO_EFn :in             std_logic;
+       SPC_ENABLE                      :in             std_logic;
+       SYNC_R_FIFO_FFn :in             std_logic;
+       S_FIFO_Q_OUT            :in             std_logic_vector(7 downto 0);
+       S_FIFO_READn            :out    std_logic;
+       R_FIFO_WRITEn           :out    std_logic;
+       R_FIFO_D_IN                     :out    std_logic_vector(7 downto 0) 
+       );
+end entity CONNECTING_FSM;
+
+architecture CONNECTING_FSM_DESIGN of CONNECTING_FSM is
+
+       signal REG                                              :std_logic_vector(7 downto 0);
+       signal HELP_0,HELP_1    :std_logic;
+       signal SIG_LOAD                         :std_logic;
+
+
+--**********************************************************
+--***         CONNECTING FSM CODIERUNG                   ***
+--**********************************************************
+--
+--
+--                                                 ---------- HELP_0
+--                                                      |--------- HELP_1   
+--                                                      ||-------- LOAD   
+--                                                        |||------- WRITE   
+--                                                                                                                                                                                        ||||------ READ   
+--                                                                                                                                                                                              |||||     
+       constant        S0      :std_logic_vector(4 downto 0)   :=      "00011";--
+       constant        S1      :std_logic_vector(4 downto 0)   :=      "01010";--READ
+       constant        S2      :std_logic_vector(4 downto 0) :=        "10010";--READ
+       constant        S3      :std_logic_vector(4 downto 0) :=        "11110";--READ,LOAD
+       constant        S4      :std_logic_vector(4 downto 0) :=        "11011";--
+       constant        S5      :std_logic_vector(4 downto 0) :=        "01001";--WRITE
+       constant        S6      :std_logic_vector(4 downto 0) :=        "10001";--WRITE
+       constant        S7      :std_logic_vector(4 downto 0) :=        "11001";--WRITE
+
+       signal STATES   :std_logic_vector(4 downto 0);
+
+--************************************************************
+--***             FSM SPEICHER-AUTOMAT                     ***
+--************************************************************
+
+       attribute       syn_state_machine       :       boolean;
+       attribute       syn_state_machine       of      STATES  :       signal  is      false;
+
+--************************************************************
+--***                          REGISTER BESCHREIBUNG                  ***
+--************************************************************
+
+begin
+
+       process (PCI_CLOCK) 
+       begin
+               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then
+                       if                      SIG_LOAD        =       '1'     then    REG     <=      S_FIFO_Q_OUT;
+                               elsif   SIG_LOAD        =       '0'     then    REG     <=      REG;   
+                       end if;
+               end if;
+       end process;
+
+--************************************************************
+--***                          FSM BESCHREIBUNG                                 ***
+--************************************************************
+
+       process (PCI_CLOCK)
+       begin  
+               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then
+  
+                       if      RESET   =       '1'     then    STATES <= S0;
+                               else
+  
+                                       case    STATES is
+
+                                       when    S0      => 
+                                               if      PSC_ENABLE                      = '1'   and
+                                                               SPC_ENABLE                      =       '1'     and
+                                                               SYNC_S_FIFO_EFn =       '1'     then
+
+                                                                                               STATES  <=      S1;
+                                                       else  
+                                                                                               STATES  <=      S0;
+                                               end if;
+
+                                       when    S1      =>      STATES  <=      S2;
+                                       when    S2      =>      STATES  <=      S3;
+                                       when    S3      =>      STATES  <=      S4;
+
+                                       when    S4      => 
+                                               if      SYNC_R_FIFO_FFn =       '1'     then
+
+                                                                                               STATES  <=      S5;
+                                               else  
+                               STATES  <=      S4;
+                                               end if;
+
+                                       when    S5      =>      STATES  <=      S6;
+                                       when    S6      =>      STATES  <=      S7;
+                                       when    S7      =>      STATES  <=      S0;
+
+                                       when others => 
+
+                                                                                               STATES  <=      S0; 
+
+                               end case;               -- STATES    
+                       end if;                         -- RESET 
+               end if;                                 -- PCI_CLOCK   
+       end process;                    -- PROCESS
+
+--************************************************************
+--***          ZUWEISUNG       signal/out      <=      STATES             ***
+--************************************************************
+
+       HELP_0                          <=      STATES(4);  
+       HELP_1                          <=      STATES(3);
+       SIG_LOAD                        <=      STATES(2);
+       R_FIFO_WRITEn   <=      STATES(1);
+       S_FIFO_READn    <=      STATES(0);
+
+       R_FIFO_D_IN             <=      REG;
+
+end architecture CONNECTING_FSM_DESIGN;

diff --git a/dhwk/source/fifo_control.vhd b/dhwk/source/fifo_control.vhd
index 1baa801b7199d5695ff8a884c4313e7aff210e99..58c25abfc4d483bd9d7e7d321be0e78166a6fbc9 100644 (file)
--- a/dhwk/source/fifo_control.vhd
+++ b/dhwk/source/fifo_control.vhd
@@ -1,172 +1,172 @@
--- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007\r
-\r
-\r
-\r
-LIBRARY ieee;\r
-\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-\r
-entity FIFO_CONTROL is\r
-      Port ( FIFO_RDn : In    std_logic;\r
-             FLAG_IN_0 : In    std_logic;\r
-             FLAG_IN_4 : In    std_logic;\r
-                HOLD : In    std_logic;\r
-             KONST_1 : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PSC_ENABLE : In    std_logic;\r
-               R_EFn : In    std_logic;\r
-               R_FFn : In    std_logic;\r
-               R_HFn : In    std_logic;\r
-               RESET : In    std_logic;\r
-               S_EFn : In    std_logic;\r
-               S_FFn : In    std_logic;\r
-             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
-               S_HFn : In    std_logic;\r
-             SERIAL_IN : In    std_logic;\r
-             SPC_ENABLE : In    std_logic;\r
-             SPC_RDY_IN : In    std_logic;\r
-             WRITE_XX1_0 : In    std_logic;\r
-             R_ERROR : Out   std_logic;\r
-             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
-             R_FIFO_READn : Out   std_logic;\r
-             R_FIFO_RESETn : Out   std_logic;\r
-             R_FIFO_RETRANSMITn : Out   std_logic;\r
-             R_FIFO_WRITEn : Out   std_logic;\r
-             RESERVE : Out   std_logic;\r
-             S_ERROR : Out   std_logic;\r
-             S_FIFO_READn : Out   std_logic;\r
-             S_FIFO_RESETn : Out   std_logic;\r
-             S_FIFO_RETRANSMITn : Out   std_logic;\r
-             S_FIFO_WRITEn : Out   std_logic;\r
-             SERIAL_OUT : Out   std_logic;\r
-             SPC_RDY_OUT : Out   std_logic;\r
-             SR_ERROR : Out   std_logic;\r
-             SYNC_FLAG : Out   std_logic_vector (7 downto 0));\r
-end FIFO_CONTROL;\r
-\r
-architecture SCHEMATIC of FIFO_CONTROL is\r
-\r
-   SIGNAL gnd : std_logic := '0';\r
-   SIGNAL vcc : std_logic := '1';\r
-\r
-   signal XXXR_FIFO_WRITEn : std_logic;\r
-   signal XXXS_FIFO_READn : std_logic;\r
-   signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);\r
-   signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);\r
-\r
-   component SER_PAR_CON\r
-      Port ( PCI_CLOCK : In    std_logic;\r
-               RESET : In    std_logic;\r
-             SERIAL_IN : In    std_logic;\r
-             SPC_ENABLE : In    std_logic;\r
-             SYNC_R_FIFO_FFn : In    std_logic;\r
-             PAR_OUT : Out   std_logic_vector (7 downto 0);\r
-             R_FIFO_WRITEn : Out   std_logic;\r
-             SPC_RDY_OUT : Out   std_logic );\r
-   end component;\r
-\r
-   component PAR_SER_CON\r
-      Port (  PAR_IN : In    std_logic_vector (7 downto 0);\r
-             PCI_CLOCK : In    std_logic;\r
-             PSC_ENABLE : In    std_logic;\r
-               RESET : In    std_logic;\r
-             SPC_RDY_IN : In    std_logic;\r
-             SYNC_S_FIFO_EFn : In    std_logic;\r
-             S_FIFO_READn : Out   std_logic;\r
-             SER_OUT : Out   std_logic );\r
-   end component;\r
-\r
-   component FIFO_IO_CONTROL\r
-      Port ( FIFO_RDn : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-               RESET : In    std_logic;\r
-             SYNC_FLAG_1 : In    std_logic;\r
-             SYNC_FLAG_7 : In    std_logic;\r
-             WRITE_XX1_0 : In    std_logic;\r
-             R_ERROR : Out   std_logic;\r
-             R_FIFO_READn : Out   std_logic;\r
-             R_FIFO_RESETn : Out   std_logic;\r
-             R_FIFO_RETRANSMITn : Out   std_logic;\r
-             S_ERROR : Out   std_logic;\r
-             S_FIFO_RESETn : Out   std_logic;\r
-             S_FIFO_RETRANSMITn : Out   std_logic;\r
-             S_FIFO_WRITEn : Out   std_logic;\r
-             SR_ERROR : Out   std_logic );\r
-   end component;\r
-\r
-   component CONNECTING_FSM\r
-      Port ( PCI_CLOCK : In    std_logic;\r
-             PSC_ENABLE : In    std_logic;\r
-               RESET : In    std_logic;\r
-             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
-             SPC_ENABLE : In    std_logic;\r
-             SYNC_R_FIFO_FFn : In    std_logic;\r
-             SYNC_S_FIFO_EFn : In    std_logic;\r
-             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
-             R_FIFO_WRITEn : Out   std_logic;\r
-             S_FIFO_READn : Out   std_logic );\r
-   end component;\r
-\r
-   component FLAG_BUS\r
-      Port ( FLAG_IN_0 : In    std_logic;\r
-             FLAG_IN_4 : In    std_logic;\r
-                HOLD : In    std_logic;\r
-              KONS_1 : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-               R_EFn : In    std_logic;\r
-               R_FFn : In    std_logic;\r
-               R_HFn : In    std_logic;\r
-               S_EFn : In    std_logic;\r
-               S_FFn : In    std_logic;\r
-               S_HFn : In    std_logic;\r
-             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
-   end component;\r
-\r
-begin\r
-\r
-   SYNC_FLAG <= SYNC_FLAG_DUMMY;\r
-\r
-   RESERVE <= gnd;\r
-   I23 : SER_PAR_CON\r
-      Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
-                 SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,\r
-                 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
-                 PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
-                 R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );\r
-   I22 : PAR_SER_CON\r
-      Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
-                 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
-                 RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,\r
-                 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
-                 S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );\r
-   I21 : FIFO_IO_CONTROL\r
-      Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
-                 SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),\r
-                 SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),\r
-                 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
-                 R_FIFO_READn=>R_FIFO_READn,\r
-                 R_FIFO_RESETn=>R_FIFO_RESETn,\r
-                 R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,\r
-                 S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,\r
-                 S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,\r
-                 S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );\r
-   I20 : CONNECTING_FSM\r
-      Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
-                 RESET=>RESET,\r
-                 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
-                 SPC_ENABLE=>SPC_ENABLE,\r
-                 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
-                 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
-                 R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),\r
-                 R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,\r
-                 S_FIFO_READn=>XXXS_FIFO_READn );\r
-   I19 : FLAG_BUS\r
-      Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,\r
-                 KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,\r
-                 R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,\r
-                 S_HFn=>S_HFn,\r
-                 SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );\r
-\r
-end SCHEMATIC;\r
+-- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007
+
+
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity FIFO_CONTROL is
+      Port ( FIFO_RDn : In    std_logic;
+             FLAG_IN_0 : In    std_logic;
+             FLAG_IN_4 : In    std_logic;
+                HOLD : In    std_logic;
+             KONST_1 : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PSC_ENABLE : In    std_logic;
+               R_EFn : In    std_logic;
+               R_FFn : In    std_logic;
+               R_HFn : In    std_logic;
+               RESET : In    std_logic;
+               S_EFn : In    std_logic;
+               S_FFn : In    std_logic;
+             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);
+               S_HFn : In    std_logic;
+             SERIAL_IN : In    std_logic;
+             SPC_ENABLE : In    std_logic;
+             SPC_RDY_IN : In    std_logic;
+             WRITE_XX1_0 : In    std_logic;
+             R_ERROR : Out   std_logic;
+             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);
+             R_FIFO_READn : Out   std_logic;
+             R_FIFO_RESETn : Out   std_logic;
+             R_FIFO_RETRANSMITn : Out   std_logic;
+             R_FIFO_WRITEn : Out   std_logic;
+             RESERVE : Out   std_logic;
+             S_ERROR : Out   std_logic;
+             S_FIFO_READn : Out   std_logic;
+             S_FIFO_RESETn : Out   std_logic;
+             S_FIFO_RETRANSMITn : Out   std_logic;
+             S_FIFO_WRITEn : Out   std_logic;
+             SERIAL_OUT : Out   std_logic;
+             SPC_RDY_OUT : Out   std_logic;
+             SR_ERROR : Out   std_logic;
+             SYNC_FLAG : Out   std_logic_vector (7 downto 0));
+end FIFO_CONTROL;
+
+architecture SCHEMATIC of FIFO_CONTROL is
+
+   SIGNAL gnd : std_logic := '0';
+   SIGNAL vcc : std_logic := '1';
+
+   signal XXXR_FIFO_WRITEn : std_logic;
+   signal XXXS_FIFO_READn : std_logic;
+   signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);
+   signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);
+
+   component SER_PAR_CON
+      Port ( PCI_CLOCK : In    std_logic;
+               RESET : In    std_logic;
+             SERIAL_IN : In    std_logic;
+             SPC_ENABLE : In    std_logic;
+             SYNC_R_FIFO_FFn : In    std_logic;
+             PAR_OUT : Out   std_logic_vector (7 downto 0);
+             R_FIFO_WRITEn : Out   std_logic;
+             SPC_RDY_OUT : Out   std_logic );
+   end component;
+
+   component PAR_SER_CON
+      Port (  PAR_IN : In    std_logic_vector (7 downto 0);
+             PCI_CLOCK : In    std_logic;
+             PSC_ENABLE : In    std_logic;
+               RESET : In    std_logic;
+             SPC_RDY_IN : In    std_logic;
+             SYNC_S_FIFO_EFn : In    std_logic;
+             S_FIFO_READn : Out   std_logic;
+             SER_OUT : Out   std_logic );
+   end component;
+
+   component FIFO_IO_CONTROL
+      Port ( FIFO_RDn : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+               RESET : In    std_logic;
+             SYNC_FLAG_1 : In    std_logic;
+             SYNC_FLAG_7 : In    std_logic;
+             WRITE_XX1_0 : In    std_logic;
+             R_ERROR : Out   std_logic;
+             R_FIFO_READn : Out   std_logic;
+             R_FIFO_RESETn : Out   std_logic;
+             R_FIFO_RETRANSMITn : Out   std_logic;
+             S_ERROR : Out   std_logic;
+             S_FIFO_RESETn : Out   std_logic;
+             S_FIFO_RETRANSMITn : Out   std_logic;
+             S_FIFO_WRITEn : Out   std_logic;
+             SR_ERROR : Out   std_logic );
+   end component;
+
+   component CONNECTING_FSM
+      Port ( PCI_CLOCK : In    std_logic;
+             PSC_ENABLE : In    std_logic;
+               RESET : In    std_logic;
+             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);
+             SPC_ENABLE : In    std_logic;
+             SYNC_R_FIFO_FFn : In    std_logic;
+             SYNC_S_FIFO_EFn : In    std_logic;
+             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);
+             R_FIFO_WRITEn : Out   std_logic;
+             S_FIFO_READn : Out   std_logic );
+   end component;
+
+   component FLAG_BUS
+      Port ( FLAG_IN_0 : In    std_logic;
+             FLAG_IN_4 : In    std_logic;
+                HOLD : In    std_logic;
+              KONS_1 : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+               R_EFn : In    std_logic;
+               R_FFn : In    std_logic;
+               R_HFn : In    std_logic;
+               S_EFn : In    std_logic;
+               S_FFn : In    std_logic;
+               S_HFn : In    std_logic;
+             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );
+   end component;
+
+begin
+
+   SYNC_FLAG <= SYNC_FLAG_DUMMY;
+
+   RESERVE <= gnd;
+   I23 : SER_PAR_CON
+      Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
+                 SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,
+                 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
+                 PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
+                 R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );
+   I22 : PAR_SER_CON
+      Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
+                 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
+                 RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,
+                 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
+                 S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );
+   I21 : FIFO_IO_CONTROL
+      Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
+                 SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),
+                 SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),
+                 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
+                 R_FIFO_READn=>R_FIFO_READn,
+                 R_FIFO_RESETn=>R_FIFO_RESETn,
+                 R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,
+                 S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,
+                 S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,
+                 S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );
+   I20 : CONNECTING_FSM
+      Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
+                 RESET=>RESET,
+                 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
+                 SPC_ENABLE=>SPC_ENABLE,
+                 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
+                 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
+                 R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),
+                 R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,
+                 S_FIFO_READn=>XXXS_FIFO_READn );
+   I19 : FLAG_BUS
+      Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,
+                 KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,
+                 R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,
+                 S_HFn=>S_HFn,
+                 SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );
+
+end SCHEMATIC;

diff --git a/dhwk/source/fifo_io_control.vhd b/dhwk/source/fifo_io_control.vhd
index 514f0780b494a38aa02b2aed55d49e54465f9001..167018f2143243c472f1a90fdc69d51c1578ea69 100644 (file)
--- a/dhwk/source/fifo_io_control.vhd
+++ b/dhwk/source/fifo_io_control.vhd
@@ -1,110 +1,110 @@
--- $Id: fifo_io_control.vhd,v 1.1 2007-03-10 11:24:03 sithglan Exp $\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity FIFO_IO_CONTROL is\r
-       port\r
-       (\r
-       PCI_CLOCK                               :in     std_logic;\r
-       WRITE_XX1_0                             :in     std_logic; -- PCI Write\r
-       FIFO_RDn                                :in     std_logic; -- FIFO Read (low active)\r
-       RESET                                   :in     std_logic;\r
-       SYNC_FLAG_1                             :in     std_logic; -- Recv FIFO Empty (low active)\r
-       SYNC_FLAG_7                             :in     std_logic; -- Send FIFO Full (low active)\r
-       S_FIFO_RESETn                           :out    std_logic; -- Send FIFO Reset (low active)\r
-       R_FIFO_RESETn                           :out    std_logic; -- Recv FIFO Reset (low active)\r
-       S_FIFO_WRITEn                           :out    std_logic; -- Send FIFO Write (low active)\r
-       R_FIFO_READn                            :out    std_logic; -- Recv FIFO Read (low active)\r
-       S_FIFO_RETRANSMITn                      :out    std_logic; -- Send FIFO Retransmit (low active)\r
-       R_FIFO_RETRANSMITn                      :out    std_logic; -- Recv FIFO Retransmit (low active)\r
-       S_ERROR                                 :out    std_logic; -- Send ERROR\r
-       R_ERROR                                 :out    std_logic; -- Recv ERROR\r
-       SR_ERROR                                :out    std_logic  -- Send / Recv Error\r
-       );      \r
-end entity FIFO_IO_CONTROL;\r
-\r
-architecture FIFO_IO_CONTROL_DESIGN of FIFO_IO_CONTROL is\r
-\r
-signal SIG_S_ERROR     :std_logic; -- Send Error\r
-signal SIG_R_ERROR     :std_logic; -- Recv Error\r
-\r
-begin\r
-\r
--- FIFO Write\r
-\r
-       process (PCI_CLOCK) \r
-       begin \r
-               if (PCI_CLOCK'event and PCI_CLOCK = '1')  then  \r
-                        if (RESET = '1') then\r
-                                S_FIFO_WRITEn <= '1';\r
-                                SIG_S_ERROR   <= '0';\r
-\r
-                        elsif (WRITE_XX1_0 = '0') then\r
-                                S_FIFO_WRITEn <= '1';\r
-\r
-                        elsif (WRITE_XX1_0 = '1') then\r
-                                if (SYNC_FLAG_7 = '0') then\r
-                                        SIG_S_ERROR <= '1';\r
-\r
-                                elsif (SYNC_FLAG_7 = '1') then\r
-                                        S_FIFO_WRITEn <= '0';\r
-                                        SIG_S_ERROR <= '0';\r
-                                end if;\r
-                                                                                               end if;\r
-               end if;\r
-       end process;    \r
-\r
-       S_ERROR <= SIG_S_ERROR;\r
-               \r
--- FIFO Read\r
-\r
-       R_FIFO_READn <= FIFO_RDn;       \r
-\r
--- Receive Error\r
-\r
-process (PCI_CLOCK) \r
-begin \r
-        if (PCI_CLOCK'event and PCI_CLOCK ='1')  then  \r
-                if (RESET = '1') then\r
-                        SIG_R_ERROR <= '0';\r
-\r
-                elsif (FIFO_RDn = '0' and SYNC_FLAG_1 = '0') then\r
-                        SIG_R_ERROR <= '1';\r
-                end if;\r
-        end if;\r
-end process; \r
-\r
-       R_ERROR <=      SIG_R_ERROR;            \r
-\r
--- Send or Receive Error\r
-\r
-process (PCI_CLOCK) \r
-begin \r
-        if (PCI_CLOCK'event and PCI_CLOCK ='1') then  \r
-                SR_ERROR       <= SIG_S_ERROR or SIG_R_ERROR;\r
-        end if;\r
-end process; \r
-\r
--- FIFO Reset\r
-\r
-process (PCI_CLOCK) \r
-begin \r
-        if (PCI_CLOCK'event and PCI_CLOCK ='1') then  \r
-                S_FIFO_RESETn <= not RESET;    \r
-                R_FIFO_RESETn <= not RESET;    \r
-        end if;\r
-end process;   \r
-\r
-\r
--- FIFO Retransmit\r
-\r
-process (PCI_CLOCK) \r
-begin \r
-        if (PCI_CLOCK'event and PCI_CLOCK ='1') then  \r
-                S_FIFO_RETRANSMITn <= '1';     \r
-                R_FIFO_RETRANSMITn <= '1';     \r
-        end if;\r
-end process; \r
-       \r
-end architecture FIFO_IO_CONTROL_DESIGN;\r
+-- $Id: fifo_io_control.vhd,v 1.2 2007-03-11 08:04:56 sithglan Exp $
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity FIFO_IO_CONTROL is
+       port
+       (
+       PCI_CLOCK                               :in     std_logic;
+       WRITE_XX1_0                             :in     std_logic; -- PCI Write
+       FIFO_RDn                                :in     std_logic; -- FIFO Read (low active)
+       RESET                                   :in     std_logic;
+       SYNC_FLAG_1                             :in     std_logic; -- Recv FIFO Empty (low active)
+       SYNC_FLAG_7                             :in     std_logic; -- Send FIFO Full (low active)
+       S_FIFO_RESETn                           :out    std_logic; -- Send FIFO Reset (low active)
+       R_FIFO_RESETn                           :out    std_logic; -- Recv FIFO Reset (low active)
+       S_FIFO_WRITEn                           :out    std_logic; -- Send FIFO Write (low active)
+       R_FIFO_READn                            :out    std_logic; -- Recv FIFO Read (low active)
+       S_FIFO_RETRANSMITn                      :out    std_logic; -- Send FIFO Retransmit (low active)
+       R_FIFO_RETRANSMITn                      :out    std_logic; -- Recv FIFO Retransmit (low active)
+       S_ERROR                                 :out    std_logic; -- Send ERROR
+       R_ERROR                                 :out    std_logic; -- Recv ERROR
+       SR_ERROR                                :out    std_logic  -- Send / Recv Error
+       );      
+end entity FIFO_IO_CONTROL;
+
+architecture FIFO_IO_CONTROL_DESIGN of FIFO_IO_CONTROL is
+
+signal SIG_S_ERROR     :std_logic; -- Send Error
+signal SIG_R_ERROR     :std_logic; -- Recv Error
+
+begin
+
+-- FIFO Write
+
+       process (PCI_CLOCK) 
+       begin 
+               if (PCI_CLOCK'event and PCI_CLOCK = '1')  then  
+                        if (RESET = '1') then
+                                S_FIFO_WRITEn <= '1';
+                                SIG_S_ERROR   <= '0';
+
+                        elsif (WRITE_XX1_0 = '0') then
+                                S_FIFO_WRITEn <= '1';
+
+                        elsif (WRITE_XX1_0 = '1') then
+                                if (SYNC_FLAG_7 = '0') then
+                                        SIG_S_ERROR <= '1';
+
+                                elsif (SYNC_FLAG_7 = '1') then
+                                        S_FIFO_WRITEn <= '0';
+                                        SIG_S_ERROR <= '0';
+                                end if;
+                                                                                               end if;
+               end if;
+       end process;    
+
+       S_ERROR <= SIG_S_ERROR;
+               
+-- FIFO Read
+
+       R_FIFO_READn <= FIFO_RDn;       
+
+-- Receive Error
+
+process (PCI_CLOCK) 
+begin 
+        if (PCI_CLOCK'event and PCI_CLOCK ='1')  then  
+                if (RESET = '1') then
+                        SIG_R_ERROR <= '0';
+
+                elsif (FIFO_RDn = '0' and SYNC_FLAG_1 = '0') then
+                        SIG_R_ERROR <= '1';
+                end if;
+        end if;
+end process; 
+
+       R_ERROR <=      SIG_R_ERROR;            
+
+-- Send or Receive Error
+
+process (PCI_CLOCK) 
+begin 
+        if (PCI_CLOCK'event and PCI_CLOCK ='1') then  
+                SR_ERROR       <= SIG_S_ERROR or SIG_R_ERROR;
+        end if;
+end process; 
+
+-- FIFO Reset
+
+process (PCI_CLOCK) 
+begin 
+        if (PCI_CLOCK'event and PCI_CLOCK ='1') then  
+                S_FIFO_RESETn <= not RESET;    
+                R_FIFO_RESETn <= not RESET;    
+        end if;
+end process;   
+
+
+-- FIFO Retransmit
+
+process (PCI_CLOCK) 
+begin 
+        if (PCI_CLOCK'event and PCI_CLOCK ='1') then  
+                S_FIFO_RETRANSMITn <= '1';     
+                R_FIFO_RETRANSMITn <= '1';     
+        end if;
+end process; 
+       
+end architecture FIFO_IO_CONTROL_DESIGN;

diff --git a/dhwk/source/io_mux_reg.vhd b/dhwk/source/io_mux_reg.vhd
index 564d8bb6337261c42158713b19f5a112ff6d2cc2..a7267f1c2443bdc626366ea517999f6498a6ec9a 100644 (file)
--- a/dhwk/source/io_mux_reg.vhd
+++ b/dhwk/source/io_mux_reg.vhd
@@ -1,104 +1,104 @@
--- VHDL model created from schematic io_mux_reg.sch -- Jan 09 09:34:13 2007\r
-\r
-\r
-\r
-LIBRARY ieee;\r
-\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-\r
-entity IO_MUX_REG is\r
-      Port ( CONFIG_DATA : In    std_logic_vector (31 downto 0);\r
-             LOAD_ADDR_REG : In    std_logic;\r
-             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_FRAMEn : In    std_logic;\r
-             PCI_IDSEL : In    std_logic;\r
-             PCI_IRDYn : In    std_logic;\r
-             PCI_PAR : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             READ_SEL : In    std_logic_vector (1 downto 0);\r
-             USER_DATA : In    std_logic_vector (31 downto 0);\r
-              PCI_AD : InOut std_logic_vector (31 downto 0);\r
-              AD_REG : Out   std_logic_vector (31 downto 0);\r
-             ADDR_REG : Out   std_logic_vector (31 downto 0);\r
-             CBE_REGn : Out   std_logic_vector (3 downto 0);\r
-             FRAME_REGn : Out   std_logic;\r
-             IDSEL_REG : Out   std_logic;\r
-             IRDY_REGn : Out   std_logic;\r
-             PAR_REG : Out   std_logic );\r
-end IO_MUX_REG;\r
-\r
-architecture SCHEMATIC of IO_MUX_REG is\r
-\r
-   SIGNAL gnd : std_logic := '0';\r
-   SIGNAL vcc : std_logic := '1';\r
-\r
-   signal  IO_DATA : std_logic_vector (31 downto 0);\r
-   signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
-\r
-   component ADDRESS_REGISTER\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             LOAD_ADDR_REG : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             ADDR_REG : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-   component IO_REG\r
-      Port ( IO_DATA : In    std_logic_vector (31 downto 0);\r
-             OE_PCI_AD : In    std_logic;\r
-             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_FRAMEn : In    std_logic;\r
-             PCI_IDSEL : In    std_logic;\r
-             PCI_IRDYn : In    std_logic;\r
-             PCI_PAR : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-              AD_REG : Out   std_logic_vector (31 downto 0);\r
-             CBE_REGn : Out   std_logic_vector (3 downto 0);\r
-             FRAME_REGn : Out   std_logic;\r
-             IDSEL_REG : Out   std_logic;\r
-             IRDY_REGn : Out   std_logic;\r
-             PAR_REG : Out   std_logic;\r
-              PCI_AD : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-   component IO_MUX\r
-      Port ( CONFIG_DATA : In    std_logic_vector (31 downto 0);\r
-              PCI_AD : In    std_logic_vector (31 downto 0);\r
-             READ_SEL : In    std_logic_vector (1 downto 0);\r
-             USER_DATA : In    std_logic_vector (31 downto 0);\r
-             IO_DATA : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-begin\r
-\r
-   AD_REG <= AD_REG_DUMMY;\r
-\r
-   I5 : ADDRESS_REGISTER\r
-      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
-                 LOAD_ADDR_REG=>LOAD_ADDR_REG, PCI_CLOCK=>PCI_CLOCK,\r
-                 PCI_RSTn=>PCI_RSTn,\r
-                 ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0) );\r
-   I1 : IO_REG\r
-      Port Map ( IO_DATA(31 downto 0)=>IO_DATA(31 downto 0),\r
-                 OE_PCI_AD=>READ_SEL(1),\r
-                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
-                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
-                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
-                 PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,\r
-                 AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
-                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
-                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
-                 IRDY_REGn=>IRDY_REGn, PAR_REG=>PAR_REG,\r
-                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0) );\r
-   I2 : IO_MUX\r
-      Port Map ( CONFIG_DATA(31 downto 0)=>CONFIG_DATA(31 downto 0),\r
-                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
-                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
-                 USER_DATA(31 downto 0)=>USER_DATA(31 downto 0),\r
-                 IO_DATA(31 downto 0)=>IO_DATA(31 downto 0) );\r
-\r
-end SCHEMATIC;\r
+-- VHDL model created from schematic io_mux_reg.sch -- Jan 09 09:34:13 2007
+
+
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity IO_MUX_REG is
+      Port ( CONFIG_DATA : In    std_logic_vector (31 downto 0);
+             LOAD_ADDR_REG : In    std_logic;
+             PCI_CBEn : In    std_logic_vector (3 downto 0);
+             PCI_CLOCK : In    std_logic;
+             PCI_FRAMEn : In    std_logic;
+             PCI_IDSEL : In    std_logic;
+             PCI_IRDYn : In    std_logic;
+             PCI_PAR : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             READ_SEL : In    std_logic_vector (1 downto 0);
+             USER_DATA : In    std_logic_vector (31 downto 0);
+              PCI_AD : InOut std_logic_vector (31 downto 0);
+              AD_REG : Out   std_logic_vector (31 downto 0);
+             ADDR_REG : Out   std_logic_vector (31 downto 0);
+             CBE_REGn : Out   std_logic_vector (3 downto 0);
+             FRAME_REGn : Out   std_logic;
+             IDSEL_REG : Out   std_logic;
+             IRDY_REGn : Out   std_logic;
+             PAR_REG : Out   std_logic );
+end IO_MUX_REG;
+
+architecture SCHEMATIC of IO_MUX_REG is
+
+   SIGNAL gnd : std_logic := '0';
+   SIGNAL vcc : std_logic := '1';
+
+   signal  IO_DATA : std_logic_vector (31 downto 0);
+   signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
+
+   component ADDRESS_REGISTER
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             LOAD_ADDR_REG : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             ADDR_REG : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+   component IO_REG
+      Port ( IO_DATA : In    std_logic_vector (31 downto 0);
+             OE_PCI_AD : In    std_logic;
+             PCI_CBEn : In    std_logic_vector (3 downto 0);
+             PCI_CLOCK : In    std_logic;
+             PCI_FRAMEn : In    std_logic;
+             PCI_IDSEL : In    std_logic;
+             PCI_IRDYn : In    std_logic;
+             PCI_PAR : In    std_logic;
+             PCI_RSTn : In    std_logic;
+              AD_REG : Out   std_logic_vector (31 downto 0);
+             CBE_REGn : Out   std_logic_vector (3 downto 0);
+             FRAME_REGn : Out   std_logic;
+             IDSEL_REG : Out   std_logic;
+             IRDY_REGn : Out   std_logic;
+             PAR_REG : Out   std_logic;
+              PCI_AD : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+   component IO_MUX
+      Port ( CONFIG_DATA : In    std_logic_vector (31 downto 0);
+              PCI_AD : In    std_logic_vector (31 downto 0);
+             READ_SEL : In    std_logic_vector (1 downto 0);
+             USER_DATA : In    std_logic_vector (31 downto 0);
+             IO_DATA : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+begin
+
+   AD_REG <= AD_REG_DUMMY;
+
+   I5 : ADDRESS_REGISTER
+      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+                 LOAD_ADDR_REG=>LOAD_ADDR_REG, PCI_CLOCK=>PCI_CLOCK,
+                 PCI_RSTn=>PCI_RSTn,
+                 ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0) );
+   I1 : IO_REG
+      Port Map ( IO_DATA(31 downto 0)=>IO_DATA(31 downto 0),
+                 OE_PCI_AD=>READ_SEL(1),
+                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
+                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
+                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
+                 PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
+                 AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
+                 IRDY_REGn=>IRDY_REGn, PAR_REG=>PAR_REG,
+                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0) );
+   I2 : IO_MUX
+      Port Map ( CONFIG_DATA(31 downto 0)=>CONFIG_DATA(31 downto 0),
+                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
+                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
+                 USER_DATA(31 downto 0)=>USER_DATA(31 downto 0),
+                 IO_DATA(31 downto 0)=>IO_DATA(31 downto 0) );
+
+end SCHEMATIC;

diff --git a/dhwk/source/parity.vhd b/dhwk/source/parity.vhd
index b0dce43921bd82222b748c14735dfc4090f127f6..c703a9d11ce0dcf25bd8e468833810beac64cdd8 100644 (file)
--- a/dhwk/source/parity.vhd
+++ b/dhwk/source/parity.vhd
@@ -1,106 +1,106 @@
--- VHDL model created from schematic parity.sch -- Jan 09 09:34:12 2007\r
-\r
---LIBRARY vanmacro;\r
---USE vanmacro.components.ALL;\r
-LIBRARY ieee;\r
---LIBRARY generics;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
---USE generics.components.ALL;\r
-\r
-entity PARITY is\r
-      Port ( OE_PCI_PAR : In    std_logic;\r
-             OE_PCI_PERR : In    std_logic;\r
-             PA_ER_RE : In    std_logic;\r
-              PAR_IN : In    std_logic_vector (35 downto 0);\r
-             PAR_REG : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             PERR_CHECK : In    std_logic;\r
-             SERR_CHECK : In    std_logic;\r
-             SERR_ENA : In    std_logic;\r
-             PCI_PAR : InOut std_logic;\r
-             PCI_PERRn : Out   std_logic;\r
-             PCI_SERRn : Out   std_logic;\r
-                PERR : Out   std_logic;\r
-                SERR : Out   std_logic );\r
-end PARITY;\r
-\r
-architecture SCHEMATIC of PARITY is\r
-\r
-   SIGNAL gnd : std_logic := '0';\r
-   SIGNAL vcc : std_logic := '1';\r
-\r
-   signal  PAR_OUT : std_logic_vector (10 downto 0);\r
-\r
-   component PARITY_OUT\r
-      Port ( OE_PCI_PAR : In    std_logic;\r
-             OE_PCI_PERR : In    std_logic;\r
-             PA_ER_RE : In    std_logic;\r
-              PAR_IN : In    std_logic_vector (2 downto 0);\r
-             PAR_REG : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_PAR_IN : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             PERR_CHECK : In    std_logic;\r
-             SERR_CHECK : In    std_logic;\r
-             SERR_ENA : In    std_logic;\r
-             PCI_PAR : Out   std_logic;\r
-             PCI_PERRn : Out   std_logic;\r
-             PCI_SERRn : Out   std_logic;\r
-                PERR : Out   std_logic;\r
-                SERR : Out   std_logic );\r
-   end component;\r
-\r
-   component PARITY_4\r
-      Port (  PAR_IN : In    std_logic_vector (3 downto 0);\r
-             PAR_OUT : Out   std_logic );\r
-   end component;\r
-\r
-begin\r
-\r
-   I12 : PARITY_OUT\r
-      Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,\r
-                 PA_ER_RE=>PA_ER_RE,\r
-                 PAR_IN(2 downto 0)=>PAR_OUT(10 downto 8),\r
-                 PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,\r
-                 PCI_PAR_IN=>PCI_PAR, PCI_RSTn=>PCI_RSTn,\r
-                 PERR_CHECK=>PERR_CHECK, SERR_CHECK=>SERR_CHECK,\r
-                 SERR_ENA=>SERR_ENA, PCI_PAR=>PCI_PAR,\r
-                 PCI_PERRn=>PCI_PERRn, PCI_SERRn=>PCI_SERRn, PERR=>PERR,\r
-                 SERR=>SERR );\r
-   I9 : PARITY_4\r
-      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(35 downto 32),\r
-                 PAR_OUT=>PAR_OUT(8) );\r
-   I11 : PARITY_4\r
-      Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(7 downto 4),\r
-                 PAR_OUT=>PAR_OUT(10) );\r
-   I8 : PARITY_4\r
-      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(31 downto 28),\r
-                 PAR_OUT=>PAR_OUT(7) );\r
-   I7 : PARITY_4\r
-      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(27 downto 24),\r
-                 PAR_OUT=>PAR_OUT(6) );\r
-   I6 : PARITY_4\r
-      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(23 downto 20),\r
-                 PAR_OUT=>PAR_OUT(5) );\r
-   I5 : PARITY_4\r
-      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(19 downto 16),\r
-                 PAR_OUT=>PAR_OUT(4) );\r
-   I4 : PARITY_4\r
-      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(15 downto 12),\r
-                 PAR_OUT=>PAR_OUT(3) );\r
-   I3 : PARITY_4\r
-      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(11 downto 8),\r
-                 PAR_OUT=>PAR_OUT(2) );\r
-   I2 : PARITY_4\r
-      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(7 downto 4),\r
-                 PAR_OUT=>PAR_OUT(1) );\r
-   I1 : PARITY_4\r
-      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(3 downto 0),\r
-                 PAR_OUT=>PAR_OUT(0) );\r
-   I10 : PARITY_4\r
-      Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(3 downto 0),\r
-                 PAR_OUT=>PAR_OUT(9) );\r
-\r
-end SCHEMATIC;\r
+-- VHDL model created from schematic parity.sch -- Jan 09 09:34:12 2007
+
+--LIBRARY vanmacro;
+--USE vanmacro.components.ALL;
+LIBRARY ieee;
+--LIBRARY generics;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+--USE generics.components.ALL;
+
+entity PARITY is
+      Port ( OE_PCI_PAR : In    std_logic;
+             OE_PCI_PERR : In    std_logic;
+             PA_ER_RE : In    std_logic;
+              PAR_IN : In    std_logic_vector (35 downto 0);
+             PAR_REG : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             PERR_CHECK : In    std_logic;
+             SERR_CHECK : In    std_logic;
+             SERR_ENA : In    std_logic;
+             PCI_PAR : InOut std_logic;
+             PCI_PERRn : Out   std_logic;
+             PCI_SERRn : Out   std_logic;
+                PERR : Out   std_logic;
+                SERR : Out   std_logic );
+end PARITY;
+
+architecture SCHEMATIC of PARITY is
+
+   SIGNAL gnd : std_logic := '0';
+   SIGNAL vcc : std_logic := '1';
+
+   signal  PAR_OUT : std_logic_vector (10 downto 0);
+
+   component PARITY_OUT
+      Port ( OE_PCI_PAR : In    std_logic;
+             OE_PCI_PERR : In    std_logic;
+             PA_ER_RE : In    std_logic;
+              PAR_IN : In    std_logic_vector (2 downto 0);
+             PAR_REG : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_PAR_IN : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             PERR_CHECK : In    std_logic;
+             SERR_CHECK : In    std_logic;
+             SERR_ENA : In    std_logic;
+             PCI_PAR : Out   std_logic;
+             PCI_PERRn : Out   std_logic;
+             PCI_SERRn : Out   std_logic;
+                PERR : Out   std_logic;
+                SERR : Out   std_logic );
+   end component;
+
+   component PARITY_4
+      Port (  PAR_IN : In    std_logic_vector (3 downto 0);
+             PAR_OUT : Out   std_logic );
+   end component;
+
+begin
+
+   I12 : PARITY_OUT
+      Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,
+                 PA_ER_RE=>PA_ER_RE,
+                 PAR_IN(2 downto 0)=>PAR_OUT(10 downto 8),
+                 PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,
+                 PCI_PAR_IN=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
+                 PERR_CHECK=>PERR_CHECK, SERR_CHECK=>SERR_CHECK,
+                 SERR_ENA=>SERR_ENA, PCI_PAR=>PCI_PAR,
+                 PCI_PERRn=>PCI_PERRn, PCI_SERRn=>PCI_SERRn, PERR=>PERR,
+                 SERR=>SERR );
+   I9 : PARITY_4
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(35 downto 32),
+                 PAR_OUT=>PAR_OUT(8) );
+   I11 : PARITY_4
+      Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(7 downto 4),
+                 PAR_OUT=>PAR_OUT(10) );
+   I8 : PARITY_4
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(31 downto 28),
+                 PAR_OUT=>PAR_OUT(7) );
+   I7 : PARITY_4
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(27 downto 24),
+                 PAR_OUT=>PAR_OUT(6) );
+   I6 : PARITY_4
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(23 downto 20),
+                 PAR_OUT=>PAR_OUT(5) );
+   I5 : PARITY_4
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(19 downto 16),
+                 PAR_OUT=>PAR_OUT(4) );
+   I4 : PARITY_4
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(15 downto 12),
+                 PAR_OUT=>PAR_OUT(3) );
+   I3 : PARITY_4
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(11 downto 8),
+                 PAR_OUT=>PAR_OUT(2) );
+   I2 : PARITY_4
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(7 downto 4),
+                 PAR_OUT=>PAR_OUT(1) );
+   I1 : PARITY_4
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(3 downto 0),
+                 PAR_OUT=>PAR_OUT(0) );
+   I10 : PARITY_4
+      Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(3 downto 0),
+                 PAR_OUT=>PAR_OUT(9) );
+
+end SCHEMATIC;

diff --git a/dhwk/source/parity_out.vhd b/dhwk/source/parity_out.vhd
index 285764d21ce3d039f62e4dac7b13abeab8df0668..55ba210252726e03deff1b660b5133207ad88400 100644 (file)
--- a/dhwk/source/parity_out.vhd
+++ b/dhwk/source/parity_out.vhd
@@ -1,66 +1,66 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: PARITY_OUT.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-\r
-entity PARITY_OUT is\r
-       port(\r
-               PCI_CLOCK               :in             std_logic;\r
-               PCI_RSTn                :in             std_logic;\r
-               PAR_IN                  :in             std_logic_vector ( 2 downto 0); \r
-               PAR_REG                 :in             std_logic;\r
-               SERR_CHECK      :in             std_logic;      \r
-               PERR_CHECK      :in             std_logic;\r
-               OE_PCI_PAR      :in             std_logic;\r
-               OE_PCI_PERR     :in             std_logic;\r
-               PA_ER_RE                :in             std_logic;\r
-               SERR_ENA                :in             std_logic;\r
-               PCI_PAR_IN      :in             std_logic;\r
-               PERR                            :out    std_logic;\r
-               SERR                            :out    std_logic;\r
-               PCI_PERRn               :out    std_logic;      --      s/t/s\r
-               PCI_SERRn               :out    std_logic;      --      o/d\r
-               PCI_PAR                 :out    std_logic               --      t/s\r
-               );\r
-end entity PARITY_OUT; \r
-\r
-architecture PARITY_OUT_DESIGN of PARITY_OUT is\r
-\r
-       signal PAR                      :std_logic;\r
-       signal PAR_FF           :std_logic;\r
-       signal SERR_FF  :std_logic;\r
-       signal PERR_FF  :std_logic;\r
-  \r
-begin\r
-\r
-       PAR             <= ( PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) ); \r
-\r
-       process (PCI_CLOCK, PCI_RSTn) \r
-       begin\r
-               if      PCI_RSTn = '0'  then    PAR_FF  <= '0';\r
-                                                                                                                       PERR_FF <= '0';\r
-                                                                                                                       SERR_FF <= '0'; \r
-\r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-\r
-                       PAR_FF  <=      PAR;\r
-                       SERR_FF <=      ((PCI_PAR_IN xor PAR) and SERR_CHECK) and PA_ER_RE and SERR_ENA and (not SERR_FF);   \r
-                       PERR_FF <=      ((PCI_PAR_IN xor PAR) and PERR_CHECK) and (not PERR_FF);  \r
-\r
-               end if;\r
-       end process; \r
-\r
-       SERR                    <=  SERR_FF;\r
-       PERR                    <=  PERR_FF;\r
-\r
-       PCI_PAR         <= PAR_FF                               when    OE_PCI_PAR      = '1' else 'Z' ; \r
-       PCI_SERRn       <= '0'                                  when    SERR_FF                 = '1' else 'Z' ;\r
-       PCI_PERRn       <= not PERR_FF  when    OE_PCI_PERR     = '1' and PA_ER_RE = '1' else 'Z' ;\r
-\r
-end architecture PARITY_OUT_DESIGN;\r
-\r
-\r
-\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: PARITY_OUT.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity PARITY_OUT is
+       port(
+               PCI_CLOCK               :in             std_logic;
+               PCI_RSTn                :in             std_logic;
+               PAR_IN                  :in             std_logic_vector ( 2 downto 0); 
+               PAR_REG                 :in             std_logic;
+               SERR_CHECK      :in             std_logic;      
+               PERR_CHECK      :in             std_logic;
+               OE_PCI_PAR      :in             std_logic;
+               OE_PCI_PERR     :in             std_logic;
+               PA_ER_RE                :in             std_logic;
+               SERR_ENA                :in             std_logic;
+               PCI_PAR_IN      :in             std_logic;
+               PERR                            :out    std_logic;
+               SERR                            :out    std_logic;
+               PCI_PERRn               :out    std_logic;      --      s/t/s
+               PCI_SERRn               :out    std_logic;      --      o/d
+               PCI_PAR                 :out    std_logic               --      t/s
+               );
+end entity PARITY_OUT; 
+
+architecture PARITY_OUT_DESIGN of PARITY_OUT is
+
+       signal PAR                      :std_logic;
+       signal PAR_FF           :std_logic;
+       signal SERR_FF  :std_logic;
+       signal PERR_FF  :std_logic;
+  
+begin
+
+       PAR             <= ( PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) ); 
+
+       process (PCI_CLOCK, PCI_RSTn) 
+       begin
+               if      PCI_RSTn = '0'  then    PAR_FF  <= '0';
+                                                                                                                       PERR_FF <= '0';
+                                                                                                                       SERR_FF <= '0'; 
+
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+
+                       PAR_FF  <=      PAR;
+                       SERR_FF <=      ((PCI_PAR_IN xor PAR) and SERR_CHECK) and PA_ER_RE and SERR_ENA and (not SERR_FF);   
+                       PERR_FF <=      ((PCI_PAR_IN xor PAR) and PERR_CHECK) and (not PERR_FF);  
+
+               end if;
+       end process; 
+
+       SERR                    <=  SERR_FF;
+       PERR                    <=  PERR_FF;
+
+       PCI_PAR         <= PAR_FF                               when    OE_PCI_PAR      = '1' else 'Z' ; 
+       PCI_SERRn       <= '0'                                  when    SERR_FF                 = '1' else 'Z' ;
+       PCI_PERRn       <= not PERR_FF  when    OE_PCI_PERR     = '1' and PA_ER_RE = '1' else 'Z' ;
+
+end architecture PARITY_OUT_DESIGN;
+
+
+

diff --git a/dhwk/source/pci/address_register.vhd b/dhwk/source/pci/address_register.vhd
index 11602a91f14f1b33e83aa80756f669457af34ce6..99360c5f65d419438adaa9dd7297a781f60ae2a7 100644 (file)
--- a/dhwk/source/pci/address_register.vhd
+++ b/dhwk/source/pci/address_register.vhd
@@ -1,39 +1,39 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: ADDR_REG.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity ADDRESS_REGISTER is\r
-       port (\r
-                PCI_CLOCK      :in     std_logic;\r
-                PCI_RSTn       :in     std_logic;\r
-                LOAD_ADDR_REG  :in     std_logic;\r
-                AD_REG         :in     std_logic_vector (31 downto 0);\r
-                ADDR_REG       :out    std_logic_vector (31 downto 0)\r
-        );\r
-end entity ADDRESS_REGISTER;\r
-\r
-architecture ADDR_REGI_DESIGN of ADDRESS_REGISTER is\r
-       signal  REG_ADDR        :std_logic_vector (31 downto 0); \r
-begin \r
-\r
-       process (PCI_CLOCK, PCI_RSTn) \r
-       begin\r
-               if      PCI_RSTn = '0'  then\r
-                        REG_ADDR       <= X"00000000";\r
-\r
-               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
-                       if LOAD_ADDR_REG = '1' then\r
-                                REG_ADDR       <=      AD_REG;\r
-                       else\r
-                                REG_ADDR       <=      REG_ADDR;\r
-                       end if;\r
-               end if;\r
-       end process;\r
-\r
-       ADDR_REG        <=      REG_ADDR;\r
-\r
-end architecture ADDR_REGI_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: ADDR_REG.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity ADDRESS_REGISTER is
+       port (
+                PCI_CLOCK      :in     std_logic;
+                PCI_RSTn       :in     std_logic;
+                LOAD_ADDR_REG  :in     std_logic;
+                AD_REG         :in     std_logic_vector (31 downto 0);
+                ADDR_REG       :out    std_logic_vector (31 downto 0)
+        );
+end entity ADDRESS_REGISTER;
+
+architecture ADDR_REGI_DESIGN of ADDRESS_REGISTER is
+       signal  REG_ADDR        :std_logic_vector (31 downto 0); 
+begin 
+
+       process (PCI_CLOCK, PCI_RSTn) 
+       begin
+               if      PCI_RSTn = '0'  then
+                        REG_ADDR       <= X"00000000";
+
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                       if LOAD_ADDR_REG = '1' then
+                                REG_ADDR       <=      AD_REG;
+                       else
+                                REG_ADDR       <=      REG_ADDR;
+                       end if;
+               end if;
+       end process;
+
+       ADDR_REG        <=      REG_ADDR;
+
+end architecture ADDR_REGI_DESIGN;

diff --git a/dhwk/source/pci_interface.vhd b/dhwk/source/pci_interface.vhd
index 25807505ad601c05644106fdc770d43ebeb12fa9..cbca14d8c7fce975069c13c5303443b251043355 100644 (file)
--- a/dhwk/source/pci_interface.vhd
+++ b/dhwk/source/pci_interface.vhd
@@ -1,227 +1,227 @@
--- VHDL model created from schematic pci_interface.sch -- Jan 09 09:34:13 2007\r
-\r
-\r
-\r
-LIBRARY ieee;\r
-\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-\r
-entity PCI_INTERFACE is\r
-      Port ( PCI_CBEn : In    std_logic_vector (3 downto 0);\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_FRAMEn : In    std_logic;\r
-             PCI_IDSEL : In    std_logic;\r
-             PCI_IRDYn : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             READ_FIFO : In    std_logic;\r
-             REVISON_ID : In    std_logic_vector (7 downto 0);\r
-             USER_DATA_OUT : In    std_logic_vector (31 downto 0);\r
-             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
-              PCI_AD : InOut std_logic_vector (31 downto 0);\r
-             PCI_PAR : InOut std_logic;\r
-              AD_REG : Out   std_logic_vector (31 downto 0);\r
-             ADDR_REG : Out   std_logic_vector (31 downto 0);\r
-             CBE_REGn : Out   std_logic_vector (3 downto 0);\r
-             DEVSELn : Out   std_logic;\r
-             FIFO_RDn : Out   std_logic;\r
-             IO_WR_COM : Out   std_logic;\r
-             IRDY_REGn : Out   std_logic;\r
-             PCI_DEVSELn : Out   std_logic;\r
-             PCI_PERRn : Out   std_logic;\r
-             PCI_SERRn : Out   std_logic;\r
-             PCI_STOPn : Out   std_logic;\r
-             PCI_TRDYn : Out   std_logic;\r
-             READ_SEL : Out   std_logic_vector (1 downto 0);\r
-               TRDYn : Out   std_logic );\r
-end PCI_INTERFACE;\r
-\r
-architecture SCHEMATIC of PCI_INTERFACE is\r
-\r
-   SIGNAL gnd : std_logic := '0';\r
-   SIGNAL vcc : std_logic := '1';\r
-\r
-   signal IRDY_REGn_DUMMY : std_logic;\r
-   signal  PAR_REG : std_logic;\r
-   signal     PERR : std_logic;\r
-   signal     SERR : std_logic;\r
-   signal CF_RD_COM : std_logic;\r
-   signal CF_WR_COM : std_logic;\r
-   signal      LAR : std_logic;\r
-   signal  MY_ADDR : std_logic;\r
-   signal SERR_CHECK : std_logic;\r
-   signal IDSEL_REG : std_logic;\r
-   signal FRAME_REGn : std_logic;\r
-   signal PERR_CHECK : std_logic;\r
-   signal OE_PCI_PAR : std_logic;\r
-   signal OE_PCI_PERR : std_logic;\r
-   signal TRDYn_DUMMY : std_logic;\r
-   signal CONF_DATA_10H : std_logic_vector (31 downto 0);\r
-   signal CONF_DATA_04H : std_logic_vector (31 downto 0);\r
-   signal CONF_DATA : std_logic_vector (31 downto 0);\r
-   signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);\r
-   signal CBE_REGn_DUMMY : std_logic_vector (3 downto 0);\r
-   signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
-   signal ADDR_REG_DUMMY : std_logic_vector (31 downto 0);\r
-\r
-   component STEUERUNG\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-             FRAME_REGn : In    std_logic;\r
-             IDSEL_REG : In    std_logic;\r
-             IO_SPACE : In    std_logic;\r
-             MY_ADDR : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             READ_FIFO : In    std_logic;\r
-             CF_RD_COM : Out   std_logic;\r
-             CF_WR_COM : Out   std_logic;\r
-             DEVSELn : Out   std_logic;\r
-             FIFO_RDn : Out   std_logic;\r
-             IO_RD_COM : Out   std_logic;\r
-             IO_WR_COM : Out   std_logic;\r
-                 LAR : Out   std_logic;\r
-             OE_PCI_PAR : Out   std_logic;\r
-             OE_PCI_PERR : Out   std_logic;\r
-             PCI_DEVSELn : Out   std_logic;\r
-             PCI_STOPn : Out   std_logic;\r
-             PCI_TRDYn : Out   std_logic;\r
-             PERR_CHECK : Out   std_logic;\r
-                READ : Out   std_logic;\r
-             SERR_CHECK : Out   std_logic;\r
-               TRDYn : Out   std_logic );\r
-   end component;\r
-\r
-   component PARITY\r
-      Port ( OE_PCI_PAR : In    std_logic;\r
-             OE_PCI_PERR : In    std_logic;\r
-             PA_ER_RE : In    std_logic;\r
-              PAR_IN : In    std_logic_vector (35 downto 0);\r
-             PAR_REG : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             PERR_CHECK : In    std_logic;\r
-             SERR_CHECK : In    std_logic;\r
-             SERR_ENA : In    std_logic;\r
-             PCI_PAR : InOut std_logic;\r
-             PCI_PERRn : Out   std_logic;\r
-             PCI_SERRn : Out   std_logic;\r
-                PERR : Out   std_logic;\r
-                SERR : Out   std_logic );\r
-   end component;\r
-\r
-   component VERGLEICH\r
-      Port (    IN_A : In    std_logic_vector (31 downto 0);\r
-                IN_B : In    std_logic_vector (31 downto 0);\r
-             GLEICH_OUT : Out   std_logic );\r
-   end component;\r
-\r
-   component IO_MUX_REG\r
-      Port ( CONFIG_DATA : In    std_logic_vector (31 downto 0);\r
-             LOAD_ADDR_REG : In    std_logic;\r
-             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_FRAMEn : In    std_logic;\r
-             PCI_IDSEL : In    std_logic;\r
-             PCI_IRDYn : In    std_logic;\r
-             PCI_PAR : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             READ_SEL : In    std_logic_vector (1 downto 0);\r
-             USER_DATA : In    std_logic_vector (31 downto 0);\r
-              PCI_AD : InOut std_logic_vector (31 downto 0);\r
-              AD_REG : Out   std_logic_vector (31 downto 0);\r
-             ADDR_REG : Out   std_logic_vector (31 downto 0);\r
-             CBE_REGn : Out   std_logic_vector (3 downto 0);\r
-             FRAME_REGn : Out   std_logic;\r
-             IDSEL_REG : Out   std_logic;\r
-             IRDY_REGn : Out   std_logic;\r
-             PAR_REG : Out   std_logic );\r
-   end component;\r
-\r
-   component CONFIG_SPACE_HEADER\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             ADDR_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-             CF_RD_COM : In    std_logic;\r
-             CF_WR_COM : In    std_logic;\r
-             IRDY_REGn : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-                PERR : In    std_logic;\r
-             REVISION_ID : In    std_logic_vector (7 downto 0);\r
-                SERR : In    std_logic;\r
-               TRDYn : In    std_logic;\r
-             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
-             CONF_DATA : Out   std_logic_vector (31 downto 0);\r
-             CONF_DATA_04H : Out   std_logic_vector (31 downto 0);\r
-             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );\r
-   end component;\r
-\r
-begin\r
-\r
-   ADDR_REG <= ADDR_REG_DUMMY;\r
-   AD_REG <= AD_REG_DUMMY;\r
-   CBE_REGn <= CBE_REGn_DUMMY;\r
-   READ_SEL <= READ_SEL_DUMMY;\r
-   TRDYn <= TRDYn_DUMMY;\r
-   IRDY_REGn <= IRDY_REGn_DUMMY;\r
-\r
-   I7 : STEUERUNG\r
-      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
-                 CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),\r
-                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
-                 IO_SPACE=>CONF_DATA_04H(0), MY_ADDR=>MY_ADDR,\r
-                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
-                 READ_FIFO=>READ_FIFO, CF_RD_COM=>CF_RD_COM,\r
-                 CF_WR_COM=>CF_WR_COM, DEVSELn=>DEVSELn,\r
-                 FIFO_RDn=>FIFO_RDn, IO_RD_COM=>READ_SEL_DUMMY(0),\r
-                 IO_WR_COM=>IO_WR_COM, LAR=>LAR, OE_PCI_PAR=>OE_PCI_PAR,\r
-                 OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,\r
-                 PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,\r
-                 PERR_CHECK=>PERR_CHECK, READ=>READ_SEL_DUMMY(1),\r
-                 SERR_CHECK=>SERR_CHECK, TRDYn=>TRDYn_DUMMY );\r
-   I5 : PARITY\r
-      Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,\r
-                 PA_ER_RE=>CONF_DATA_04H(6),\r
-                 PAR_IN(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
-                 PAR_IN(35 downto 32)=>CBE_REGn_DUMMY(3 downto 0),\r
-                 PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,\r
-                 PCI_RSTn=>PCI_RSTn, PERR_CHECK=>PERR_CHECK,\r
-                 SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8),\r
-                 PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn,\r
-                 PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR );\r
-   I4 : VERGLEICH\r
-      Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0),\r
-                 IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
-                 GLEICH_OUT=>MY_ADDR );\r
-   I2 : IO_MUX_REG\r
-      Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0),\r
-                 LOAD_ADDR_REG=>LAR,\r
-                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
-                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
-                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
-                 PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,\r
-                 READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),\r
-                 USER_DATA(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
-                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
-                 AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
-                 ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),\r
-                 CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),\r
-                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
-                 IRDY_REGn=>IRDY_REGn_DUMMY, PAR_REG=>PAR_REG );\r
-   I1 : CONFIG_SPACE_HEADER\r
-      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
-                 ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),\r
-                 CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),\r
-                 CF_RD_COM=>CF_RD_COM, CF_WR_COM=>CF_WR_COM,\r
-                 IRDY_REGn=>IRDY_REGn_DUMMY, PCI_CLOCK=>PCI_CLOCK,\r
-                 PCI_RSTn=>PCI_RSTn, PERR=>PERR,\r
-                 REVISION_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
-                 SERR=>SERR, TRDYn=>TRDYn_DUMMY,\r
-                 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
-                 CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0),\r
-                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0),\r
-                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) );\r
-\r
-end SCHEMATIC;\r
+-- VHDL model created from schematic pci_interface.sch -- Jan 09 09:34:13 2007
+
+
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity PCI_INTERFACE is
+      Port ( PCI_CBEn : In    std_logic_vector (3 downto 0);
+             PCI_CLOCK : In    std_logic;
+             PCI_FRAMEn : In    std_logic;
+             PCI_IDSEL : In    std_logic;
+             PCI_IRDYn : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             READ_FIFO : In    std_logic;
+             REVISON_ID : In    std_logic_vector (7 downto 0);
+             USER_DATA_OUT : In    std_logic_vector (31 downto 0);
+             VENDOR_ID : In    std_logic_vector (15 downto 0);
+              PCI_AD : InOut std_logic_vector (31 downto 0);
+             PCI_PAR : InOut std_logic;
+              AD_REG : Out   std_logic_vector (31 downto 0);
+             ADDR_REG : Out   std_logic_vector (31 downto 0);
+             CBE_REGn : Out   std_logic_vector (3 downto 0);
+             DEVSELn : Out   std_logic;
+             FIFO_RDn : Out   std_logic;
+             IO_WR_COM : Out   std_logic;
+             IRDY_REGn : Out   std_logic;
+             PCI_DEVSELn : Out   std_logic;
+             PCI_PERRn : Out   std_logic;
+             PCI_SERRn : Out   std_logic;
+             PCI_STOPn : Out   std_logic;
+             PCI_TRDYn : Out   std_logic;
+             READ_SEL : Out   std_logic_vector (1 downto 0);
+               TRDYn : Out   std_logic );
+end PCI_INTERFACE;
+
+architecture SCHEMATIC of PCI_INTERFACE is
+
+   SIGNAL gnd : std_logic := '0';
+   SIGNAL vcc : std_logic := '1';
+
+   signal IRDY_REGn_DUMMY : std_logic;
+   signal  PAR_REG : std_logic;
+   signal     PERR : std_logic;
+   signal     SERR : std_logic;
+   signal CF_RD_COM : std_logic;
+   signal CF_WR_COM : std_logic;
+   signal      LAR : std_logic;
+   signal  MY_ADDR : std_logic;
+   signal SERR_CHECK : std_logic;
+   signal IDSEL_REG : std_logic;
+   signal FRAME_REGn : std_logic;
+   signal PERR_CHECK : std_logic;
+   signal OE_PCI_PAR : std_logic;
+   signal OE_PCI_PERR : std_logic;
+   signal TRDYn_DUMMY : std_logic;
+   signal CONF_DATA_10H : std_logic_vector (31 downto 0);
+   signal CONF_DATA_04H : std_logic_vector (31 downto 0);
+   signal CONF_DATA : std_logic_vector (31 downto 0);
+   signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);
+   signal CBE_REGn_DUMMY : std_logic_vector (3 downto 0);
+   signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
+   signal ADDR_REG_DUMMY : std_logic_vector (31 downto 0);
+
+   component STEUERUNG
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+             FRAME_REGn : In    std_logic;
+             IDSEL_REG : In    std_logic;
+             IO_SPACE : In    std_logic;
+             MY_ADDR : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             READ_FIFO : In    std_logic;
+             CF_RD_COM : Out   std_logic;
+             CF_WR_COM : Out   std_logic;
+             DEVSELn : Out   std_logic;
+             FIFO_RDn : Out   std_logic;
+             IO_RD_COM : Out   std_logic;
+             IO_WR_COM : Out   std_logic;
+                 LAR : Out   std_logic;
+             OE_PCI_PAR : Out   std_logic;
+             OE_PCI_PERR : Out   std_logic;
+             PCI_DEVSELn : Out   std_logic;
+             PCI_STOPn : Out   std_logic;
+             PCI_TRDYn : Out   std_logic;
+             PERR_CHECK : Out   std_logic;
+                READ : Out   std_logic;
+             SERR_CHECK : Out   std_logic;
+               TRDYn : Out   std_logic );
+   end component;
+
+   component PARITY
+      Port ( OE_PCI_PAR : In    std_logic;
+             OE_PCI_PERR : In    std_logic;
+             PA_ER_RE : In    std_logic;
+              PAR_IN : In    std_logic_vector (35 downto 0);
+             PAR_REG : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             PERR_CHECK : In    std_logic;
+             SERR_CHECK : In    std_logic;
+             SERR_ENA : In    std_logic;
+             PCI_PAR : InOut std_logic;
+             PCI_PERRn : Out   std_logic;
+             PCI_SERRn : Out   std_logic;
+                PERR : Out   std_logic;
+                SERR : Out   std_logic );
+   end component;
+
+   component VERGLEICH
+      Port (    IN_A : In    std_logic_vector (31 downto 0);
+                IN_B : In    std_logic_vector (31 downto 0);
+             GLEICH_OUT : Out   std_logic );
+   end component;
+
+   component IO_MUX_REG
+      Port ( CONFIG_DATA : In    std_logic_vector (31 downto 0);
+             LOAD_ADDR_REG : In    std_logic;
+             PCI_CBEn : In    std_logic_vector (3 downto 0);
+             PCI_CLOCK : In    std_logic;
+             PCI_FRAMEn : In    std_logic;
+             PCI_IDSEL : In    std_logic;
+             PCI_IRDYn : In    std_logic;
+             PCI_PAR : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             READ_SEL : In    std_logic_vector (1 downto 0);
+             USER_DATA : In    std_logic_vector (31 downto 0);
+              PCI_AD : InOut std_logic_vector (31 downto 0);
+              AD_REG : Out   std_logic_vector (31 downto 0);
+             ADDR_REG : Out   std_logic_vector (31 downto 0);
+             CBE_REGn : Out   std_logic_vector (3 downto 0);
+             FRAME_REGn : Out   std_logic;
+             IDSEL_REG : Out   std_logic;
+             IRDY_REGn : Out   std_logic;
+             PAR_REG : Out   std_logic );
+   end component;
+
+   component CONFIG_SPACE_HEADER
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             ADDR_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+             CF_RD_COM : In    std_logic;
+             CF_WR_COM : In    std_logic;
+             IRDY_REGn : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+                PERR : In    std_logic;
+             REVISION_ID : In    std_logic_vector (7 downto 0);
+                SERR : In    std_logic;
+               TRDYn : In    std_logic;
+             VENDOR_ID : In    std_logic_vector (15 downto 0);
+             CONF_DATA : Out   std_logic_vector (31 downto 0);
+             CONF_DATA_04H : Out   std_logic_vector (31 downto 0);
+             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );
+   end component;
+
+begin
+
+   ADDR_REG <= ADDR_REG_DUMMY;
+   AD_REG <= AD_REG_DUMMY;
+   CBE_REGn <= CBE_REGn_DUMMY;
+   READ_SEL <= READ_SEL_DUMMY;
+   TRDYn <= TRDYn_DUMMY;
+   IRDY_REGn <= IRDY_REGn_DUMMY;
+
+   I7 : STEUERUNG
+      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+                 CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
+                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
+                 IO_SPACE=>CONF_DATA_04H(0), MY_ADDR=>MY_ADDR,
+                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
+                 READ_FIFO=>READ_FIFO, CF_RD_COM=>CF_RD_COM,
+                 CF_WR_COM=>CF_WR_COM, DEVSELn=>DEVSELn,
+                 FIFO_RDn=>FIFO_RDn, IO_RD_COM=>READ_SEL_DUMMY(0),
+                 IO_WR_COM=>IO_WR_COM, LAR=>LAR, OE_PCI_PAR=>OE_PCI_PAR,
+                 OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,
+                 PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,
+                 PERR_CHECK=>PERR_CHECK, READ=>READ_SEL_DUMMY(1),
+                 SERR_CHECK=>SERR_CHECK, TRDYn=>TRDYn_DUMMY );
+   I5 : PARITY
+      Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,
+                 PA_ER_RE=>CONF_DATA_04H(6),
+                 PAR_IN(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+                 PAR_IN(35 downto 32)=>CBE_REGn_DUMMY(3 downto 0),
+                 PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,
+                 PCI_RSTn=>PCI_RSTn, PERR_CHECK=>PERR_CHECK,
+                 SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8),
+                 PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn,
+                 PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR );
+   I4 : VERGLEICH
+      Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0),
+                 IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+                 GLEICH_OUT=>MY_ADDR );
+   I2 : IO_MUX_REG
+      Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
+                 LOAD_ADDR_REG=>LAR,
+                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
+                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
+                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
+                 PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
+                 READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
+                 USER_DATA(31 downto 0)=>USER_DATA_OUT(31 downto 0),
+                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
+                 AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+                 ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),
+                 CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
+                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
+                 IRDY_REGn=>IRDY_REGn_DUMMY, PAR_REG=>PAR_REG );
+   I1 : CONFIG_SPACE_HEADER
+      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+                 ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),
+                 CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),
+                 CF_RD_COM=>CF_RD_COM, CF_WR_COM=>CF_WR_COM,
+                 IRDY_REGn=>IRDY_REGn_DUMMY, PCI_CLOCK=>PCI_CLOCK,
+                 PCI_RSTn=>PCI_RSTn, PERR=>PERR,
+                 REVISION_ID(7 downto 0)=>REVISON_ID(7 downto 0),
+                 SERR=>SERR, TRDYn=>TRDYn_DUMMY,
+                 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
+                 CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0),
+                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0),
+                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) );
+
+end SCHEMATIC;

diff --git a/dhwk/source/pci_top.vhd b/dhwk/source/pci_top.vhd
index 64c94d6dc9c9829b071b9716c8ad5703915e16e2..f0b7a515ba47f65871ded349cdf021f4d1ab9db8 100644 (file)
--- a/dhwk/source/pci_top.vhd
+++ b/dhwk/source/pci_top.vhd
@@ -1,165 +1,165 @@
--- VHDL model created from schematic pci_top.sch -- Jan 09 09:34:14 2007\r
-\r
-\r
-\r
-LIBRARY ieee;\r
-\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-\r
-entity PCI_TOP is\r
-      Port (    FLAG : In    std_logic_vector (7 downto 0);\r
-             INT_REG : In    std_logic_vector (7 downto 0);\r
-             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_FRAMEn : In    std_logic;\r
-             PCI_IDSEL : In    std_logic;\r
-             PCI_IRDYn : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             R_FIFO_Q : In    std_logic_vector (7 downto 0);\r
-             REVISON_ID : In    std_logic_vector (7 downto 0);\r
-             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
-              PCI_AD : InOut std_logic_vector (31 downto 0);\r
-             PCI_PAR : InOut std_logic;\r
-              AD_REG : Out   std_logic_vector (31 downto 0);\r
-             DEVSELn : Out   std_logic;\r
-             FIFO_RDn : Out   std_logic;\r
-             PCI_DEVSELn : Out   std_logic;\r
-             PCI_PERRn : Out   std_logic;\r
-             PCI_SERRn : Out   std_logic;\r
-             PCI_STOPn : Out   std_logic;\r
-             PCI_TRDYn : Out   std_logic;\r
-             READ_SEL : Out   std_logic_vector (1 downto 0);\r
-             READ_XX1_0 : Out   std_logic;\r
-             READ_XX3_2 : Out   std_logic;\r
-             READ_XX5_4 : Out   std_logic;\r
-             READ_XX7_6 : Out   std_logic;\r
-             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
-             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
-             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);\r
-               TRDYn : Out   std_logic;\r
-             WRITE_XX1_0 : Out   std_logic;\r
-             WRITE_XX3_2 : Out   std_logic;\r
-             WRITE_XX5_4 : Out   std_logic;\r
-             WRITE_XX7_6 : Out   std_logic );\r
-end PCI_TOP;\r
-\r
-architecture SCHEMATIC of PCI_TOP is\r
-\r
-   SIGNAL gnd : std_logic := '0';\r
-   SIGNAL vcc : std_logic := '1';\r
-\r
-   signal IRDY_REGn : std_logic;\r
-   signal IO_WR_COM : std_logic;\r
-   signal TRDYn_DUMMY : std_logic;\r
-   signal READ_XX3_2_DUMMY : std_logic;\r
-   signal USER_DATA_OUT : std_logic_vector (31 downto 0);\r
-   signal CBE_REGn : std_logic_vector (3 downto 0);\r
-   signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
-   signal ADDR_REG : std_logic_vector (31 downto 0);\r
-   signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);\r
-\r
-   component USER_IO\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             ADDR_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-                FLAG : In    std_logic_vector (7 downto 0);\r
-             INT_REG : In    std_logic_vector (7 downto 0);\r
-             IO_WR_COM : In    std_logic;\r
-             IRDY_REGn : In    std_logic;\r
-             PCI_CLK : In    std_logic;\r
-             R_FIFO_Q : In    std_logic_vector (7 downto 0);\r
-             READ_SEL : In    std_logic_vector (1 downto 0);\r
-               TRDYn : In    std_logic;\r
-             READ_XX1_0 : Out   std_logic;\r
-             READ_XX3_2 : Out   std_logic;\r
-             READ_XX5_4 : Out   std_logic;\r
-             READ_XX7_6 : Out   std_logic;\r
-             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
-             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
-             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);\r
-             USER_DATA_OUT : Out   std_logic_vector (31 downto 0);\r
-             WRITE_XX1_0 : Out   std_logic;\r
-             WRITE_XX3_2 : Out   std_logic;\r
-             WRITE_XX5_4 : Out   std_logic;\r
-             WRITE_XX7_6 : Out   std_logic );\r
-   end component;\r
-\r
-   component PCI_INTERFACE\r
-      Port ( PCI_CBEn : In    std_logic_vector (3 downto 0);\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_FRAMEn : In    std_logic;\r
-             PCI_IDSEL : In    std_logic;\r
-             PCI_IRDYn : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             READ_FIFO : In    std_logic;\r
-             REVISON_ID : In    std_logic_vector (7 downto 0);\r
-             USER_DATA_OUT : In    std_logic_vector (31 downto 0);\r
-             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
-              PCI_AD : InOut std_logic_vector (31 downto 0);\r
-             PCI_PAR : InOut std_logic;\r
-              AD_REG : Out   std_logic_vector (31 downto 0);\r
-             ADDR_REG : Out   std_logic_vector (31 downto 0);\r
-             CBE_REGn : Out   std_logic_vector (3 downto 0);\r
-             DEVSELn : Out   std_logic;\r
-             FIFO_RDn : Out   std_logic;\r
-             IO_WR_COM : Out   std_logic;\r
-             IRDY_REGn : Out   std_logic;\r
-             PCI_DEVSELn : Out   std_logic;\r
-             PCI_PERRn : Out   std_logic;\r
-             PCI_SERRn : Out   std_logic;\r
-             PCI_STOPn : Out   std_logic;\r
-             PCI_TRDYn : Out   std_logic;\r
-             READ_SEL : Out   std_logic_vector (1 downto 0);\r
-               TRDYn : Out   std_logic );\r
-   end component;\r
-\r
-begin\r
-\r
-   READ_SEL <= READ_SEL_DUMMY;\r
-   AD_REG <= AD_REG_DUMMY;\r
-   READ_XX3_2 <= READ_XX3_2_DUMMY;\r
-   TRDYn <= TRDYn_DUMMY;\r
-\r
-   I19 : USER_IO\r
-      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
-                 ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
-                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
-                 FLAG(7 downto 0)=>FLAG(7 downto 0),\r
-                 INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
-                 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,\r
-                 PCI_CLK=>PCI_CLOCK,\r
-                 R_FIFO_Q(7 downto 0)=>R_FIFO_Q(7 downto 0),\r
-                 READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),\r
-                 TRDYn=>TRDYn_DUMMY, READ_XX1_0=>READ_XX1_0,\r
-                 READ_XX3_2=>READ_XX3_2_DUMMY, READ_XX5_4=>READ_XX5_4,\r
-                 READ_XX7_6=>READ_XX7_6,\r
-                 REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0(7 downto 0),\r
-                 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
-                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
-                 USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
-                 WRITE_XX1_0=>WRITE_XX1_0, WRITE_XX3_2=>WRITE_XX3_2,\r
-                 WRITE_XX5_4=>WRITE_XX5_4, WRITE_XX7_6=>WRITE_XX7_6 );\r
-   I10 : PCI_INTERFACE\r
-      Port Map ( PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
-                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
-                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
-                 PCI_RSTn=>PCI_RSTn, READ_FIFO=>READ_XX3_2_DUMMY,\r
-                 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
-                 USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
-                 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
-                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
-                 PCI_PAR=>PCI_PAR,\r
-                 AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
-                 ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
-                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
-                 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
-                 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,\r
-                 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
-                 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
-                 PCI_TRDYn=>PCI_TRDYn,\r
-                 READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),\r
-                 TRDYn=>TRDYn_DUMMY );\r
-\r
-end SCHEMATIC;\r
+-- VHDL model created from schematic pci_top.sch -- Jan 09 09:34:14 2007
+
+
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity PCI_TOP is
+      Port (    FLAG : In    std_logic_vector (7 downto 0);
+             INT_REG : In    std_logic_vector (7 downto 0);
+             PCI_CBEn : In    std_logic_vector (3 downto 0);
+             PCI_CLOCK : In    std_logic;
+             PCI_FRAMEn : In    std_logic;
+             PCI_IDSEL : In    std_logic;
+             PCI_IRDYn : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             R_FIFO_Q : In    std_logic_vector (7 downto 0);
+             REVISON_ID : In    std_logic_vector (7 downto 0);
+             VENDOR_ID : In    std_logic_vector (15 downto 0);
+              PCI_AD : InOut std_logic_vector (31 downto 0);
+             PCI_PAR : InOut std_logic;
+              AD_REG : Out   std_logic_vector (31 downto 0);
+             DEVSELn : Out   std_logic;
+             FIFO_RDn : Out   std_logic;
+             PCI_DEVSELn : Out   std_logic;
+             PCI_PERRn : Out   std_logic;
+             PCI_SERRn : Out   std_logic;
+             PCI_STOPn : Out   std_logic;
+             PCI_TRDYn : Out   std_logic;
+             READ_SEL : Out   std_logic_vector (1 downto 0);
+             READ_XX1_0 : Out   std_logic;
+             READ_XX3_2 : Out   std_logic;
+             READ_XX5_4 : Out   std_logic;
+             READ_XX7_6 : Out   std_logic;
+             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);
+             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);
+             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);
+               TRDYn : Out   std_logic;
+             WRITE_XX1_0 : Out   std_logic;
+             WRITE_XX3_2 : Out   std_logic;
+             WRITE_XX5_4 : Out   std_logic;
+             WRITE_XX7_6 : Out   std_logic );
+end PCI_TOP;
+
+architecture SCHEMATIC of PCI_TOP is
+
+   SIGNAL gnd : std_logic := '0';
+   SIGNAL vcc : std_logic := '1';
+
+   signal IRDY_REGn : std_logic;
+   signal IO_WR_COM : std_logic;
+   signal TRDYn_DUMMY : std_logic;
+   signal READ_XX3_2_DUMMY : std_logic;
+   signal USER_DATA_OUT : std_logic_vector (31 downto 0);
+   signal CBE_REGn : std_logic_vector (3 downto 0);
+   signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
+   signal ADDR_REG : std_logic_vector (31 downto 0);
+   signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);
+
+   component USER_IO
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             ADDR_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+                FLAG : In    std_logic_vector (7 downto 0);
+             INT_REG : In    std_logic_vector (7 downto 0);
+             IO_WR_COM : In    std_logic;
+             IRDY_REGn : In    std_logic;
+             PCI_CLK : In    std_logic;
+             R_FIFO_Q : In    std_logic_vector (7 downto 0);
+             READ_SEL : In    std_logic_vector (1 downto 0);
+               TRDYn : In    std_logic;
+             READ_XX1_0 : Out   std_logic;
+             READ_XX3_2 : Out   std_logic;
+             READ_XX5_4 : Out   std_logic;
+             READ_XX7_6 : Out   std_logic;
+             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);
+             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);
+             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);
+             USER_DATA_OUT : Out   std_logic_vector (31 downto 0);
+             WRITE_XX1_0 : Out   std_logic;
+             WRITE_XX3_2 : Out   std_logic;
+             WRITE_XX5_4 : Out   std_logic;
+             WRITE_XX7_6 : Out   std_logic );
+   end component;
+
+   component PCI_INTERFACE
+      Port ( PCI_CBEn : In    std_logic_vector (3 downto 0);
+             PCI_CLOCK : In    std_logic;
+             PCI_FRAMEn : In    std_logic;
+             PCI_IDSEL : In    std_logic;
+             PCI_IRDYn : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             READ_FIFO : In    std_logic;
+             REVISON_ID : In    std_logic_vector (7 downto 0);
+             USER_DATA_OUT : In    std_logic_vector (31 downto 0);
+             VENDOR_ID : In    std_logic_vector (15 downto 0);
+              PCI_AD : InOut std_logic_vector (31 downto 0);
+             PCI_PAR : InOut std_logic;
+              AD_REG : Out   std_logic_vector (31 downto 0);
+             ADDR_REG : Out   std_logic_vector (31 downto 0);
+             CBE_REGn : Out   std_logic_vector (3 downto 0);
+             DEVSELn : Out   std_logic;
+             FIFO_RDn : Out   std_logic;
+             IO_WR_COM : Out   std_logic;
+             IRDY_REGn : Out   std_logic;
+             PCI_DEVSELn : Out   std_logic;
+             PCI_PERRn : Out   std_logic;
+             PCI_SERRn : Out   std_logic;
+             PCI_STOPn : Out   std_logic;
+             PCI_TRDYn : Out   std_logic;
+             READ_SEL : Out   std_logic_vector (1 downto 0);
+               TRDYn : Out   std_logic );
+   end component;
+
+begin
+
+   READ_SEL <= READ_SEL_DUMMY;
+   AD_REG <= AD_REG_DUMMY;
+   READ_XX3_2 <= READ_XX3_2_DUMMY;
+   TRDYn <= TRDYn_DUMMY;
+
+   I19 : USER_IO
+      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+                 ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+                 FLAG(7 downto 0)=>FLAG(7 downto 0),
+                 INT_REG(7 downto 0)=>INT_REG(7 downto 0),
+                 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
+                 PCI_CLK=>PCI_CLOCK,
+                 R_FIFO_Q(7 downto 0)=>R_FIFO_Q(7 downto 0),
+                 READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
+                 TRDYn=>TRDYn_DUMMY, READ_XX1_0=>READ_XX1_0,
+                 READ_XX3_2=>READ_XX3_2_DUMMY, READ_XX5_4=>READ_XX5_4,
+                 READ_XX7_6=>READ_XX7_6,
+                 REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0(7 downto 0),
+                 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
+                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
+                 USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
+                 WRITE_XX1_0=>WRITE_XX1_0, WRITE_XX3_2=>WRITE_XX3_2,
+                 WRITE_XX5_4=>WRITE_XX5_4, WRITE_XX7_6=>WRITE_XX7_6 );
+   I10 : PCI_INTERFACE
+      Port Map ( PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
+                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
+                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
+                 PCI_RSTn=>PCI_RSTn, READ_FIFO=>READ_XX3_2_DUMMY,
+                 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
+                 USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
+                 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
+                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
+                 PCI_PAR=>PCI_PAR,
+                 AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
+                 ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+                 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
+                 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
+                 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
+                 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
+                 PCI_TRDYn=>PCI_TRDYn,
+                 READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
+                 TRDYn=>TRDYn_DUMMY );
+
+end SCHEMATIC;

diff --git a/dhwk/source/reg_io.vhd b/dhwk/source/reg_io.vhd
index 1e338102ab8610b0df8938953ba261b38ad58398..610861e05955140afb993f9658dadfe6195bd8b1 100644 (file)
--- a/dhwk/source/reg_io.vhd
+++ b/dhwk/source/reg_io.vhd
@@ -1,54 +1,54 @@
--- VHDL model created from schematic reg_io.sch -- Jan 09 09:34:12 2007\r
-\r
-\r
-\r
-LIBRARY ieee;\r
-\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-\r
-entity REG_IO is\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             PCI_CLOCK : In    std_logic;\r
-               RESET : In    std_logic;\r
-             WRITE_XX1_0 : In    std_logic;\r
-             WRITE_XX7_6 : In    std_logic;\r
-             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
-             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
-             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0) );\r
-end REG_IO;\r
-\r
-architecture SCHEMATIC of REG_IO is\r
-\r
-   SIGNAL gnd : std_logic := '0';\r
-   SIGNAL vcc : std_logic := '1';\r
-\r
-\r
-   component REG\r
-      Port (   CLOCK : In    std_logic;\r
-              REG_IN : In    std_logic_vector (7 downto 0);\r
-               RESET : In    std_logic;\r
-               WRITE : In    std_logic;\r
-             REG_OUT : Out   std_logic_vector (7 downto 0) );\r
-   end component;\r
-\r
-begin\r
-\r
-   I14 : REG\r
-      Port Map ( CLOCK=>PCI_CLOCK,\r
-                 REG_IN(7 downto 0)=>AD_REG(7 downto 0), RESET=>RESET,\r
-                 WRITE=>WRITE_XX1_0,\r
-                 REG_OUT(7 downto 0)=>REG_OUT_XX0(7 downto 0) );\r
-   I15 : REG\r
-      Port Map ( CLOCK=>PCI_CLOCK,\r
-                 REG_IN(7 downto 0)=>AD_REG(31 downto 24), RESET=>RESET,\r
-                 WRITE=>WRITE_XX7_6,\r
-                 REG_OUT(7 downto 0)=>REG_OUT_XX7(7 downto 0) );\r
-   I16 : REG\r
-      Port Map ( CLOCK=>PCI_CLOCK,\r
-                 REG_IN(7 downto 0)=>AD_REG(23 downto 16), RESET=>RESET,\r
-                 WRITE=>WRITE_XX7_6,\r
-                 REG_OUT(7 downto 0)=>REG_OUT_XX6(7 downto 0) );\r
-\r
-end SCHEMATIC;\r
+-- VHDL model created from schematic reg_io.sch -- Jan 09 09:34:12 2007
+
+
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity REG_IO is
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             PCI_CLOCK : In    std_logic;
+               RESET : In    std_logic;
+             WRITE_XX1_0 : In    std_logic;
+             WRITE_XX7_6 : In    std_logic;
+             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);
+             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);
+             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0) );
+end REG_IO;
+
+architecture SCHEMATIC of REG_IO is
+
+   SIGNAL gnd : std_logic := '0';
+   SIGNAL vcc : std_logic := '1';
+
+
+   component REG
+      Port (   CLOCK : In    std_logic;
+              REG_IN : In    std_logic_vector (7 downto 0);
+               RESET : In    std_logic;
+               WRITE : In    std_logic;
+             REG_OUT : Out   std_logic_vector (7 downto 0) );
+   end component;
+
+begin
+
+   I14 : REG
+      Port Map ( CLOCK=>PCI_CLOCK,
+                 REG_IN(7 downto 0)=>AD_REG(7 downto 0), RESET=>RESET,
+                 WRITE=>WRITE_XX1_0,
+                 REG_OUT(7 downto 0)=>REG_OUT_XX0(7 downto 0) );
+   I15 : REG
+      Port Map ( CLOCK=>PCI_CLOCK,
+                 REG_IN(7 downto 0)=>AD_REG(31 downto 24), RESET=>RESET,
+                 WRITE=>WRITE_XX7_6,
+                 REG_OUT(7 downto 0)=>REG_OUT_XX7(7 downto 0) );
+   I16 : REG
+      Port Map ( CLOCK=>PCI_CLOCK,
+                 REG_IN(7 downto 0)=>AD_REG(23 downto 16), RESET=>RESET,
+                 WRITE=>WRITE_XX7_6,
+                 REG_OUT(7 downto 0)=>REG_OUT_XX6(7 downto 0) );
+
+end SCHEMATIC;

diff --git a/dhwk/source/steuerung.vhd b/dhwk/source/steuerung.vhd
index 90922dc165d9d0b011ddec0364fbd68a628d1746..f0bee2069fc0abd8feb8cc95ec6f46264ce87683 100644 (file)
--- a/dhwk/source/steuerung.vhd
+++ b/dhwk/source/steuerung.vhd
@@ -1,131 +1,131 @@
--- VHDL model created from schematic steuerung.sch -- Jan 09 09:34:14 2007\r
-\r
--- LIBRARY vanmacro;\r
--- USE vanmacro.components.ALL;\r
-LIBRARY ieee;\r
---LIBRARY generics;\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
---USE generics.components.ALL;\r
-\r
-entity STEUERUNG is\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-             FRAME_REGn : In    std_logic;\r
-             IDSEL_REG : In    std_logic;\r
-             IO_SPACE : In    std_logic;\r
-             MY_ADDR : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             READ_FIFO : In    std_logic;\r
-             CF_RD_COM : Out   std_logic;\r
-             CF_WR_COM : Out   std_logic;\r
-             DEVSELn : Out   std_logic;\r
-             FIFO_RDn : Out   std_logic;\r
-             IO_RD_COM : Out   std_logic;\r
-             IO_WR_COM : Out   std_logic;\r
-                 LAR : Out   std_logic;\r
-             OE_PCI_PAR : Out   std_logic;\r
-             OE_PCI_PERR : Out   std_logic;\r
-             PCI_DEVSELn : Out   std_logic;\r
-             PCI_STOPn : Out   std_logic;\r
-             PCI_TRDYn : Out   std_logic;\r
-             PERR_CHECK : Out   std_logic;\r
-                READ : Out   std_logic;\r
-             SERR_CHECK : Out   std_logic;\r
-               TRDYn : Out   std_logic );\r
-end STEUERUNG;\r
-\r
-architecture SCHEMATIC of STEUERUNG is\r
-\r
-   SIGNAL gnd : std_logic := '0';\r
-   SIGNAL vcc : std_logic := '1';\r
-\r
-   signal DEVSELn_DUMMY : std_logic;\r
-   signal  IO_READ : std_logic;\r
-   signal IO_WRITE : std_logic;\r
-   signal CONF_READ : std_logic;\r
-   signal CONF_WRITE : std_logic;\r
-\r
-   component CONT_FSM\r
-      Port ( CONF_READ : In    std_logic;\r
-             CONF_WRITE : In    std_logic;\r
-             FIFO_READ : In    std_logic;\r
-             IO_READ : In    std_logic;\r
-             IO_WRITE : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             DEVSELn : Out   std_logic;\r
-             FIFO_RDn : Out   std_logic;\r
-             OE_PCI_PAR : Out   std_logic;\r
-             OE_PCI_PERR : Out   std_logic;\r
-             PCI_DEVSELn : Out   std_logic;\r
-             PCI_STOPn : Out   std_logic;\r
-             PCI_TRDYn : Out   std_logic;\r
-             PERR_CHECK : Out   std_logic;\r
-                READ : Out   std_logic;\r
-               TRDYn : Out   std_logic );\r
-   end component;\r
-\r
-   component COMM_FSM\r
-      Port ( CONF_READ : In    std_logic;\r
-             CONF_WRITE : In    std_logic;\r
-             DEVSELn : In    std_logic;\r
-             IO_READ : In    std_logic;\r
-             IO_WRITE : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             CF_RD_COM : Out   std_logic;\r
-             CF_WR_COM : Out   std_logic;\r
-             IO_RD_COM : Out   std_logic;\r
-             IO_WR_COM : Out   std_logic );\r
-   end component;\r
-\r
-   component COMM_DEC\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-             FRAME_REGn : In    std_logic;\r
-             IDSEL_REG : In    std_logic;\r
-             IO_SPACE : In    std_logic;\r
-             MY_ADDR : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             CONF_READ : Out   std_logic;\r
-             CONF_WRITE : Out   std_logic;\r
-             IO_READ : Out   std_logic;\r
-             IO_WRITE : Out   std_logic;\r
-                 LAR : Out   std_logic;\r
-             SERR_CHECK : Out   std_logic );\r
-   end component;\r
-\r
-begin\r
-\r
-   DEVSELn <= DEVSELn_DUMMY;\r
-\r
-   I1 : CONT_FSM\r
-      Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,\r
-                 FIFO_READ=>READ_FIFO, IO_READ=>IO_READ,\r
-                 IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,\r
-                 PCI_RSTn=>PCI_RSTn, DEVSELn=>DEVSELn_DUMMY,\r
-                 FIFO_RDn=>FIFO_RDn, OE_PCI_PAR=>OE_PCI_PAR,\r
-                 OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,\r
-                 PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,\r
-                 PERR_CHECK=>PERR_CHECK, READ=>READ, TRDYn=>TRDYn );\r
-   I2 : COMM_FSM\r
-      Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,\r
-                 DEVSELn=>DEVSELn_DUMMY, IO_READ=>IO_READ,\r
-                 IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,\r
-                 PCI_RSTn=>PCI_RSTn, CF_RD_COM=>CF_RD_COM,\r
-                 CF_WR_COM=>CF_WR_COM, IO_RD_COM=>IO_RD_COM,\r
-                 IO_WR_COM=>IO_WR_COM );\r
-   I3 : COMM_DEC\r
-      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
-                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
-                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
-                 IO_SPACE=>IO_SPACE, MY_ADDR=>MY_ADDR,\r
-                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
-                 CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,\r
-                 IO_READ=>IO_READ, IO_WRITE=>IO_WRITE, LAR=>LAR,\r
-                 SERR_CHECK=>SERR_CHECK );\r
-\r
-end SCHEMATIC;\r
+-- VHDL model created from schematic steuerung.sch -- Jan 09 09:34:14 2007
+
+-- LIBRARY vanmacro;
+-- USE vanmacro.components.ALL;
+LIBRARY ieee;
+--LIBRARY generics;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+--USE generics.components.ALL;
+
+entity STEUERUNG is
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+             FRAME_REGn : In    std_logic;
+             IDSEL_REG : In    std_logic;
+             IO_SPACE : In    std_logic;
+             MY_ADDR : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             READ_FIFO : In    std_logic;
+             CF_RD_COM : Out   std_logic;
+             CF_WR_COM : Out   std_logic;
+             DEVSELn : Out   std_logic;
+             FIFO_RDn : Out   std_logic;
+             IO_RD_COM : Out   std_logic;
+             IO_WR_COM : Out   std_logic;
+                 LAR : Out   std_logic;
+             OE_PCI_PAR : Out   std_logic;
+             OE_PCI_PERR : Out   std_logic;
+             PCI_DEVSELn : Out   std_logic;
+             PCI_STOPn : Out   std_logic;
+             PCI_TRDYn : Out   std_logic;
+             PERR_CHECK : Out   std_logic;
+                READ : Out   std_logic;
+             SERR_CHECK : Out   std_logic;
+               TRDYn : Out   std_logic );
+end STEUERUNG;
+
+architecture SCHEMATIC of STEUERUNG is
+
+   SIGNAL gnd : std_logic := '0';
+   SIGNAL vcc : std_logic := '1';
+
+   signal DEVSELn_DUMMY : std_logic;
+   signal  IO_READ : std_logic;
+   signal IO_WRITE : std_logic;
+   signal CONF_READ : std_logic;
+   signal CONF_WRITE : std_logic;
+
+   component CONT_FSM
+      Port ( CONF_READ : In    std_logic;
+             CONF_WRITE : In    std_logic;
+             FIFO_READ : In    std_logic;
+             IO_READ : In    std_logic;
+             IO_WRITE : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             DEVSELn : Out   std_logic;
+             FIFO_RDn : Out   std_logic;
+             OE_PCI_PAR : Out   std_logic;
+             OE_PCI_PERR : Out   std_logic;
+             PCI_DEVSELn : Out   std_logic;
+             PCI_STOPn : Out   std_logic;
+             PCI_TRDYn : Out   std_logic;
+             PERR_CHECK : Out   std_logic;
+                READ : Out   std_logic;
+               TRDYn : Out   std_logic );
+   end component;
+
+   component COMM_FSM
+      Port ( CONF_READ : In    std_logic;
+             CONF_WRITE : In    std_logic;
+             DEVSELn : In    std_logic;
+             IO_READ : In    std_logic;
+             IO_WRITE : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             CF_RD_COM : Out   std_logic;
+             CF_WR_COM : Out   std_logic;
+             IO_RD_COM : Out   std_logic;
+             IO_WR_COM : Out   std_logic );
+   end component;
+
+   component COMM_DEC
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+             FRAME_REGn : In    std_logic;
+             IDSEL_REG : In    std_logic;
+             IO_SPACE : In    std_logic;
+             MY_ADDR : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             CONF_READ : Out   std_logic;
+             CONF_WRITE : Out   std_logic;
+             IO_READ : Out   std_logic;
+             IO_WRITE : Out   std_logic;
+                 LAR : Out   std_logic;
+             SERR_CHECK : Out   std_logic );
+   end component;
+
+begin
+
+   DEVSELn <= DEVSELn_DUMMY;
+
+   I1 : CONT_FSM
+      Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
+                 FIFO_READ=>READ_FIFO, IO_READ=>IO_READ,
+                 IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,
+                 PCI_RSTn=>PCI_RSTn, DEVSELn=>DEVSELn_DUMMY,
+                 FIFO_RDn=>FIFO_RDn, OE_PCI_PAR=>OE_PCI_PAR,
+                 OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,
+                 PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,
+                 PERR_CHECK=>PERR_CHECK, READ=>READ, TRDYn=>TRDYn );
+   I2 : COMM_FSM
+      Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
+                 DEVSELn=>DEVSELn_DUMMY, IO_READ=>IO_READ,
+                 IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,
+                 PCI_RSTn=>PCI_RSTn, CF_RD_COM=>CF_RD_COM,
+                 CF_WR_COM=>CF_WR_COM, IO_RD_COM=>IO_RD_COM,
+                 IO_WR_COM=>IO_WR_COM );
+   I3 : COMM_DEC
+      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,
+                 IO_SPACE=>IO_SPACE, MY_ADDR=>MY_ADDR,
+                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
+                 CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,
+                 IO_READ=>IO_READ, IO_WRITE=>IO_WRITE, LAR=>LAR,
+                 SERR_CHECK=>SERR_CHECK );
+
+end SCHEMATIC;

diff --git a/dhwk/source/synplify.vhd b/dhwk/source/synplify.vhd
index 904bf0d2681b2f58293453239f8daadd09794666..09137f67f96271ea292967b0eab2b4c6551d2caf 100644 (file)
--- a/dhwk/source/synplify.vhd
+++ b/dhwk/source/synplify.vhd
@@ -1,184 +1,184 @@
------------------------------------------------------------------------------\r
---                                                                         --\r
--- Copyright (c) 1997 by Synplicity, Inc.  All rights reserved.            --\r
---                                                                         --\r
--- This source file may be used and distributed without restriction        --\r
--- provided that this copyright statement is not removed from the file     --\r
--- and that any derivative work contains this copyright notice.            --\r
---                                                                         --\r
--- Primitive library for post synthesis simulation                         --\r
--- These models are not intended for efficient synthesis                   --\r
---                                                                         --\r
------------------------------------------------------------------------------\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-entity prim_counter is\r
-    generic (w : integer := 8);\r
-    port (\r
-        q : buffer std_logic_vector(w - 1 downto 0);\r
-        cout : out std_logic;\r
-        d : in std_logic_vector(w - 1 downto 0);\r
-        cin : in std_logic;\r
-        clk : in std_logic;\r
-        rst : in std_logic;\r
-        load : in std_logic;\r
-        en : in std_logic;\r
-        updn : in std_logic\r
-    );\r
-end prim_counter;\r
-\r
-architecture beh of prim_counter is\r
-    signal nextq : std_logic_vector(w - 1 downto 0);\r
-begin\r
-    nxt: process (q, cin, updn)\r
-        variable i : integer;\r
-        variable nextc, c : std_logic;\r
-    begin\r
-        nextc := cin;\r
-        for i in 0 to w - 1 loop\r
-            c := nextc;\r
-            nextq(i) <= c xor (not updn) xor q(i);\r
-            nextc := (c and (not updn)) or \r
-                 (c and q(i)) or\r
-                 ((not updn) and q(i));\r
-        end loop;\r
-        cout <= nextc;\r
-    end process;\r
-\r
-    ff : process (clk, rst)\r
-    begin\r
-        if rst = '1' then\r
-            q <= (others => '0');\r
-        elsif rising_edge(clk) then\r
-            q <= nextq;\r
-        end if;\r
-    end process ff;\r
-end beh;\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-entity prim_dff is\r
-    port (q : out std_logic;\r
-          d : in std_logic;\r
-          clk : in std_logic;\r
-          r : in std_logic := '0';\r
-          s : in std_logic := '0');\r
-end prim_dff;\r
-\r
-architecture beh of prim_dff is\r
-begin\r
-    ff : process (clk, r, s)\r
-    begin\r
-        if r = '1' then\r
-            q <= '0';\r
-        elsif s = '1' then\r
-            q <= '1';\r
-        elsif rising_edge(clk) then\r
-            q <= d;\r
-        end if;\r
-    end process ff;\r
-end beh;\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-entity prim_latch is\r
-    port (q : out std_logic;\r
-          d : in std_logic;\r
-          clk : in std_logic;\r
-          r : in std_logic := '0';\r
-          s : in std_logic := '0');\r
-end prim_latch;\r
-\r
-architecture beh of prim_latch is\r
-begin\r
-    q <= '0' when r = '1' else\r
-         '1' when s = '1' else\r
-         d when clk = '1';\r
-end beh;\r
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.std_logic_unsigned.all;\r
-\r
-entity prim_ramd is\r
-generic (\r
-   data_width : integer := 4;\r
-    addr_width : integer := 5);\r
-port (\r
-    dout : out std_logic_vector(data_width-1 downto 0);\r
-    aout : in std_logic_vector(addr_width-1 downto 0);\r
-    din  : in std_logic_vector(data_width-1 downto 0);\r
-    ain : in std_logic_vector(addr_width-1 downto 0);\r
-    we   : in std_logic;\r
-    clk  : in std_logic);\r
-end prim_ramd;\r
-\r
-architecture beh of prim_ramd is\r
-\r
-constant depth : integer := 2** addr_width;\r
-type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);\r
-signal mem: mem_type;\r
-\r
-begin  \r
-\r
-dout <= mem(conv_integer(aout));\r
-\r
-process (clk)\r
-    begin\r
-        if rising_edge(clk) then    \r
-            if (we = '1') then\r
-                mem(conv_integer(ain)) <= din;\r
-            end if;\r
-        end if;\r
-end process;\r
-\r
-end beh ;\r
-\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-package components is\r
-    component prim_counter\r
-        generic (w : integer);\r
-        port (\r
-            q : buffer std_logic_vector(w - 1 downto 0);\r
-            cout : out std_logic;\r
-            d : in std_logic_vector(w - 1 downto 0);\r
-            cin : in std_logic;\r
-            clk : in std_logic;\r
-            rst : in std_logic;\r
-            load : in std_logic;\r
-            en : in std_logic;\r
-            updn : in std_logic\r
-        );\r
-    end component;\r
-    component prim_dff\r
-        port (q : out std_logic;\r
-              d : in std_logic;\r
-              clk : in std_logic;\r
-              r : in std_logic := '0';\r
-              s : in std_logic := '0');\r
-    end component;\r
-    component prim_latch\r
-        port (q : out std_logic;\r
-              d : in std_logic;\r
-              clk : in std_logic;\r
-              r : in std_logic := '0';\r
-              s : in std_logic := '0');\r
-    end component;\r
-\r
-    component prim_ramd is\r
-    generic (\r
-        data_width : integer := 4;\r
-        addr_width : integer := 5);\r
-    port (\r
-        dout : out std_logic_vector(data_width-1 downto 0);\r
-        aout : in std_logic_vector(addr_width-1 downto 0);\r
-        din  : in std_logic_vector(data_width-1 downto 0);\r
-        ain : in std_logic_vector(addr_width-1 downto 0);\r
-        we   : in std_logic;\r
-        clk  : in std_logic);\r
-    end component;\r
-\r
-end components;\r
+-----------------------------------------------------------------------------
+--                                                                         --
+-- Copyright (c) 1997 by Synplicity, Inc.  All rights reserved.            --
+--                                                                         --
+-- This source file may be used and distributed without restriction        --
+-- provided that this copyright statement is not removed from the file     --
+-- and that any derivative work contains this copyright notice.            --
+--                                                                         --
+-- Primitive library for post synthesis simulation                         --
+-- These models are not intended for efficient synthesis                   --
+--                                                                         --
+-----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+entity prim_counter is
+    generic (w : integer := 8);
+    port (
+        q : buffer std_logic_vector(w - 1 downto 0);
+        cout : out std_logic;
+        d : in std_logic_vector(w - 1 downto 0);
+        cin : in std_logic;
+        clk : in std_logic;
+        rst : in std_logic;
+        load : in std_logic;
+        en : in std_logic;
+        updn : in std_logic
+    );
+end prim_counter;
+
+architecture beh of prim_counter is
+    signal nextq : std_logic_vector(w - 1 downto 0);
+begin
+    nxt: process (q, cin, updn)
+        variable i : integer;
+        variable nextc, c : std_logic;
+    begin
+        nextc := cin;
+        for i in 0 to w - 1 loop
+            c := nextc;
+            nextq(i) <= c xor (not updn) xor q(i);
+            nextc := (c and (not updn)) or 
+                 (c and q(i)) or
+                 ((not updn) and q(i));
+        end loop;
+        cout <= nextc;
+    end process;
+
+    ff : process (clk, rst)
+    begin
+        if rst = '1' then
+            q <= (others => '0');
+        elsif rising_edge(clk) then
+            q <= nextq;
+        end if;
+    end process ff;
+end beh;
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity prim_dff is
+    port (q : out std_logic;
+          d : in std_logic;
+          clk : in std_logic;
+          r : in std_logic := '0';
+          s : in std_logic := '0');
+end prim_dff;
+
+architecture beh of prim_dff is
+begin
+    ff : process (clk, r, s)
+    begin
+        if r = '1' then
+            q <= '0';
+        elsif s = '1' then
+            q <= '1';
+        elsif rising_edge(clk) then
+            q <= d;
+        end if;
+    end process ff;
+end beh;
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity prim_latch is
+    port (q : out std_logic;
+          d : in std_logic;
+          clk : in std_logic;
+          r : in std_logic := '0';
+          s : in std_logic := '0');
+end prim_latch;
+
+architecture beh of prim_latch is
+begin
+    q <= '0' when r = '1' else
+         '1' when s = '1' else
+         d when clk = '1';
+end beh;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity prim_ramd is
+generic (
+   data_width : integer := 4;
+    addr_width : integer := 5);
+port (
+    dout : out std_logic_vector(data_width-1 downto 0);
+    aout : in std_logic_vector(addr_width-1 downto 0);
+    din  : in std_logic_vector(data_width-1 downto 0);
+    ain : in std_logic_vector(addr_width-1 downto 0);
+    we   : in std_logic;
+    clk  : in std_logic);
+end prim_ramd;
+
+architecture beh of prim_ramd is
+
+constant depth : integer := 2** addr_width;
+type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
+signal mem: mem_type;
+
+begin  
+
+dout <= mem(conv_integer(aout));
+
+process (clk)
+    begin
+        if rising_edge(clk) then    
+            if (we = '1') then
+                mem(conv_integer(ain)) <= din;
+            end if;
+        end if;
+end process;
+
+end beh ;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+package components is
+    component prim_counter
+        generic (w : integer);
+        port (
+            q : buffer std_logic_vector(w - 1 downto 0);
+            cout : out std_logic;
+            d : in std_logic_vector(w - 1 downto 0);
+            cin : in std_logic;
+            clk : in std_logic;
+            rst : in std_logic;
+            load : in std_logic;
+            en : in std_logic;
+            updn : in std_logic
+        );
+    end component;
+    component prim_dff
+        port (q : out std_logic;
+              d : in std_logic;
+              clk : in std_logic;
+              r : in std_logic := '0';
+              s : in std_logic := '0');
+    end component;
+    component prim_latch
+        port (q : out std_logic;
+              d : in std_logic;
+              clk : in std_logic;
+              r : in std_logic := '0';
+              s : in std_logic := '0');
+    end component;
+
+    component prim_ramd is
+    generic (
+        data_width : integer := 4;
+        addr_width : integer := 5);
+    port (
+        dout : out std_logic_vector(data_width-1 downto 0);
+        aout : in std_logic_vector(addr_width-1 downto 0);
+        din  : in std_logic_vector(data_width-1 downto 0);
+        ain : in std_logic_vector(addr_width-1 downto 0);
+        we   : in std_logic;
+        clk  : in std_logic);
+    end component;
+
+end components;

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index a148b3884ed09abd9c7dc5d29115a38fa0bd7813..2bf0f5d17249a2fa631b61593001ab18c0fec58a 100644 (file)
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -1,427 +1,427 @@
--- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007\r
-\r
-\r
-\r
-LIBRARY ieee;\r
-\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-\r
-entity dhwk is\r
-      Port ( KONST_1 : In    std_logic;\r
-             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_FRAMEn : In    std_logic;\r
-             PCI_IDSEL : In    std_logic;\r
-             PCI_IRDYn : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
---             SERIAL_IN : In    std_logic;\r
---             SPC_RDY_IN : In    std_logic;\r
-             TAST_RESn : In    std_logic;\r
-             TAST_SETn : In    std_logic;\r
-             LED_2 : out    std_logic;\r
-             LED_3 : out    std_logic;\r
-             LED_4 : out    std_logic;\r
-             LED_5 : out    std_logic;\r
-              PCI_AD : InOut std_logic_vector (31 downto 0);\r
-             PCI_PAR : InOut std_logic;\r
-             PCI_DEVSELn : Out   std_logic;\r
-             PCI_INTAn : Out   std_logic;\r
-             PCI_PERRn : Out   std_logic;\r
-             PCI_SERRn : Out   std_logic;\r
-             PCI_STOPn : Out   std_logic;\r
-             PCI_TRDYn : Out   std_logic;\r
-            PCI_REQn : Out std_logic;\r
-            PCI_GNTn : In std_logic;\r
---             SERIAL_OUT : Out   std_logic;\r
---             SPC_RDY_OUT : Out   std_logic;\r
-             TB_IDSEL : Out   std_logic;\r
-             TB_nDEVSEL : Out   std_logic;\r
-             TB_nINTA : Out   std_logic );\r
-end dhwk;\r
-\r
-architecture SCHEMATIC of dhwk is\r
-\r
-   SIGNAL gnd : std_logic := '0';\r
-   SIGNAL vcc : std_logic := '1';\r
-\r
-   signal READ_XX7_6 : std_logic;\r
-   signal  RESERVE : std_logic;\r
-   signal SR_ERROR : std_logic;\r
-   signal  R_ERROR : std_logic;\r
-   signal  S_ERROR : std_logic;\r
-   signal WRITE_XX3_2 : std_logic;\r
-   signal WRITE_XX5_4 : std_logic;\r
-   signal WRITE_XX7_6 : std_logic;\r
-   signal READ_XX1_0 : std_logic;\r
-   signal READ_XX3_2 : std_logic;\r
-   signal    INTAn : std_logic;\r
-   signal    TRDYn : std_logic;\r
-   signal READ_XX5_4 : std_logic;\r
-   signal  DEVSELn : std_logic;\r
-   signal FIFO_RDn : std_logic;\r
-   signal WRITE_XX1_0 : std_logic;\r
-   signal REG_OUT_XX6 : std_logic_vector (7 downto 0);\r
-   signal SYNC_FLAG : std_logic_vector (7 downto 0);\r
-   signal  INT_REG : std_logic_vector (7 downto 0);\r
-   signal REVISON_ID : std_logic_vector (7 downto 0);\r
-   signal VENDOR_ID : std_logic_vector (15 downto 0);\r
-   signal READ_SEL : std_logic_vector (1 downto 0);\r
-   signal   AD_REG : std_logic_vector (31 downto 0);\r
-   signal REG_OUT_XX7 : std_logic_vector (7 downto 0);\r
-   signal R_EFn : std_logic;\r
-   signal R_FFn : std_logic;\r
-   signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
-   signal R_HFn : std_logic;\r
-   signal S_EFn : std_logic;\r
-   signal S_FFn : std_logic;\r
-   signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
-   signal S_HFn : std_logic;\r
-   signal R_FIFO_D_IN : std_logic_vector (7 downto 0);\r
-   signal R_FIFO_READn : std_logic;\r
-   signal R_FIFO_RESETn : std_logic;\r
-   signal R_FIFO_RTn : std_logic;\r
-   signal R_FIFO_WRITEn : std_logic;\r
-   signal S_FIFO_D_IN : std_logic_vector (7 downto 0);\r
-   signal S_FIFO_READn : std_logic;\r
-   signal S_FIFO_RESETn : std_logic;\r
-   signal S_FIFO_RTn : std_logic;\r
-   signal S_FIFO_WRITEn : std_logic;\r
-   signal SERIAL_IN : std_logic;\r
-   signal SPC_RDY_IN : std_logic;\r
-   signal SERIAL_OUT : std_logic;\r
-   signal SPC_RDY_OUT : std_logic;\r
-   signal watch_PCI_INTAn : std_logic;\r
-   signal watch_PCI_TRDYn : std_logic;\r
-   signal watch_PCI_STOPn : std_logic;\r
-   signal watch_PCI_SERRn : std_logic;\r
-   signal watch_PCI_PERRn : std_logic;\r
-   signal watch_PCI_REQn : std_logic;\r
-   signal control0       : std_logic_vector(35 downto 0);\r
-   signal data       : std_logic_vector(95 downto 0);\r
-   signal trig0      : std_logic_vector(31 downto 0);\r
-\r
-   component MESS_1_TB\r
-      Port ( DEVSELn : In    std_logic;\r
-               INTAn : In    std_logic;\r
-             KONST_1 : In    std_logic;\r
-             PCI_IDSEL : In    std_logic;\r
-             REG_OUT_XX7 : In    std_logic_vector (7 downto 0);\r
-             TB_DEVSELn : Out   std_logic;\r
-             TB_INTAn : Out   std_logic;\r
-             TB_PCI_IDSEL : Out   std_logic );\r
-   end component;\r
-\r
-   component VEN_REV_ID\r
-      Port (  REV_ID : Out   std_logic_vector (7 downto 0);\r
-              VEN_ID : Out   std_logic_vector (15 downto 0) );\r
-   end component;\r
-\r
-   component INTERRUPT\r
-      Port ( INT_IN_0 : In    std_logic;\r
-             INT_IN_1 : In    std_logic;\r
-             INT_IN_2 : In    std_logic;\r
-             INT_IN_3 : In    std_logic;\r
-             INT_IN_4 : In    std_logic;\r
-             INT_IN_5 : In    std_logic;\r
-             INT_IN_6 : In    std_logic;\r
-             INT_IN_7 : In    std_logic;\r
-             INT_MASKE : In    std_logic_vector (7 downto 0);\r
-             INT_RES : In    std_logic_vector (7 downto 0);\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             READ_XX5_4 : In    std_logic;\r
-               RESET : In    std_logic;\r
-             TAST_RESn : In    std_logic;\r
-             TAST_SETn : In    std_logic;\r
-               TRDYn : In    std_logic;\r
-             INT_REG : Out   std_logic_vector (7 downto 0);\r
-               INTAn : Out   std_logic;\r
-             PCI_INTAn : Out   std_logic );\r
-   end component;\r
-\r
-   component FIFO_CONTROL\r
-      Port ( FIFO_RDn : In    std_logic;\r
-             FLAG_IN_0 : In    std_logic;\r
-             FLAG_IN_4 : In    std_logic;\r
-                HOLD : In    std_logic;\r
-             KONST_1 : In    std_logic;\r
-             PCI_CLOCK : In    std_logic;\r
-             PSC_ENABLE : In    std_logic;\r
-               R_EFn : In    std_logic;\r
-               R_FFn : In    std_logic;\r
-               R_HFn : In    std_logic;\r
-               RESET : In    std_logic;\r
-               S_EFn : In    std_logic;\r
-               S_FFn : In    std_logic;\r
-             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
-               S_HFn : In    std_logic;\r
-             SERIAL_IN : In    std_logic;\r
-             SPC_ENABLE : In    std_logic;\r
-             SPC_RDY_IN : In    std_logic;\r
-             WRITE_XX1_0 : In    std_logic;\r
-             R_ERROR : Out   std_logic;\r
-             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
-             R_FIFO_READn : Out   std_logic;\r
-             R_FIFO_RESETn : Out   std_logic;\r
-             R_FIFO_RETRANSMITn : Out   std_logic;\r
-             R_FIFO_WRITEn : Out   std_logic;\r
-             RESERVE : Out   std_logic;\r
-             S_ERROR : Out   std_logic;\r
-             S_FIFO_READn : Out   std_logic;\r
-             S_FIFO_RESETn : Out   std_logic;\r
-             S_FIFO_RETRANSMITn : Out   std_logic;\r
-             S_FIFO_WRITEn : Out   std_logic;\r
-             SERIAL_OUT : Out   std_logic;\r
-             SPC_RDY_OUT : Out   std_logic;\r
-             SR_ERROR : Out   std_logic;\r
-             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
-   end component;\r
-\r
-   component PCI_TOP\r
-      Port (    FLAG : In    std_logic_vector (7 downto 0);\r
-             INT_REG : In    std_logic_vector (7 downto 0);\r
-             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
-             PCI_CLOCK : In    std_logic;\r
-             PCI_FRAMEn : In    std_logic;\r
-             PCI_IDSEL : In    std_logic;\r
-             PCI_IRDYn : In    std_logic;\r
-             PCI_RSTn : In    std_logic;\r
-             R_FIFO_Q : In    std_logic_vector (7 downto 0);\r
-             REVISON_ID : In    std_logic_vector (7 downto 0);\r
-             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
-              PCI_AD : InOut std_logic_vector (31 downto 0);\r
-             PCI_PAR : InOut std_logic;\r
-              AD_REG : Out   std_logic_vector (31 downto 0);\r
-             DEVSELn : Out   std_logic;\r
-             FIFO_RDn : Out   std_logic;\r
-             PCI_DEVSELn : Out   std_logic;\r
-             PCI_PERRn : Out   std_logic;\r
-             PCI_SERRn : Out   std_logic;\r
-             PCI_STOPn : Out   std_logic;\r
-             PCI_TRDYn : Out   std_logic;\r
-             READ_SEL : Out   std_logic_vector (1 downto 0);\r
-             READ_XX1_0 : Out   std_logic;\r
-             READ_XX3_2 : Out   std_logic;\r
-             READ_XX5_4 : Out   std_logic;\r
-             READ_XX7_6 : Out   std_logic;\r
-             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
-             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
-             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);\r
-               TRDYn : Out   std_logic;\r
-             WRITE_XX1_0 : Out   std_logic;\r
-             WRITE_XX3_2 : Out   std_logic;\r
-             WRITE_XX5_4 : Out   std_logic;\r
-             WRITE_XX7_6 : Out   std_logic );\r
-   end component;\r
-\r
-component dhwk_fifo\r
-        port (\r
-        clk: IN std_logic;\r
-        din: IN std_logic_VECTOR(7 downto 0);\r
-        rd_en: IN std_logic;\r
-        rst: IN std_logic;\r
-        wr_en: IN std_logic;\r
-        almost_empty: OUT std_logic;\r
-        almost_full: OUT std_logic;\r
-        dout: OUT std_logic_VECTOR(7 downto 0);\r
-        empty: OUT std_logic;\r
-        full: OUT std_logic;\r
-        prog_full: OUT std_logic);\r
-end component;\r
-\r
-component icon\r
-port\r
-       (\r
-        control0    :   out std_logic_vector(35 downto 0)\r
-       );\r
-end component;\r
-\r
-  component ila\r
-    port\r
-    (\r
-      control     : in    std_logic_vector(35 downto 0);\r
-      clk         : in    std_logic;\r
-      data        : in    std_logic_vector(95 downto 0);\r
-      trig0       : in    std_logic_vector(31 downto 0)\r
-    );\r
-  end component;\r
-\r
-\r
-begin\r
-       watch_PCI_REQn <= '1';\r
-       SERIAL_IN <= SERIAL_OUT;\r
-       SPC_RDY_IN <= SPC_RDY_OUT;\r
-       LED_2 <= not PCI_RSTn;\r
-       LED_3 <= PCI_IDSEL;\r
-       LED_4 <= not PCI_FRAMEn;\r
-       LED_5 <= not watch_PCI_INTAn;\r
-       PCI_INTAn <= watch_PCI_INTAn;\r
-       trig0(31 downto 0) <= (\r
-               0 => watch_PCI_INTAn,\r
-               1 => R_FIFO_READn,\r
-               2 => R_FIFO_WRITEn,\r
-               3 => S_FIFO_READn,\r
-               4 => S_FIFO_WRITEn, \r
-               5 => PCI_RSTn,\r
-               16 => PCI_AD(0),\r
-               17 => PCI_AD(1),\r
-               18 => PCI_AD(2),\r
-               19 => PCI_AD(3),\r
-               20 => PCI_AD(4),\r
-               21 => PCI_AD(5),\r
-               22 => PCI_AD(6),\r
-               23 => PCI_AD(7),\r
-               27 => PCI_FRAMEn,\r
-               28 => PCI_CBEn(0),\r
-               29 => PCI_CBEn(1),\r
-               30 => PCI_CBEn(2),\r
-               31 => PCI_CBEn(3),\r
-               others => '0');\r
-\r
-       data(0) <= watch_PCI_INTAn;\r
-       data(1) <= R_EFn;\r
-       data(2) <= R_HFn;\r
-       data(3) <= R_FFn;\r
-       data(4) <= R_FIFO_READn;\r
-       data(5) <= R_FIFO_RESETn;\r
-       data(6) <= R_FIFO_RTn;\r
-       data(7) <= R_FIFO_WRITEn;\r
-       data(8) <= S_EFn;\r
-       data(9) <= S_HFn;\r
-       data(10) <= S_FFn;\r
-       data(11) <= S_FIFO_READn;\r
-       data(12) <= S_FIFO_RESETn;\r
-       data(13) <= S_FIFO_RTn;\r
-       data(14) <= S_FIFO_WRITEn;\r
-       data(15) <= SERIAL_IN;\r
-       data(16) <= SPC_RDY_IN;\r
-       data(17) <= SERIAL_OUT;\r
-       data(18) <= SPC_RDY_OUT;\r
-       data(26 downto 19) <= S_FIFO_Q_OUT;\r
-       data(34 downto 27) <= R_FIFO_Q_OUT;\r
-       data(66 downto 35) <= PCI_AD(31 downto 0);\r
-       data(70 downto 67) <= PCI_CBEn(3 downto 0);\r
-       data(71) <= PCI_FRAMEn;\r
-       data(72) <= PCI_IDSEL;\r
-       PCI_TRDYn <= watch_PCI_TRDYn;\r
-       data(73) <= watch_PCI_TRDYn;\r
-       data(74) <= PCI_IRDYn;\r
-       PCI_STOPn <= watch_PCI_STOPn;\r
-       data(75) <= watch_PCI_STOPn;\r
-       PCI_SERRn <= watch_PCI_SERRn;\r
-       data(76) <= watch_PCI_SERRn;\r
-       PCI_PERRn <= watch_PCI_PERRn;\r
-       data(77) <= watch_PCI_PERRn;\r
-       PCI_REQn <= watch_PCI_REQn;\r
-       data(78) <= watch_PCI_REQn;\r
-       data(79) <= PCI_GNTn;\r
-\r
-   I19 : MESS_1_TB\r
-      Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
-                 PCI_IDSEL=>PCI_IDSEL,\r
-                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
-                 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,\r
-                 TB_PCI_IDSEL=>TB_IDSEL );\r
-   I18 : VEN_REV_ID\r
-      Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
-                 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );\r
-   I16 : INTERRUPT\r
-      Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),\r
-                 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,\r
-                 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,\r
-                 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
-                 INT_RES(7 downto 0)=>AD_REG(7 downto 0),\r
-                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
-                 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
-                 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
-                 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
-                 INTAn=>INTAn, PCI_INTAn=>watch_PCI_INTAn);\r
-   I14 : FIFO_CONTROL\r
-      Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
-                 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
-                 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),\r
-                 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,\r
-                 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,\r
-                 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
-                 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,\r
-                 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,\r
-                 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
-                 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
-                 R_FIFO_READn=>R_FIFO_READn,\r
-                 R_FIFO_RESETn=>R_FIFO_RESETn,\r
-                 R_FIFO_RETRANSMITn=>R_FIFO_RTn,\r
-                 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,\r
-                 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,\r
-                 S_FIFO_RESETn=>S_FIFO_RESETn,\r
-                 S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
-                 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
-                 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
-                 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
-   I1 : PCI_TOP\r
-      Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
-                 INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
-                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
-                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
-                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
-                 PCI_RSTn=>PCI_RSTn,\r
-                 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),\r
-                 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
-                 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
-                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
-                 PCI_PAR=>PCI_PAR,\r
-                 AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
-                 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
-                 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>watch_PCI_PERRn,\r
-                 PCI_SERRn=>watch_PCI_SERRn, PCI_STOPn=>watch_PCI_STOPn,\r
-                 PCI_TRDYn=>watch_PCI_TRDYn,\r
-                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
-                 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
-                 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,\r
-                 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),\r
-                 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
-                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
-                 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,\r
-                 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
-                 WRITE_XX7_6=>WRITE_XX7_6 );\r
-\r
-receive_fifo : dhwk_fifo\r
-                port map (\r
-                        clk => PCI_CLOCK,\r
-                        din => R_FIFO_D_IN,\r
-                        rd_en => not R_FIFO_READn,\r
-                        rst => not R_FIFO_RESETn,\r
-                        wr_en => not R_FIFO_WRITEn,\r
-                        dout => R_FIFO_Q_OUT,\r
-                        empty => R_EFn,\r
-                        full => R_FFn,\r
-                        prog_full => R_HFn);\r
-\r
-send_fifo : dhwk_fifo\r
-                port map (\r
-                        clk => PCI_CLOCK,\r
-                        din => S_FIFO_D_IN,\r
-                        rd_en => not S_FIFO_READn,\r
-                        rst => not S_FIFO_RESETn,\r
-                        wr_en => not S_FIFO_WRITEn,\r
-                        dout => S_FIFO_Q_OUT,\r
-                        empty => S_EFn,\r
-                        full => S_FFn,\r
-                        prog_full => S_HFn);\r
-\r
-  i_icon : icon\r
-      port map\r
-          (\r
-               control0    => control0\r
-         );\r
-\r
-  i_ila : ila\r
-    port map\r
-    (\r
-      control   => control0,\r
-      clk       => PCI_CLOCK,\r
-      data      => data,\r
-      trig0     => trig0\r
-    );\r
-end SCHEMATIC;\r
+-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007
+
+
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity dhwk is
+      Port ( KONST_1 : In    std_logic;
+             PCI_CBEn : In    std_logic_vector (3 downto 0);
+             PCI_CLOCK : In    std_logic;
+             PCI_FRAMEn : In    std_logic;
+             PCI_IDSEL : In    std_logic;
+             PCI_IRDYn : In    std_logic;
+             PCI_RSTn : In    std_logic;
+--             SERIAL_IN : In    std_logic;
+--             SPC_RDY_IN : In    std_logic;
+             TAST_RESn : In    std_logic;
+             TAST_SETn : In    std_logic;
+             LED_2 : out    std_logic;
+             LED_3 : out    std_logic;
+             LED_4 : out    std_logic;
+             LED_5 : out    std_logic;
+              PCI_AD : InOut std_logic_vector (31 downto 0);
+             PCI_PAR : InOut std_logic;
+             PCI_DEVSELn : Out   std_logic;
+             PCI_INTAn : Out   std_logic;
+             PCI_PERRn : Out   std_logic;
+             PCI_SERRn : Out   std_logic;
+             PCI_STOPn : Out   std_logic;
+             PCI_TRDYn : Out   std_logic;
+            PCI_REQn : Out std_logic;
+            PCI_GNTn : In std_logic;
+--             SERIAL_OUT : Out   std_logic;
+--             SPC_RDY_OUT : Out   std_logic;
+             TB_IDSEL : Out   std_logic;
+             TB_nDEVSEL : Out   std_logic;
+             TB_nINTA : Out   std_logic );
+end dhwk;
+
+architecture SCHEMATIC of dhwk is
+
+   SIGNAL gnd : std_logic := '0';
+   SIGNAL vcc : std_logic := '1';
+
+   signal READ_XX7_6 : std_logic;
+   signal  RESERVE : std_logic;
+   signal SR_ERROR : std_logic;
+   signal  R_ERROR : std_logic;
+   signal  S_ERROR : std_logic;
+   signal WRITE_XX3_2 : std_logic;
+   signal WRITE_XX5_4 : std_logic;
+   signal WRITE_XX7_6 : std_logic;
+   signal READ_XX1_0 : std_logic;
+   signal READ_XX3_2 : std_logic;
+   signal    INTAn : std_logic;
+   signal    TRDYn : std_logic;
+   signal READ_XX5_4 : std_logic;
+   signal  DEVSELn : std_logic;
+   signal FIFO_RDn : std_logic;
+   signal WRITE_XX1_0 : std_logic;
+   signal REG_OUT_XX6 : std_logic_vector (7 downto 0);
+   signal SYNC_FLAG : std_logic_vector (7 downto 0);
+   signal  INT_REG : std_logic_vector (7 downto 0);
+   signal REVISON_ID : std_logic_vector (7 downto 0);
+   signal VENDOR_ID : std_logic_vector (15 downto 0);
+   signal READ_SEL : std_logic_vector (1 downto 0);
+   signal   AD_REG : std_logic_vector (31 downto 0);
+   signal REG_OUT_XX7 : std_logic_vector (7 downto 0);
+   signal R_EFn : std_logic;
+   signal R_FFn : std_logic;
+   signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);
+   signal R_HFn : std_logic;
+   signal S_EFn : std_logic;
+   signal S_FFn : std_logic;
+   signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);
+   signal S_HFn : std_logic;
+   signal R_FIFO_D_IN : std_logic_vector (7 downto 0);
+   signal R_FIFO_READn : std_logic;
+   signal R_FIFO_RESETn : std_logic;
+   signal R_FIFO_RTn : std_logic;
+   signal R_FIFO_WRITEn : std_logic;
+   signal S_FIFO_D_IN : std_logic_vector (7 downto 0);
+   signal S_FIFO_READn : std_logic;
+   signal S_FIFO_RESETn : std_logic;
+   signal S_FIFO_RTn : std_logic;
+   signal S_FIFO_WRITEn : std_logic;
+   signal SERIAL_IN : std_logic;
+   signal SPC_RDY_IN : std_logic;
+   signal SERIAL_OUT : std_logic;
+   signal SPC_RDY_OUT : std_logic;
+   signal watch_PCI_INTAn : std_logic;
+   signal watch_PCI_TRDYn : std_logic;
+   signal watch_PCI_STOPn : std_logic;
+   signal watch_PCI_SERRn : std_logic;
+   signal watch_PCI_PERRn : std_logic;
+   signal watch_PCI_REQn : std_logic;
+   signal control0       : std_logic_vector(35 downto 0);
+   signal data       : std_logic_vector(95 downto 0);
+   signal trig0      : std_logic_vector(31 downto 0);
+
+   component MESS_1_TB
+      Port ( DEVSELn : In    std_logic;
+               INTAn : In    std_logic;
+             KONST_1 : In    std_logic;
+             PCI_IDSEL : In    std_logic;
+             REG_OUT_XX7 : In    std_logic_vector (7 downto 0);
+             TB_DEVSELn : Out   std_logic;
+             TB_INTAn : Out   std_logic;
+             TB_PCI_IDSEL : Out   std_logic );
+   end component;
+
+   component VEN_REV_ID
+      Port (  REV_ID : Out   std_logic_vector (7 downto 0);
+              VEN_ID : Out   std_logic_vector (15 downto 0) );
+   end component;
+
+   component INTERRUPT
+      Port ( INT_IN_0 : In    std_logic;
+             INT_IN_1 : In    std_logic;
+             INT_IN_2 : In    std_logic;
+             INT_IN_3 : In    std_logic;
+             INT_IN_4 : In    std_logic;
+             INT_IN_5 : In    std_logic;
+             INT_IN_6 : In    std_logic;
+             INT_IN_7 : In    std_logic;
+             INT_MASKE : In    std_logic_vector (7 downto 0);
+             INT_RES : In    std_logic_vector (7 downto 0);
+             PCI_CLOCK : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             READ_XX5_4 : In    std_logic;
+               RESET : In    std_logic;
+             TAST_RESn : In    std_logic;
+             TAST_SETn : In    std_logic;
+               TRDYn : In    std_logic;
+             INT_REG : Out   std_logic_vector (7 downto 0);
+               INTAn : Out   std_logic;
+             PCI_INTAn : Out   std_logic );
+   end component;
+
+   component FIFO_CONTROL
+      Port ( FIFO_RDn : In    std_logic;
+             FLAG_IN_0 : In    std_logic;
+             FLAG_IN_4 : In    std_logic;
+                HOLD : In    std_logic;
+             KONST_1 : In    std_logic;
+             PCI_CLOCK : In    std_logic;
+             PSC_ENABLE : In    std_logic;
+               R_EFn : In    std_logic;
+               R_FFn : In    std_logic;
+               R_HFn : In    std_logic;
+               RESET : In    std_logic;
+               S_EFn : In    std_logic;
+               S_FFn : In    std_logic;
+             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);
+               S_HFn : In    std_logic;
+             SERIAL_IN : In    std_logic;
+             SPC_ENABLE : In    std_logic;
+             SPC_RDY_IN : In    std_logic;
+             WRITE_XX1_0 : In    std_logic;
+             R_ERROR : Out   std_logic;
+             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);
+             R_FIFO_READn : Out   std_logic;
+             R_FIFO_RESETn : Out   std_logic;
+             R_FIFO_RETRANSMITn : Out   std_logic;
+             R_FIFO_WRITEn : Out   std_logic;
+             RESERVE : Out   std_logic;
+             S_ERROR : Out   std_logic;
+             S_FIFO_READn : Out   std_logic;
+             S_FIFO_RESETn : Out   std_logic;
+             S_FIFO_RETRANSMITn : Out   std_logic;
+             S_FIFO_WRITEn : Out   std_logic;
+             SERIAL_OUT : Out   std_logic;
+             SPC_RDY_OUT : Out   std_logic;
+             SR_ERROR : Out   std_logic;
+             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );
+   end component;
+
+   component PCI_TOP
+      Port (    FLAG : In    std_logic_vector (7 downto 0);
+             INT_REG : In    std_logic_vector (7 downto 0);
+             PCI_CBEn : In    std_logic_vector (3 downto 0);
+             PCI_CLOCK : In    std_logic;
+             PCI_FRAMEn : In    std_logic;
+             PCI_IDSEL : In    std_logic;
+             PCI_IRDYn : In    std_logic;
+             PCI_RSTn : In    std_logic;
+             R_FIFO_Q : In    std_logic_vector (7 downto 0);
+             REVISON_ID : In    std_logic_vector (7 downto 0);
+             VENDOR_ID : In    std_logic_vector (15 downto 0);
+              PCI_AD : InOut std_logic_vector (31 downto 0);
+             PCI_PAR : InOut std_logic;
+              AD_REG : Out   std_logic_vector (31 downto 0);
+             DEVSELn : Out   std_logic;
+             FIFO_RDn : Out   std_logic;
+             PCI_DEVSELn : Out   std_logic;
+             PCI_PERRn : Out   std_logic;
+             PCI_SERRn : Out   std_logic;
+             PCI_STOPn : Out   std_logic;
+             PCI_TRDYn : Out   std_logic;
+             READ_SEL : Out   std_logic_vector (1 downto 0);
+             READ_XX1_0 : Out   std_logic;
+             READ_XX3_2 : Out   std_logic;
+             READ_XX5_4 : Out   std_logic;
+             READ_XX7_6 : Out   std_logic;
+             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);
+             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);
+             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);
+               TRDYn : Out   std_logic;
+             WRITE_XX1_0 : Out   std_logic;
+             WRITE_XX3_2 : Out   std_logic;
+             WRITE_XX5_4 : Out   std_logic;
+             WRITE_XX7_6 : Out   std_logic );
+   end component;
+
+component dhwk_fifo
+        port (
+        clk: IN std_logic;
+        din: IN std_logic_VECTOR(7 downto 0);
+        rd_en: IN std_logic;
+        rst: IN std_logic;
+        wr_en: IN std_logic;
+        almost_empty: OUT std_logic;
+        almost_full: OUT std_logic;
+        dout: OUT std_logic_VECTOR(7 downto 0);
+        empty: OUT std_logic;
+        full: OUT std_logic;
+        prog_full: OUT std_logic);
+end component;
+
+component icon
+port
+       (
+        control0    :   out std_logic_vector(35 downto 0)
+       );
+end component;
+
+  component ila
+    port
+    (
+      control     : in    std_logic_vector(35 downto 0);
+      clk         : in    std_logic;
+      data        : in    std_logic_vector(95 downto 0);
+      trig0       : in    std_logic_vector(31 downto 0)
+    );
+  end component;
+
+
+begin
+       watch_PCI_REQn <= '1';
+       SERIAL_IN <= SERIAL_OUT;
+       SPC_RDY_IN <= SPC_RDY_OUT;
+       LED_2 <= not PCI_RSTn;
+       LED_3 <= PCI_IDSEL;
+       LED_4 <= not PCI_FRAMEn;
+       LED_5 <= not watch_PCI_INTAn;
+       PCI_INTAn <= watch_PCI_INTAn;
+       trig0(31 downto 0) <= (
+               0 => watch_PCI_INTAn,
+               1 => R_FIFO_READn,
+               2 => R_FIFO_WRITEn,
+               3 => S_FIFO_READn,
+               4 => S_FIFO_WRITEn, 
+               5 => PCI_RSTn,
+               16 => PCI_AD(0),
+               17 => PCI_AD(1),
+               18 => PCI_AD(2),
+               19 => PCI_AD(3),
+               20 => PCI_AD(4),
+               21 => PCI_AD(5),
+               22 => PCI_AD(6),
+               23 => PCI_AD(7),
+               27 => PCI_FRAMEn,
+               28 => PCI_CBEn(0),
+               29 => PCI_CBEn(1),
+               30 => PCI_CBEn(2),
+               31 => PCI_CBEn(3),
+               others => '0');
+
+       data(0) <= watch_PCI_INTAn;
+       data(1) <= R_EFn;
+       data(2) <= R_HFn;
+       data(3) <= R_FFn;
+       data(4) <= R_FIFO_READn;
+       data(5) <= R_FIFO_RESETn;
+       data(6) <= R_FIFO_RTn;
+       data(7) <= R_FIFO_WRITEn;
+       data(8) <= S_EFn;
+       data(9) <= S_HFn;
+       data(10) <= S_FFn;
+       data(11) <= S_FIFO_READn;
+       data(12) <= S_FIFO_RESETn;
+       data(13) <= S_FIFO_RTn;
+       data(14) <= S_FIFO_WRITEn;
+       data(15) <= SERIAL_IN;
+       data(16) <= SPC_RDY_IN;
+       data(17) <= SERIAL_OUT;
+       data(18) <= SPC_RDY_OUT;
+       data(26 downto 19) <= S_FIFO_Q_OUT;
+       data(34 downto 27) <= R_FIFO_Q_OUT;
+       data(66 downto 35) <= PCI_AD(31 downto 0);
+       data(70 downto 67) <= PCI_CBEn(3 downto 0);
+       data(71) <= PCI_FRAMEn;
+       data(72) <= PCI_IDSEL;
+       PCI_TRDYn <= watch_PCI_TRDYn;
+       data(73) <= watch_PCI_TRDYn;
+       data(74) <= PCI_IRDYn;
+       PCI_STOPn <= watch_PCI_STOPn;
+       data(75) <= watch_PCI_STOPn;
+       PCI_SERRn <= watch_PCI_SERRn;
+       data(76) <= watch_PCI_SERRn;
+       PCI_PERRn <= watch_PCI_PERRn;
+       data(77) <= watch_PCI_PERRn;
+       PCI_REQn <= watch_PCI_REQn;
+       data(78) <= watch_PCI_REQn;
+       data(79) <= PCI_GNTn;
+
+   I19 : MESS_1_TB
+      Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
+                 PCI_IDSEL=>PCI_IDSEL,
+                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
+                 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,
+                 TB_PCI_IDSEL=>TB_IDSEL );
+   I18 : VEN_REV_ID
+      Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),
+                 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );
+   I16 : INTERRUPT
+      Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),
+                 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,
+                 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,
+                 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),
+                 INT_RES(7 downto 0)=>AD_REG(7 downto 0),
+                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
+                 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
+                 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
+                 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
+                 INTAn=>INTAn, PCI_INTAn=>watch_PCI_INTAn);
+   I14 : FIFO_CONTROL
+      Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
+                 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
+                 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),
+                 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,
+                 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,
+                 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
+                 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,
+                 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,
+                 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
+                 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
+                 R_FIFO_READn=>R_FIFO_READn,
+                 R_FIFO_RESETn=>R_FIFO_RESETn,
+                 R_FIFO_RETRANSMITn=>R_FIFO_RTn,
+                 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,
+                 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,
+                 S_FIFO_RESETn=>S_FIFO_RESETn,
+                 S_FIFO_RETRANSMITn=>S_FIFO_RTn,
+                 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
+                 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
+                 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
+   I1 : PCI_TOP
+      Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),
+                 INT_REG(7 downto 0)=>INT_REG(7 downto 0),
+                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
+                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
+                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
+                 PCI_RSTn=>PCI_RSTn,
+                 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),
+                 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
+                 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
+                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
+                 PCI_PAR=>PCI_PAR,
+                 AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+                 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
+                 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>watch_PCI_PERRn,
+                 PCI_SERRn=>watch_PCI_SERRn, PCI_STOPn=>watch_PCI_STOPn,
+                 PCI_TRDYn=>watch_PCI_TRDYn,
+                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
+                 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
+                 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,
+                 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),
+                 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
+                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
+                 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,
+                 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
+                 WRITE_XX7_6=>WRITE_XX7_6 );
+
+receive_fifo : dhwk_fifo
+                port map (
+                        clk => PCI_CLOCK,
+                        din => R_FIFO_D_IN,
+                        rd_en => not R_FIFO_READn,
+                        rst => not R_FIFO_RESETn,
+                        wr_en => not R_FIFO_WRITEn,
+                        dout => R_FIFO_Q_OUT,
+                        empty => R_EFn,
+                        full => R_FFn,
+                        prog_full => R_HFn);
+
+send_fifo : dhwk_fifo
+                port map (
+                        clk => PCI_CLOCK,
+                        din => S_FIFO_D_IN,
+                        rd_en => not S_FIFO_READn,
+                        rst => not S_FIFO_RESETn,
+                        wr_en => not S_FIFO_WRITEn,
+                        dout => S_FIFO_Q_OUT,
+                        empty => S_EFn,
+                        full => S_FFn,
+                        prog_full => S_HFn);
+
+  i_icon : icon
+      port map
+          (
+               control0    => control0
+         );
+
+  i_ila : ila
+    port map
+    (
+      control   => control0,
+      clk       => PCI_CLOCK,
+      data      => data,
+      trig0     => trig0
+    );
+end SCHEMATIC;

diff --git a/dhwk/source/user_io.vhd b/dhwk/source/user_io.vhd
index 72070cdaa676445d50825ebe061232fc94e94542..d7616be093413e725bf688eab5878c8e28f8ce5c 100644 (file)
--- a/dhwk/source/user_io.vhd
+++ b/dhwk/source/user_io.vhd
@@ -1,129 +1,129 @@
--- VHDL model created from schematic user_io.sch -- Jan 09 09:34:12 2007\r
-\r
-\r
-\r
-LIBRARY ieee;\r
-\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-\r
-entity USER_IO is\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             ADDR_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-                FLAG : In    std_logic_vector (7 downto 0);\r
-             INT_REG : In    std_logic_vector (7 downto 0);\r
-             IO_WR_COM : In    std_logic;\r
-             IRDY_REGn : In    std_logic;\r
-             PCI_CLK : In    std_logic;\r
-             R_FIFO_Q : In    std_logic_vector (7 downto 0);\r
-             READ_SEL : In    std_logic_vector (1 downto 0);\r
-               TRDYn : In    std_logic;\r
-             READ_XX1_0 : Out   std_logic;\r
-             READ_XX3_2 : Out   std_logic;\r
-             READ_XX5_4 : Out   std_logic;\r
-             READ_XX7_6 : Out   std_logic;\r
-             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
-             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
-             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);\r
-             USER_DATA_OUT : Out   std_logic_vector (31 downto 0);\r
-             WRITE_XX1_0 : Out   std_logic;\r
-             WRITE_XX3_2 : Out   std_logic;\r
-             WRITE_XX5_4 : Out   std_logic;\r
-             WRITE_XX7_6 : Out   std_logic );\r
-end USER_IO;\r
-\r
-architecture SCHEMATIC of USER_IO is\r
-\r
-   SIGNAL gnd : std_logic := '0';\r
-   SIGNAL vcc : std_logic := '1';\r
-\r
-   signal WRITE_XX1_0_DUMMY : std_logic;\r
-   signal WRITE_XX7_6_DUMMY : std_logic;\r
-   signal REG_OUT_XX7_DUMMY : std_logic_vector (7 downto 0);\r
-   signal REG_OUT_XX6_DUMMY : std_logic_vector (7 downto 0);\r
-   signal REG_OUT_XX0_DUMMY : std_logic_vector (7 downto 0);\r
-\r
-   component IO_WR_SEL\r
-      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-             IO_WR_COM : In    std_logic;\r
-             IRDY_REGn : In    std_logic;\r
-               TRDYn : In    std_logic;\r
-             WRITE_XX1_0 : Out   std_logic;\r
-             WRITE_XX3_2 : Out   std_logic;\r
-             WRITE_XX5_4 : Out   std_logic;\r
-             WRITE_XX7_6 : Out   std_logic );\r
-   end component;\r
-\r
-   component DATA_MUX\r
-      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);\r
-             CBE_REGn : In    std_logic_vector (3 downto 0);\r
-             MUX_IN_XX0 : In    std_logic_vector (7 downto 0);\r
-             MUX_IN_XX1 : In    std_logic_vector (7 downto 0);\r
-             MUX_IN_XX2 : In    std_logic_vector (7 downto 0);\r
-             MUX_IN_XX3 : In    std_logic_vector (7 downto 0);\r
-             MUX_IN_XX4 : In    std_logic_vector (7 downto 0);\r
-             MUX_IN_XX5 : In    std_logic_vector (7 downto 0);\r
-             MUX_IN_XX6 : In    std_logic_vector (7 downto 0);\r
-             MUX_IN_XX7 : In    std_logic_vector (7 downto 0);\r
-             READ_SEL : In    std_logic_vector (1 downto 0);\r
-             MUX_OUT : Out   std_logic_vector (31 downto 0);\r
-             READ_XX1_0 : Out   std_logic;\r
-             READ_XX3_2 : Out   std_logic;\r
-             READ_XX5_4 : Out   std_logic;\r
-             READ_XX7_6 : Out   std_logic );\r
-   end component;\r
-\r
-   component REG_IO\r
-      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
-             PCI_CLOCK : In    std_logic;\r
-               RESET : In    std_logic;\r
-             WRITE_XX1_0 : In    std_logic;\r
-             WRITE_XX7_6 : In    std_logic;\r
-             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
-             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
-             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0) );\r
-   end component;\r
-\r
-begin\r
-\r
-   REG_OUT_XX0 <= REG_OUT_XX0_DUMMY;\r
-   REG_OUT_XX6 <= REG_OUT_XX6_DUMMY;\r
-   REG_OUT_XX7 <= REG_OUT_XX7_DUMMY;\r
-   WRITE_XX7_6 <= WRITE_XX7_6_DUMMY;\r
-   WRITE_XX1_0 <= WRITE_XX1_0_DUMMY;\r
-\r
-   I4 : IO_WR_SEL\r
-      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
-                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
-                 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,\r
-                 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0_DUMMY,\r
-                 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
-                 WRITE_XX7_6=>WRITE_XX7_6_DUMMY );\r
-   I2 : DATA_MUX\r
-      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
-                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
-                 MUX_IN_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),\r
-                 MUX_IN_XX1(7 downto 0)=>FLAG(7 downto 0),\r
-                 MUX_IN_XX2(7 downto 0)=>R_FIFO_Q(7 downto 0),\r
-                 MUX_IN_XX3(7 downto 0)=>FLAG(7 downto 0),\r
-                 MUX_IN_XX4(7 downto 0)=>INT_REG(7 downto 0),\r
-                 MUX_IN_XX5(7 downto 0)=>FLAG(7 downto 0),\r
-                 MUX_IN_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),\r
-                 MUX_IN_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0),\r
-                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
-                 MUX_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
-                 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
-                 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6 );\r
-   I1 : REG_IO\r
-      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
-                 PCI_CLOCK=>PCI_CLK, RESET=>REG_OUT_XX7_DUMMY(0),\r
-                 WRITE_XX1_0=>WRITE_XX1_0_DUMMY,\r
-                 WRITE_XX7_6=>WRITE_XX7_6_DUMMY,\r
-                 REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),\r
-                 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),\r
-                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0) );\r
-\r
-end SCHEMATIC;\r
+-- VHDL model created from schematic user_io.sch -- Jan 09 09:34:12 2007
+
+
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity USER_IO is
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             ADDR_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+                FLAG : In    std_logic_vector (7 downto 0);
+             INT_REG : In    std_logic_vector (7 downto 0);
+             IO_WR_COM : In    std_logic;
+             IRDY_REGn : In    std_logic;
+             PCI_CLK : In    std_logic;
+             R_FIFO_Q : In    std_logic_vector (7 downto 0);
+             READ_SEL : In    std_logic_vector (1 downto 0);
+               TRDYn : In    std_logic;
+             READ_XX1_0 : Out   std_logic;
+             READ_XX3_2 : Out   std_logic;
+             READ_XX5_4 : Out   std_logic;
+             READ_XX7_6 : Out   std_logic;
+             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);
+             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);
+             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);
+             USER_DATA_OUT : Out   std_logic_vector (31 downto 0);
+             WRITE_XX1_0 : Out   std_logic;
+             WRITE_XX3_2 : Out   std_logic;
+             WRITE_XX5_4 : Out   std_logic;
+             WRITE_XX7_6 : Out   std_logic );
+end USER_IO;
+
+architecture SCHEMATIC of USER_IO is
+
+   SIGNAL gnd : std_logic := '0';
+   SIGNAL vcc : std_logic := '1';
+
+   signal WRITE_XX1_0_DUMMY : std_logic;
+   signal WRITE_XX7_6_DUMMY : std_logic;
+   signal REG_OUT_XX7_DUMMY : std_logic_vector (7 downto 0);
+   signal REG_OUT_XX6_DUMMY : std_logic_vector (7 downto 0);
+   signal REG_OUT_XX0_DUMMY : std_logic_vector (7 downto 0);
+
+   component IO_WR_SEL
+      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+             IO_WR_COM : In    std_logic;
+             IRDY_REGn : In    std_logic;
+               TRDYn : In    std_logic;
+             WRITE_XX1_0 : Out   std_logic;
+             WRITE_XX3_2 : Out   std_logic;
+             WRITE_XX5_4 : Out   std_logic;
+             WRITE_XX7_6 : Out   std_logic );
+   end component;
+
+   component DATA_MUX
+      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);
+             CBE_REGn : In    std_logic_vector (3 downto 0);
+             MUX_IN_XX0 : In    std_logic_vector (7 downto 0);
+             MUX_IN_XX1 : In    std_logic_vector (7 downto 0);
+             MUX_IN_XX2 : In    std_logic_vector (7 downto 0);
+             MUX_IN_XX3 : In    std_logic_vector (7 downto 0);
+             MUX_IN_XX4 : In    std_logic_vector (7 downto 0);
+             MUX_IN_XX5 : In    std_logic_vector (7 downto 0);
+             MUX_IN_XX6 : In    std_logic_vector (7 downto 0);
+             MUX_IN_XX7 : In    std_logic_vector (7 downto 0);
+             READ_SEL : In    std_logic_vector (1 downto 0);
+             MUX_OUT : Out   std_logic_vector (31 downto 0);
+             READ_XX1_0 : Out   std_logic;
+             READ_XX3_2 : Out   std_logic;
+             READ_XX5_4 : Out   std_logic;
+             READ_XX7_6 : Out   std_logic );
+   end component;
+
+   component REG_IO
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);
+             PCI_CLOCK : In    std_logic;
+               RESET : In    std_logic;
+             WRITE_XX1_0 : In    std_logic;
+             WRITE_XX7_6 : In    std_logic;
+             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);
+             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);
+             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0) );
+   end component;
+
+begin
+
+   REG_OUT_XX0 <= REG_OUT_XX0_DUMMY;
+   REG_OUT_XX6 <= REG_OUT_XX6_DUMMY;
+   REG_OUT_XX7 <= REG_OUT_XX7_DUMMY;
+   WRITE_XX7_6 <= WRITE_XX7_6_DUMMY;
+   WRITE_XX1_0 <= WRITE_XX1_0_DUMMY;
+
+   I4 : IO_WR_SEL
+      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+                 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
+                 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
+                 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
+                 WRITE_XX7_6=>WRITE_XX7_6_DUMMY );
+   I2 : DATA_MUX
+      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
+                 MUX_IN_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
+                 MUX_IN_XX1(7 downto 0)=>FLAG(7 downto 0),
+                 MUX_IN_XX2(7 downto 0)=>R_FIFO_Q(7 downto 0),
+                 MUX_IN_XX3(7 downto 0)=>FLAG(7 downto 0),
+                 MUX_IN_XX4(7 downto 0)=>INT_REG(7 downto 0),
+                 MUX_IN_XX5(7 downto 0)=>FLAG(7 downto 0),
+                 MUX_IN_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
+                 MUX_IN_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0),
+                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
+                 MUX_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
+                 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
+                 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6 );
+   I1 : REG_IO
+      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
+                 PCI_CLOCK=>PCI_CLK, RESET=>REG_OUT_XX7_DUMMY(0),
+                 WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
+                 WRITE_XX7_6=>WRITE_XX7_6_DUMMY,
+                 REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
+                 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
+                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0) );
+
+end SCHEMATIC;

diff --git a/dhwk/source/ven_rev_id.vhd b/dhwk/source/ven_rev_id.vhd
index e57fa32862d6cffbab5504bb01b2a39441fadb79..669264e0f578689474ed946650d28184c1b54a09 100644 (file)
--- a/dhwk/source/ven_rev_id.vhd
+++ b/dhwk/source/ven_rev_id.vhd
@@ -1,24 +1,24 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: VEN_REV_ID.VHD\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-\r
-entity VEN_REV_ID is\r
-       port\r
-       (\r
-       VEN_ID  :out    std_logic_vector(15 downto 0);\r
-       REV_ID  :out    std_logic_vector( 7 downto 0)\r
-       );\r
-end entity VEN_REV_ID;\r
-\r
-architecture VEN_REV_ID_DESIGN of VEN_REV_ID is\r
-\r
-begin\r
-\r
-       VEN_ID  <= X"2222";\r
-       REV_ID  <= X"01";\r
-\r
-end architecture VEN_REV_ID_DESIGN;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VEN_REV_ID.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity VEN_REV_ID is
+       port
+       (
+       VEN_ID  :out    std_logic_vector(15 downto 0);
+       REV_ID  :out    std_logic_vector( 7 downto 0)
+       );
+end entity VEN_REV_ID;
+
+architecture VEN_REV_ID_DESIGN of VEN_REV_ID is
+
+begin
+
+       VEN_ID  <= X"2222";
+       REV_ID  <= X"01";
+
+end architecture VEN_REV_ID_DESIGN;

diff --git a/dhwk/source/verg_8.vhd b/dhwk/source/verg_8.vhd
index 294aac5552cc2196c3fcb743558539d87860d502..618a0cca22168df6ac8babd88cfe132c3ac80a55 100644 (file)
--- a/dhwk/source/verg_8.vhd
+++ b/dhwk/source/verg_8.vhd
@@ -1,28 +1,28 @@
--- J.STELZNER\r
--- INFORMATIK-3 LABOR\r
--- 23.08.2006\r
--- File: VERG_8.VHD\r
-\r
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-\r
-entity VERG_8 is\r
-       port\r
-       (\r
-       GLEICH                  :in             std_logic_vector(7 downto 0);\r
-       GLEICH_OUT      :out    std_logic\r
-       );\r
-\r
-end entity VERG_8 ;\r
-\r
-architecture VERG_8_DESIGN of VERG_8 is\r
- \r
-\r
-begin\r
-\r
---     GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte\r
-\r
---     GLEICH_OUT      <=      '1'     when    GLEICH(7 downto 0)      =       "11111111"      else    '0';    \r
-               GLEICH_OUT      <=      '1'     when    GLEICH(7 downto 1)      =       "1111111"               else    '0'; \r
- \r
-end architecture VERG_8_DESIGN ;\r
+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VERG_8.VHD
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity VERG_8 is
+       port
+       (
+       GLEICH                  :in             std_logic_vector(7 downto 0);
+       GLEICH_OUT      :out    std_logic
+       );
+
+end entity VERG_8 ;
+
+architecture VERG_8_DESIGN of VERG_8 is
+ 
+
+begin
+
+--     GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte
+
+--     GLEICH_OUT      <=      '1'     when    GLEICH(7 downto 0)      =       "11111111"      else    '0';    
+               GLEICH_OUT      <=      '1'     when    GLEICH(7 downto 1)      =       "1111111"               else    '0'; 
+ 
+end architecture VERG_8_DESIGN ;

diff --git a/dhwk/source/vergleich.vhd b/dhwk/source/vergleich.vhd
index 66a9709b6248c2262f11d1b74a7e7a8f2d858cce..27460a90376dc7fd4b4f8ee313ca08d8b12399ab 100644 (file)
--- a/dhwk/source/vergleich.vhd
+++ b/dhwk/source/vergleich.vhd
@@ -1,71 +1,71 @@
--- VHDL model created from schematic vergleich.sch -- Jan 09 09:34:16 2007\r
-\r
-\r
-\r
-LIBRARY ieee;\r
-\r
-USE ieee.std_logic_1164.ALL;\r
-USE ieee.numeric_std.ALL;\r
-\r
-\r
-entity VERGLEICH is\r
-      Port (    IN_A : In    std_logic_vector (31 downto 0);\r
-                IN_B : In    std_logic_vector (31 downto 0);\r
-             GLEICH_OUT : Out   std_logic );\r
-end VERGLEICH;\r
-\r
-architecture SCHEMATIC of VERGLEICH is\r
-\r
-   SIGNAL gnd : std_logic := '0';\r
-   SIGNAL vcc : std_logic := '1';\r
-\r
-   signal   GLEICH : std_logic_vector (7 downto 0);\r
-\r
-   component VERG_2\r
-      Port (    IN_A : In    std_logic_vector (1 downto 0);\r
-                IN_B : In    std_logic_vector (1 downto 0);\r
-              GLEICH : Out   std_logic );\r
-   end component;\r
-\r
-   component VERG_8\r
-      Port (  GLEICH : In    std_logic_vector (7 downto 0);\r
-             GLEICH_OUT : Out   std_logic );\r
-   end component;\r
-\r
-   component VERG_4\r
-      Port (    IN_A : In    std_logic_vector (3 downto 0);\r
-                IN_B : In    std_logic_vector (3 downto 0);\r
-              GLEICH : Out   std_logic );\r
-   end component;\r
-\r
-begin\r
-\r
-   I11 : VERG_2\r
-      Port Map ( IN_A(1 downto 0)=>IN_A(3 downto 2),\r
-                 IN_B(1 downto 0)=>IN_B(3 downto 2), GLEICH=>GLEICH(0) );\r
-   I9 : VERG_8\r
-      Port Map ( GLEICH(7 downto 0)=>GLEICH(7 downto 0),\r
-                 GLEICH_OUT=>GLEICH_OUT );\r
-   I8 : VERG_4\r
-      Port Map ( IN_A(3 downto 0)=>IN_A(31 downto 28),\r
-                 IN_B(3 downto 0)=>IN_B(31 downto 28), GLEICH=>GLEICH(7) );\r
-   I7 : VERG_4\r
-      Port Map ( IN_A(3 downto 0)=>IN_A(27 downto 24),\r
-                 IN_B(3 downto 0)=>IN_B(27 downto 24), GLEICH=>GLEICH(6) );\r
-   I6 : VERG_4\r
-      Port Map ( IN_A(3 downto 0)=>IN_A(23 downto 20),\r
-                 IN_B(3 downto 0)=>IN_B(23 downto 20), GLEICH=>GLEICH(5) );\r
-   I5 : VERG_4\r
-      Port Map ( IN_A(3 downto 0)=>IN_A(19 downto 16),\r
-                 IN_B(3 downto 0)=>IN_B(19 downto 16), GLEICH=>GLEICH(4) );\r
-   I4 : VERG_4\r
-      Port Map ( IN_A(3 downto 0)=>IN_A(15 downto 12),\r
-                 IN_B(3 downto 0)=>IN_B(15 downto 12), GLEICH=>GLEICH(3) );\r
-   I3 : VERG_4\r
-      Port Map ( IN_A(3 downto 0)=>IN_A(11 downto 8),\r
-                 IN_B(3 downto 0)=>IN_B(11 downto 8), GLEICH=>GLEICH(2) );\r
-   I2 : VERG_4\r
-      Port Map ( IN_A(3 downto 0)=>IN_A(7 downto 4),\r
-                 IN_B(3 downto 0)=>IN_B(7 downto 4), GLEICH=>GLEICH(1) );\r
-\r
-end SCHEMATIC;\r
+-- VHDL model created from schematic vergleich.sch -- Jan 09 09:34:16 2007
+
+
+
+LIBRARY ieee;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+
+entity VERGLEICH is
+      Port (    IN_A : In    std_logic_vector (31 downto 0);
+                IN_B : In    std_logic_vector (31 downto 0);
+             GLEICH_OUT : Out   std_logic );
+end VERGLEICH;
+
+architecture SCHEMATIC of VERGLEICH is
+
+   SIGNAL gnd : std_logic := '0';
+   SIGNAL vcc : std_logic := '1';
+
+   signal   GLEICH : std_logic_vector (7 downto 0);
+
+   component VERG_2
+      Port (    IN_A : In    std_logic_vector (1 downto 0);
+                IN_B : In    std_logic_vector (1 downto 0);
+              GLEICH : Out   std_logic );
+   end component;
+
+   component VERG_8
+      Port (  GLEICH : In    std_logic_vector (7 downto 0);
+             GLEICH_OUT : Out   std_logic );
+   end component;
+
+   component VERG_4
+      Port (    IN_A : In    std_logic_vector (3 downto 0);
+                IN_B : In    std_logic_vector (3 downto 0);
+              GLEICH : Out   std_logic );
+   end component;
+
+begin
+
+   I11 : VERG_2
+      Port Map ( IN_A(1 downto 0)=>IN_A(3 downto 2),
+                 IN_B(1 downto 0)=>IN_B(3 downto 2), GLEICH=>GLEICH(0) );
+   I9 : VERG_8
+      Port Map ( GLEICH(7 downto 0)=>GLEICH(7 downto 0),
+                 GLEICH_OUT=>GLEICH_OUT );
+   I8 : VERG_4
+      Port Map ( IN_A(3 downto 0)=>IN_A(31 downto 28),
+                 IN_B(3 downto 0)=>IN_B(31 downto 28), GLEICH=>GLEICH(7) );
+   I7 : VERG_4
+      Port Map ( IN_A(3 downto 0)=>IN_A(27 downto 24),
+                 IN_B(3 downto 0)=>IN_B(27 downto 24), GLEICH=>GLEICH(6) );
+   I6 : VERG_4
+      Port Map ( IN_A(3 downto 0)=>IN_A(23 downto 20),
+                 IN_B(3 downto 0)=>IN_B(23 downto 20), GLEICH=>GLEICH(5) );
+   I5 : VERG_4
+      Port Map ( IN_A(3 downto 0)=>IN_A(19 downto 16),
+                 IN_B(3 downto 0)=>IN_B(19 downto 16), GLEICH=>GLEICH(4) );
+   I4 : VERG_4
+      Port Map ( IN_A(3 downto 0)=>IN_A(15 downto 12),
+                 IN_B(3 downto 0)=>IN_B(15 downto 12), GLEICH=>GLEICH(3) );
+   I3 : VERG_4
+      Port Map ( IN_A(3 downto 0)=>IN_A(11 downto 8),
+                 IN_B(3 downto 0)=>IN_B(11 downto 8), GLEICH=>GLEICH(2) );
+   I2 : VERG_4
+      Port Map ( IN_A(3 downto 0)=>IN_A(7 downto 4),
+                 IN_B(3 downto 0)=>IN_B(7 downto 4), GLEICH=>GLEICH(1) );
+
+end SCHEMATIC;