update to EDK 9.1i

diff --git a/xps/raggedstone.mhs b/xps/raggedstone.mhs
index c21e39eff8b31bd74d24423a4272158265d1f6d0..fe6d836011cf8e52b005f2a0bff2560774d0a661 100644 (file)
--- a/xps/raggedstone.mhs
+++ b/xps/raggedstone.mhs
@@ -135,7 +135,7 @@ END
 
 BEGIN dcm_module
  PARAMETER INSTANCE = dcm_0
 
 BEGIN dcm_module
  PARAMETER INSTANCE = dcm_0

- PARAMETER HW_VER = 1.00.a
+ PARAMETER HW_VER = 1.00.b

  PARAMETER C_CLK0_BUF = TRUE
  PARAMETER C_CLKIN_PERIOD = 20.000000
  PARAMETER C_CLK_FEEDBACK = 1X
  PARAMETER C_CLK0_BUF = TRUE
  PARAMETER C_CLKIN_PERIOD = 20.000000
  PARAMETER C_CLK_FEEDBACK = 1X

diff --git a/xps/raggedstone.mss b/xps/raggedstone.mss
index 48442c2d5530fe61037c8ef2516cacf7572345ed..e68bbbd3b290202321eb802f7cd30ce3c47259ec 100644 (file)
--- a/xps/raggedstone.mss
+++ b/xps/raggedstone.mss
@@ -29,7 +29,7 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = uartlite
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = uartlite

- PARAMETER DRIVER_VER = 1.01.a
+ PARAMETER DRIVER_VER = 1.02.a

  PARAMETER HW_INSTANCE = debug_module
 END
 
  PARAMETER HW_INSTANCE = debug_module
 END
 


@@ -47,7 +47,7 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = uartlite
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = uartlite

- PARAMETER DRIVER_VER = 1.01.a
+ PARAMETER DRIVER_VER = 1.02.a

  PARAMETER HW_INSTANCE = RS232
 END
 
  PARAMETER HW_INSTANCE = RS232
 END
 

diff --git a/xps/raggedstone.xmp b/xps/raggedstone.xmp
index 2b393bb4cd9371ffebeebcdd93bf0b6726fd3657..8b2302fe80de8b64a3d2cfce7d04af33ba37fa86 100644 (file)
--- a/xps/raggedstone.xmp
+++ b/xps/raggedstone.xmp
@@ -1,5 +1,6 @@
 #Please do not modify this file by hand
 #Please do not modify this file by hand

-XmpVersion: 8.2.02
+XmpVersion: 9.1.01
+VerMgmt: 9.1.01

 IntStyle: default
 MHS File: raggedstone.mhs
 MSS File: raggedstone.mss
 IntStyle: default
 MHS File: raggedstone.mhs
 MSS File: raggedstone.mss


@@ -16,15 +17,12 @@ UserCmd1Type: 0
 UserCmd2: 
 UserCmd2Type: 0
 TopInst: system_i
 UserCmd2: 
 UserCmd2Type: 0
 TopInst: system_i

-ReloadPbde: 0
-MainMhsEditor: 0
+GenSimTB: 0

 InsertNoPads: 0
 WarnForEAArch: 1
 HdlLang: VHDL
 Simulator: mti
 SimModel: BEHAVIORAL
 InsertNoPads: 0
 WarnForEAArch: 1
 HdlLang: VHDL
 Simulator: mti
 SimModel: BEHAVIORAL

-SimXLib: 
-SimEdkLib: 

 MixLangSim: 1
 UcfFile: data/raggedstone.ucf
 FpgaImpMode: 0
 MixLangSim: 1
 UcfFile: data/raggedstone.ucf
 FpgaImpMode: 0