+= interface wb <=> fifo
authorsithglan <sithglan>
Sun, 11 Feb 2007 22:11:04 +0000 (22:11 +0000)
committersithglan <sithglan>
Sun, 11 Feb 2007 22:11:04 +0000 (22:11 +0000)
dhwk_old/source/wb_fifo.v [new file with mode: 0644]

diff --git a/dhwk_old/source/wb_fifo.v b/dhwk_old/source/wb_fifo.v
new file mode 100644 (file)
index 0000000..5ffd1b1
--- /dev/null
@@ -0,0 +1,37 @@
+module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i, \r
+       wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, fifo_data_i, fifo_data_o, fifo_we_o, fifo_re_o);\r
+\r
+       input clk_i;\r
+       input nrst_i;\r
+       input [24:1] wb_adr_i;\r
+       output [15:0] wb_dat_o;\r
+       input [15:0] wb_dat_i;\r
+       input [1:0] wb_sel_i;\r
+       input wb_we_i;\r
+       input wb_stb_i;\r
+       input wb_cyc_i;\r
+       output wb_ack_o;\r
+       output wb_err_o;\r
+       output wb_int_o;\r
+       input reg [7:0] fifo_data_i;\r
+       output reg [7:0] fifo_data_o;\r
+        output fifo_we_i;\r
+        output fifo_we_o;\r
+\r
+       reg [15:0]      data_reg;\r
+\r
+       always @(posedge clk_i or negedge nrst_i)\r
+       begin\r
+               if (nrst_i == 0)\r
+                       data_reg <= 16'hABCD;\r
+               else \r
+                       if (wb_stb_i && wb_we_i)\r
+                               data_reg <= wb_dat_i;\r
+       end\r
+\r
+       assign wb_ack_o = wb_stb_i;\r
+       assign wb_err_o = 1'b0;\r
+       assign wb_int_o = 1'b0;\r
+       assign wb_dat_o = data_reg;\r
+\r
+endmodule\r
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