-fifo_control stuff

diff --git a/dhwk/source/fifo_control.vhd b/dhwk/source/fifo_control.vhd
index 9a934046a5d88c7ba0e9a623724d37160c2befbe..1baa801b7199d5695ff8a884c4313e7aff210e99 100644 (file)
--- a/dhwk/source/fifo_control.vhd
+++ b/dhwk/source/fifo_control.vhd
@@ -43,9 +43,7 @@ entity FIFO_CONTROL is
              SERIAL_OUT : Out   std_logic;\r
              SPC_RDY_OUT : Out   std_logic;\r
              SR_ERROR : Out   std_logic;\r
              SERIAL_OUT : Out   std_logic;\r
              SPC_RDY_OUT : Out   std_logic;\r
              SR_ERROR : Out   std_logic;\r

-             SYNC_FLAG : Out   std_logic_vector (7 downto 0);\r
-            PAR_SER_IN : Out std_logic_vector (7 downto 0);\r
-            SER_PAR_OUT : Out std_logic_vector (7 downto 0));\r
+             SYNC_FLAG : Out   std_logic_vector (7 downto 0));\r

 end FIFO_CONTROL;\r
 \r
 architecture SCHEMATIC of FIFO_CONTROL is\r
 end FIFO_CONTROL;\r
 \r
 architecture SCHEMATIC of FIFO_CONTROL is\r


@@ -57,7 +55,6 @@ architecture SCHEMATIC of FIFO_CONTROL is
    signal XXXS_FIFO_READn : std_logic;\r
    signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);\r
    signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);\r
    signal XXXS_FIFO_READn : std_logic;\r
    signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);\r
    signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);\r

-   signal watcher : std_logic_vector (7 downto 0);\r

 \r
    component SER_PAR_CON\r
       Port ( PCI_CLOCK : In    std_logic;\r
 \r
    component SER_PAR_CON\r
       Port ( PCI_CLOCK : In    std_logic;\r


@@ -130,16 +127,13 @@ architecture SCHEMATIC of FIFO_CONTROL is
 begin\r
 \r
    SYNC_FLAG <= SYNC_FLAG_DUMMY;\r
 begin\r
 \r
    SYNC_FLAG <= SYNC_FLAG_DUMMY;\r

-   PAR_SER_IN <= S_FIFO_Q_OUT;\r
-   SER_PAR_OUT <= watcher;\r
-   R_FIFO_D_IN(7 downto 0) <= watcher;\r

 \r
    RESERVE <= gnd;\r
    I23 : SER_PAR_CON\r
       Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
                  SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,\r
                  SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
 \r
    RESERVE <= gnd;\r
    I23 : SER_PAR_CON\r
       Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
                  SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,\r
                  SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r

-                 PAR_OUT(7 downto 0)=>watcher,\r
+                 PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r

                  R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );\r
    I22 : PAR_SER_CON\r
       Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
                  R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );\r
    I22 : PAR_SER_CON\r
       Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 2d25fcd56fbfd04c0d1db0c626379d5b2d7ba114..4becb68de5b660595716589d730a2a40835bba91 100644 (file)
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -169,8 +169,6 @@ architecture SCHEMATIC of dhwk is
              SERIAL_OUT : Out   std_logic;\r
              SPC_RDY_OUT : Out   std_logic;\r
              SR_ERROR : Out   std_logic;\r
              SERIAL_OUT : Out   std_logic;\r
              SPC_RDY_OUT : Out   std_logic;\r
              SR_ERROR : Out   std_logic;\r

-            PAR_SER_IN : Out std_logic_vector (7 downto 0);\r
-            SER_PAR_OUT : Out std_logic_vector (7 downto 0);\r

              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
    end component;\r
 \r
              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
    end component;\r
 \r


@@ -273,6 +271,7 @@ begin
        data(16) <= SPC_RDY_IN;\r
        data(17) <= SERIAL_OUT;\r
        data(18) <= SPC_RDY_OUT;\r
        data(16) <= SPC_RDY_IN;\r
        data(17) <= SERIAL_OUT;\r
        data(18) <= SPC_RDY_OUT;\r

+       data(26 downto 19) <= S_FIFO_Q_OUT;\r

        data(34 downto 27) <= R_FIFO_Q_OUT;\r
 \r
    I19 : MESS_1_TB\r
        data(34 downto 27) <= R_FIFO_Q_OUT;\r
 \r
    I19 : MESS_1_TB\r


@@ -315,7 +314,6 @@ begin
                  S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
                  S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
                  SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
                  S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
                  S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
                  SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r

-                PAR_SER_IN(7 downto 0)=>data(26 downto 19),\r

                  SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
    I1 : PCI_TOP\r
       Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
                  SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
    I1 : PCI_TOP\r
       Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r