CDDR |= ((1<<POWER_PIN) | (1<<RESET_PIN));
/* About 1ms */
- OCR0 = ((F_CPU/256)/1000)-1;
+ OCR0 = ((F_CPU/64)/1000) - 1;
- TCCR0 = ((1<<WGM01) | (1<<CS02)); /* CTC, Prescaler 256 */
+ TCCR0 = ((1<<WGM01) | (1<<CS01) | (1<<CS00)); /* CTC, Prescaler 64 */
TIMSK |= (1<<OCIE0);
}
break;
case CHASSIS_ACTION_POWER_UP:
- chassis_power(500);
+ chassis_power(200);
break;
case CHASSIS_ACTION_HARD_RESET:
- chassis_reset(500);
+ chassis_reset(200);
break;
default: