galaxians
[fpga-games] / galaxian / src / altera / alt_ram_1024_8_8.v
1 // megafunction wizard: %RAM: 2-PORT%
2 // GENERATION: STANDARD
3 // VERSION: WM1.0
4 // MODULE: altsyncram
5
6 // ============================================================
7 // File Name: alt_ram_1024_8_8.v
8 // Megafunction Name(s):
9 // altsyncram
10 // ============================================================
11 // ************************************************************
12 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
13 //
14 // 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
15 // ************************************************************
16
17
18 //Copyright (C) 1991-2004 Altera Corporation
19 //Any megafunction design, and related netlist (encrypted or decrypted),
20 //support information, device programming or simulation file, and any other
21 //associated documentation or information provided by Altera or a partner
22 //under Altera's Megafunction Partnership Program may be used only
23 //to program PLD devices (but not masked PLD devices) from Altera. Any
24 //other use of such megafunction design, netlist, support information,
25 //device programming or simulation file, or any other related documentation
26 //or information is prohibited for any other purpose, including, but not
27 //limited to modification, reverse engineering, de-compiling, or use with
28 //any other silicon devices, unless such use is explicitly licensed under
29 //a separate agreement with Altera or a megafunction partner. Title to the
30 //intellectual property, including patents, copyrights, trademarks, trade
31 //secrets, or maskworks, embodied in any such megafunction design, netlist,
32 //support information, device programming or simulation file, or any other
33 //related documentation or information provided by Altera or a megafunction
34 //partner, remains with Altera, the megafunction partner, or their respective
35 //licensors. No other licenses, including any licenses needed under any third
36 //party's intellectual property, are provided herein.
37
38
39 // synopsys translate_off
40 `timescale 1 ps / 1 ps
41 // synopsys translate_on
42 module alt_ram_1024_8_8 (
43 data_a,
44 wren_a,
45 address_a,
46 data_b,
47 address_b,
48 wren_b,
49 clock_a,
50 enable_a,
51 clock_b,
52 enable_b,
53 q_a,
54 q_b);
55
56 input [7:0] data_a;
57 input wren_a;
58 input [9:0] address_a;
59 input [7:0] data_b;
60 input [9:0] address_b;
61 input wren_b;
62 input clock_a;
63 input enable_a;
64 input clock_b;
65 input enable_b;
66 output [7:0] q_a;
67 output [7:0] q_b;
68
69 wire [7:0] sub_wire0;
70 wire [7:0] sub_wire1;
71 wire [7:0] q_a = sub_wire0[7:0];
72 wire [7:0] q_b = sub_wire1[7:0];
73
74 altsyncram altsyncram_component (
75 .clocken0 (enable_a),
76 .clocken1 (enable_b),
77 .wren_a (wren_a),
78 .clock0 (clock_a),
79 .wren_b (wren_b),
80 .clock1 (clock_b),
81 .address_a (address_a),
82 .address_b (address_b),
83 .data_a (data_a),
84 .data_b (data_b),
85 .q_a (sub_wire0),
86 .q_b (sub_wire1)
87 // synopsys translate_off
88 ,
89 .rden_b (),
90 .aclr0 (),
91 .aclr1 (),
92 .byteena_a (),
93 .byteena_b (),
94 .addressstall_a (),
95 .addressstall_b ()
96 // synopsys translate_on
97
98 );
99 defparam
100 altsyncram_component.intended_device_family = "Cyclone",
101 altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
102 altsyncram_component.width_a = 8,
103 altsyncram_component.widthad_a = 10,
104 altsyncram_component.numwords_a = 1024,
105 altsyncram_component.width_b = 8,
106 altsyncram_component.widthad_b = 10,
107 altsyncram_component.numwords_b = 1024,
108 altsyncram_component.lpm_type = "altsyncram",
109 altsyncram_component.width_byteena_a = 1,
110 altsyncram_component.width_byteena_b = 1,
111 altsyncram_component.outdata_reg_a = "UNREGISTERED",
112 altsyncram_component.outdata_aclr_a = "NONE",
113 altsyncram_component.outdata_reg_b = "UNREGISTERED",
114 altsyncram_component.indata_aclr_a = "NONE",
115 altsyncram_component.wrcontrol_aclr_a = "NONE",
116 altsyncram_component.address_aclr_a = "NONE",
117 altsyncram_component.indata_reg_b = "CLOCK1",
118 altsyncram_component.address_reg_b = "CLOCK1",
119 altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1",
120 altsyncram_component.indata_aclr_b = "NONE",
121 altsyncram_component.wrcontrol_aclr_b = "NONE",
122 altsyncram_component.address_aclr_b = "NONE",
123 altsyncram_component.outdata_aclr_b = "NONE",
124 altsyncram_component.ram_block_type = "AUTO";
125
126
127 endmodule
128
129 // ============================================================
130 // CNX file retrieval info
131 // ============================================================
132 // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
133 // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
134 // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
135 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
136 // Retrieval info: PRIVATE: VarWidth NUMERIC "0"
137 // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
138 // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
139 // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
140 // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
141 // Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
142 // Retrieval info: PRIVATE: Clock NUMERIC "5"
143 // Retrieval info: PRIVATE: rden NUMERIC "0"
144 // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
145 // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
146 // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
147 // Retrieval info: PRIVATE: Clock_A NUMERIC "0"
148 // Retrieval info: PRIVATE: Clock_B NUMERIC "0"
149 // Retrieval info: PRIVATE: REGdata NUMERIC "1"
150 // Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
151 // Retrieval info: PRIVATE: REGwren NUMERIC "1"
152 // Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
153 // Retrieval info: PRIVATE: REGrren NUMERIC "0"
154 // Retrieval info: PRIVATE: REGq NUMERIC "0"
155 // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
156 // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
157 // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
158 // Retrieval info: PRIVATE: CLRdata NUMERIC "0"
159 // Retrieval info: PRIVATE: CLRwren NUMERIC "0"
160 // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
161 // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
162 // Retrieval info: PRIVATE: CLRrren NUMERIC "0"
163 // Retrieval info: PRIVATE: CLRq NUMERIC "0"
164 // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
165 // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
166 // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
167 // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
168 // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
169 // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
170 // Retrieval info: PRIVATE: enable NUMERIC "1"
171 // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
172 // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
173 // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
174 // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
175 // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
176 // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
177 // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
178 // Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
179 // Retrieval info: PRIVATE: MIFfilename STRING ""
180 // Retrieval info: PRIVATE: UseLCs NUMERIC "0"
181 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
182 // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
183 // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
184 // Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "wren_a;wren_b;rden_b;data_a;data_b"
185 // Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "address_a;address_b;clock0;clock1;clocken0"
186 // Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "clocken1;aclr0;aclr1;byteena_a;byteena_b"
187 // Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "addressstall_a;addressstall_b;q_a;q_b"
188 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
189 // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
190 // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
191 // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
192 // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
193 // Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
194 // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
195 // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
196 // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
197 // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
198 // Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
199 // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
200 // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
201 // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
202 // Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
203 // Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
204 // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
205 // Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
206 // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
207 // Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
208 // Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"
209 // Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"
210 // Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
211 // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
212 // Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"
213 // Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
214 // Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
215 // Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
216 // Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
217 // Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL address_a[9..0]
218 // Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
219 // Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL address_b[9..0]
220 // Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
221 // Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
222 // Retrieval info: USED_PORT: enable_a 0 0 0 0 INPUT VCC enable_a
223 // Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
224 // Retrieval info: USED_PORT: enable_b 0 0 0 0 INPUT VCC enable_b
225 // Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
226 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
227 // Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
228 // Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
229 // Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
230 // Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
231 // Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
232 // Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
233 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
234 // Retrieval info: CONNECT: @clocken0 0 0 0 0 enable_a 0 0 0 0
235 // Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
236 // Retrieval info: CONNECT: @clocken1 0 0 0 0 enable_b 0 0 0 0
237 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
238 // Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8.v TRUE
239 // Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8.inc FALSE
240 // Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8.cmp FALSE
241 // Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8.bsf FALSE
242 // Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8_inst.v FALSE
243 // Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8_bb.v FALSE
244 // Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8_waveforms.html FALSE
245 // Retrieval info: GEN_FILE: TYPE_NORMAL alt_ram_1024_8_8_wave*.jpg FALSE
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