galaxians
[fpga-games] / galaxian / src / altera / alt_ram_256_8.v
1 // megafunction wizard: %RAM: 1-PORT%
2 // GENERATION: STANDARD
3 // VERSION: WM1.0
4 // MODULE: altsyncram
5
6 // ============================================================
7 // File Name: alt_ram_256_8.v
8 // Megafunction Name(s):
9 // altsyncram
10 // ============================================================
11 // ************************************************************
12 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
13 // ************************************************************
14
15
16 //Copyright (C) 1991-2003 Altera Corporation
17 //Any megafunction design, and related netlist (encrypted or decrypted),
18 //support information, device programming or simulation file, and any other
19 //associated documentation or information provided by Altera or a partner
20 //under Altera's Megafunction Partnership Program may be used only
21 //to program PLD devices (but not masked PLD devices) from Altera. Any
22 //other use of such megafunction design, netlist, support information,
23 //device programming or simulation file, or any other related documentation
24 //or information is prohibited for any other purpose, including, but not
25 //limited to modification, reverse engineering, de-compiling, or use with
26 //any other silicon devices, unless such use is explicitly licensed under
27 //a separate agreement with Altera or a megafunction partner. Title to the
28 //intellectual property, including patents, copyrights, trademarks, trade
29 //secrets, or maskworks, embodied in any such megafunction design, netlist,
30 //support information, device programming or simulation file, or any other
31 //related documentation or information provided by Altera or a megafunction
32 //partner, remains with Altera, the megafunction partner, or their respective
33 //licensors. No other licenses, including any licenses needed under any third
34 //party's intellectual property, are provided herein.
35
36
37 module alt_ram_256_8 (
38 address,
39 clock,
40 data,
41 wren,
42 q);
43
44 input [7:0] address;
45 input clock;
46 input [7:0] data;
47 input wren;
48 output [7:0] q;
49
50 wire [7:0] sub_wire0;
51 wire [7:0] q = sub_wire0[7:0];
52
53 altsyncram altsyncram_component (
54 .wren_a (wren),
55 .clock0 (clock),
56 .address_a (address),
57 .data_a (data),
58 .q_a (sub_wire0));
59 defparam
60 altsyncram_component.intended_device_family = "Cyclone",
61 altsyncram_component.width_a = 8,
62 altsyncram_component.widthad_a = 8,
63 altsyncram_component.numwords_a = 256,
64 altsyncram_component.operation_mode = "SINGLE_PORT",
65 altsyncram_component.outdata_reg_a = "UNREGISTERED",
66 altsyncram_component.indata_aclr_a = "NONE",
67 altsyncram_component.wrcontrol_aclr_a = "NONE",
68 altsyncram_component.address_aclr_a = "NONE",
69 altsyncram_component.outdata_aclr_a = "NONE",
70 altsyncram_component.width_byteena_a = 1,
71 altsyncram_component.ram_block_type = "AUTO",
72 altsyncram_component.lpm_type = "altsyncram";
73
74
75 endmodule
76
77 // ============================================================
78 // CNX file retrieval info
79 // ============================================================
80 // Retrieval info: PRIVATE: WidthData NUMERIC "8"
81 // Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
82 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
83 // Retrieval info: PRIVATE: SingleClock NUMERIC "1"
84 // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
85 // Retrieval info: PRIVATE: RegData NUMERIC "1"
86 // Retrieval info: PRIVATE: RegAddr NUMERIC "1"
87 // Retrieval info: PRIVATE: RegOutput NUMERIC "0"
88 // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
89 // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
90 // Retrieval info: PRIVATE: AclrByte NUMERIC "0"
91 // Retrieval info: PRIVATE: AclrData NUMERIC "0"
92 // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
93 // Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
94 // Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
95 // Retrieval info: PRIVATE: Clken NUMERIC "0"
96 // Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
97 // Retrieval info: PRIVATE: MIFfilename STRING ""
98 // Retrieval info: PRIVATE: UseLCs NUMERIC "0"
99 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
100 // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
101 // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
102 // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
103 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
104 // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
105 // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
106 // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
107 // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
108 // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
109 // Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
110 // Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
111 // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
112 // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
113 // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
114 // Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"
115 // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
116 // Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
117 // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
118 // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
119 // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
120 // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
121 // Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
122 // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
123 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
124 // Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
125 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
126 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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