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15c4dc5a | 1 | //----------------------------------------------------------------------------- |
bd20f8f4 | 2 | // This code is licensed to you under the terms of the GNU GPL, version 2 or, |
3 | // at your option, any later version. See the LICENSE.txt file for the text of | |
4 | // the license. | |
5 | //----------------------------------------------------------------------------- | |
15c4dc5a | 6 | // Miscellaneous routines for low frequency tag operations. |
7 | // Tags supported here so far are Texas Instruments (TI), HID | |
8 | // Also routines for raw mode reading/simulating of LF waveform | |
15c4dc5a | 9 | //----------------------------------------------------------------------------- |
bd20f8f4 | 10 | |
e30c654b | 11 | #include "proxmark3.h" |
15c4dc5a | 12 | #include "apps.h" |
f7e3ed82 | 13 | #include "util.h" |
15c4dc5a | 14 | #include "hitag2.h" |
15 | #include "crc16.h" | |
9ab7a6c7 | 16 | #include "string.h" |
7db5f1ca | 17 | #include "lfdemod.h" |
15c4dc5a | 18 | |
cb366e9d MHS |
19 | typedef struct { |
20 | uint8_t * buffer; | |
21 | uint32_t numbits; | |
22 | uint8_t position; | |
23 | } BitstreamOut; | |
24 | /** | |
25 | * @brief Pushes bit onto the stream | |
26 | * @param stream | |
27 | * @param bit | |
28 | */ | |
29 | void pushBit( BitstreamOut* stream, bool bit) | |
30 | { | |
31 | int bytepos = stream->position >> 3; // divide by 8 | |
32 | int bitpos = stream->position & 7; | |
33 | *(stream->buffer+bytepos) |= (bit & 1) << (7 - bitpos); | |
34 | stream->position++; | |
35 | stream->numbits++; | |
36 | } | |
7c676e72 MHS |
37 | /** |
38 | * @brief Does LF sample acquisition, this method implements decimation and quantization in order to | |
39 | * be able to provide longer sample traces. | |
40 | * @param decimation - how much should the signal be decimated. A decimation of 1 means every sample, 2 means | |
41 | * every other sample, etc. | |
42 | * @param bits_per_sample - bits per sample. Max 8, min 1 bit per sample. | |
43 | * @param trigger_threshold - a threshold. The sampling won't commence until this threshold has been reached. Set | |
44 | * to -1 to ignore threshold. | |
45 | * @param averaging If set to true, decimation will use averaging, so that if e.g. decimation is 3, the sample | |
46 | * value that will be used is the average value of the three samples. | |
47 | * @return the number of bits occupied by the samples. | |
48 | */ | |
49 | uint8_t DoAcquisition(int decimation, int bits_per_sample, int trigger_threshold, bool averaging) | |
cb366e9d MHS |
50 | { |
51 | //A decimation of 2 means we keep every 2nd sample | |
52 | //A decimation of 3 means we keep 1 in 3 samples. | |
53 | //A quantization of 1 means one bit is discarded from the sample (division by 2). | |
54 | uint8_t *dest = (uint8_t *)BigBuf; | |
55 | int bufsize = BIGBUF_SIZE; | |
56 | memset(dest, 0, bufsize); | |
7c676e72 MHS |
57 | if(bits_per_sample < 1) bits_per_sample = 1; |
58 | if(bits_per_sample > 8) bits_per_sample = 8; | |
59 | ||
cb366e9d MHS |
60 | // Use a bit stream to handle the output |
61 | BitstreamOut data = { dest , 0, 0}; | |
62 | int sample_counter = 0; | |
63 | uint8_t sample = 0; | |
64 | //If we want to do averaging | |
65 | uint32_t sample_sum =0 ; | |
66 | uint32_t sample_total_numbers =0 ; | |
67 | uint32_t sample_total_saved =0 ; | |
68 | ||
69 | for(;;) { | |
70 | WDT_HIT(); | |
71 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { | |
72 | AT91C_BASE_SSC->SSC_THR = 0x43; | |
73 | LED_D_ON(); | |
74 | } | |
75 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { | |
76 | sample = (uint8_t)AT91C_BASE_SSC->SSC_RHR; | |
cb366e9d MHS |
77 | if (trigger_threshold != -1 && sample < trigger_threshold) |
78 | continue; | |
7242efa0 | 79 | sample_total_numbers++; |
cb366e9d MHS |
80 | |
81 | LED_D_OFF(); | |
82 | trigger_threshold = -1; | |
83 | sample_counter++; | |
84 | sample_sum += sample; | |
85 | //Check decimation | |
86 | if(sample_counter < decimation) continue; | |
87 | //Averaging | |
88 | if(averaging) sample = sample_sum / decimation; | |
89 | ||
90 | sample_counter = 0; | |
91 | sample_sum =0; | |
92 | sample_total_saved ++; | |
93 | pushBit(&data, sample & 0x80); | |
7c676e72 MHS |
94 | if(bits_per_sample > 1) pushBit(&data, sample & 0x40); |
95 | if(bits_per_sample > 2) pushBit(&data, sample & 0x20); | |
96 | if(bits_per_sample > 3) pushBit(&data, sample & 0x10); | |
97 | if(bits_per_sample > 4) pushBit(&data, sample & 0x08); | |
98 | if(bits_per_sample > 5) pushBit(&data, sample & 0x04); | |
99 | if(bits_per_sample > 6) pushBit(&data, sample & 0x02); | |
100 | if(bits_per_sample > 7) pushBit(&data, sample & 0x01); | |
cb366e9d | 101 | |
7c676e72 | 102 | if((data.numbits >> 3) +1 >= bufsize) break; |
cb366e9d MHS |
103 | } |
104 | } | |
105 | Dbprintf("Done, saved %l out of %l seen samples.",sample_total_saved, sample_total_numbers); | |
106 | ||
7c676e72 | 107 | return data.numbits; |
cb366e9d MHS |
108 | } |
109 | ||
b2256785 MHS |
110 | |
111 | /** | |
ba1a299c | 112 | * Does the sample acquisition. If threshold is specified, the actual sampling |
113 | * is not commenced until the threshold has been reached. | |
b2256785 MHS |
114 | * @param trigger_threshold - the threshold |
115 | * @param silent - is true, now outputs are made. If false, dbprints the status | |
116 | */ | |
f97d4e23 | 117 | void DoAcquisition125k_internal(int trigger_threshold,bool silent) |
69d88ec4 | 118 | { |
ae8e8a43 MHS |
119 | uint8_t *dest = (uint8_t *)BigBuf; |
120 | int n = sizeof(BigBuf); | |
121 | int i; | |
122 | ||
123 | memset(dest, 0, n); | |
124 | i = 0; | |
125 | for(;;) { | |
126 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { | |
127 | AT91C_BASE_SSC->SSC_THR = 0x43; | |
128 | LED_D_ON(); | |
129 | } | |
130 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { | |
131 | dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; | |
132 | LED_D_OFF(); | |
133 | if (trigger_threshold != -1 && dest[i] < trigger_threshold) | |
134 | continue; | |
135 | else | |
136 | trigger_threshold = -1; | |
137 | if (++i >= n) break; | |
138 | } | |
139 | } | |
140 | if(!silent) | |
141 | { | |
142 | Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...", | |
143 | dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]); | |
144 | ||
145 | } | |
69d88ec4 | 146 | } |
b2256785 | 147 | /** |
ba1a299c | 148 | * Perform sample aquisition. |
b2256785 | 149 | */ |
f97d4e23 | 150 | void DoAcquisition125k(int trigger_threshold) |
69d88ec4 | 151 | { |
ae8e8a43 | 152 | DoAcquisition125k_internal(trigger_threshold, false); |
69d88ec4 MHS |
153 | } |
154 | ||
b2256785 | 155 | /** |
ba1a299c | 156 | * Setup the FPGA to listen for samples. This method downloads the FPGA bitstream |
157 | * if not already loaded, sets divisor and starts up the antenna. | |
b2256785 MHS |
158 | * @param divisor : 1, 88> 255 or negative ==> 134.8 KHz |
159 | * 0 or 95 ==> 125 KHz | |
ba1a299c | 160 | * |
b2256785 | 161 | **/ |
b014c96d | 162 | void LFSetupFPGAForADC(int divisor, bool lf_field) |
15c4dc5a | 163 | { |
ae8e8a43 MHS |
164 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
165 | if ( (divisor == 1) || (divisor < 0) || (divisor > 255) ) | |
166 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz | |
167 | else if (divisor == 0) | |
168 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
169 | else | |
170 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor); | |
171 | ||
172 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0)); | |
173 | ||
174 | // Connect the A/D to the peak-detected low-frequency path. | |
175 | SetAdcMuxFor(GPIO_MUXSEL_LOPKD); | |
176 | // Give it a bit of time for the resonant antenna to settle. | |
177 | SpinDelay(50); | |
178 | // Now set up the SSC to get the ADC samples that are now streaming at us. | |
179 | FpgaSetupSsc(); | |
15c4dc5a | 180 | } |
b2256785 | 181 | /** |
ba1a299c | 182 | * Initializes the FPGA, and acquires the samples. |
b2256785 | 183 | **/ |
69d88ec4 | 184 | void AcquireRawAdcSamples125k(int divisor) |
15c4dc5a | 185 | { |
ae8e8a43 MHS |
186 | LFSetupFPGAForADC(divisor, true); |
187 | // Now call the acquisition routine | |
188 | DoAcquisition125k_internal(-1,false); | |
b014c96d | 189 | } |
b2256785 | 190 | /** |
ba1a299c | 191 | * Initializes the FPGA for snoop-mode, and acquires the samples. |
b2256785 MHS |
192 | **/ |
193 | ||
b014c96d | 194 | void SnoopLFRawAdcSamples(int divisor, int trigger_threshold) |
195 | { | |
ae8e8a43 MHS |
196 | LFSetupFPGAForADC(divisor, false); |
197 | DoAcquisition125k(trigger_threshold); | |
15c4dc5a | 198 | } |
199 | ||
f7e3ed82 | 200 | void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command) |
15c4dc5a | 201 | { |
15c4dc5a | 202 | |
ae8e8a43 MHS |
203 | /* Make sure the tag is reset */ |
204 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); | |
205 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
206 | SpinDelay(2500); | |
e30c654b | 207 | |
b2256785 | 208 | |
ae8e8a43 MHS |
209 | int divisor_used = 95; // 125 KHz |
210 | // see if 'h' was specified | |
b2256785 | 211 | |
ae8e8a43 MHS |
212 | if (command[strlen((char *) command) - 1] == 'h') |
213 | divisor_used = 88; // 134.8 KHz | |
15c4dc5a | 214 | |
15c4dc5a | 215 | |
ae8e8a43 MHS |
216 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); |
217 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); | |
218 | // Give it a bit of time for the resonant antenna to settle. | |
219 | SpinDelay(50); | |
b2256785 | 220 | |
ae8e8a43 MHS |
221 | // And a little more time for the tag to fully power up |
222 | SpinDelay(2000); | |
15c4dc5a | 223 | |
ae8e8a43 MHS |
224 | // Now set up the SSC to get the ADC samples that are now streaming at us. |
225 | FpgaSetupSsc(); | |
15c4dc5a | 226 | |
ae8e8a43 MHS |
227 | // now modulate the reader field |
228 | while(*command != '\0' && *command != ' ') { | |
229 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
230 | LED_D_OFF(); | |
231 | SpinDelayUs(delay_off); | |
232 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); | |
15c4dc5a | 233 | |
ae8e8a43 MHS |
234 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); |
235 | LED_D_ON(); | |
236 | if(*(command++) == '0') | |
237 | SpinDelayUs(period_0); | |
238 | else | |
239 | SpinDelayUs(period_1); | |
240 | } | |
241 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
242 | LED_D_OFF(); | |
243 | SpinDelayUs(delay_off); | |
244 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); | |
15c4dc5a | 245 | |
ae8e8a43 | 246 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); |
15c4dc5a | 247 | |
ae8e8a43 MHS |
248 | // now do the read |
249 | DoAcquisition125k(-1); | |
15c4dc5a | 250 | } |
251 | ||
252 | /* blank r/w tag data stream | |
253 | ...0000000000000000 01111111 | |
254 | 1010101010101010101010101010101010101010101010101010101010101010 | |
255 | 0011010010100001 | |
256 | 01111111 | |
257 | 101010101010101[0]000... | |
258 | ||
259 | [5555fe852c5555555555555555fe0000] | |
260 | */ | |
261 | void ReadTItag(void) | |
262 | { | |
ae8e8a43 MHS |
263 | // some hardcoded initial params |
264 | // when we read a TI tag we sample the zerocross line at 2Mhz | |
265 | // TI tags modulate a 1 as 16 cycles of 123.2Khz | |
266 | // TI tags modulate a 0 as 16 cycles of 134.2Khz | |
ba1a299c | 267 | #define FSAMPLE 2000000 |
268 | #define FREQLO 123200 | |
269 | #define FREQHI 134200 | |
ae8e8a43 MHS |
270 | |
271 | signed char *dest = (signed char *)BigBuf; | |
272 | int n = sizeof(BigBuf); | |
ae8e8a43 MHS |
273 | // 128 bit shift register [shift3:shift2:shift1:shift0] |
274 | uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0; | |
275 | ||
276 | int i, cycles=0, samples=0; | |
277 | // how many sample points fit in 16 cycles of each frequency | |
278 | uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI; | |
279 | // when to tell if we're close enough to one freq or another | |
280 | uint32_t threshold = (sampleslo - sampleshi + 1)>>1; | |
281 | ||
282 | // TI tags charge at 134.2Khz | |
283 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); | |
284 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz | |
285 | ||
286 | // Place FPGA in passthrough mode, in this mode the CROSS_LO line | |
287 | // connects to SSP_DIN and the SSP_DOUT logic level controls | |
288 | // whether we're modulating the antenna (high) | |
289 | // or listening to the antenna (low) | |
290 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); | |
291 | ||
292 | // get TI tag data into the buffer | |
293 | AcquireTiType(); | |
294 | ||
295 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
296 | ||
297 | for (i=0; i<n-1; i++) { | |
298 | // count cycles by looking for lo to hi zero crossings | |
299 | if ( (dest[i]<0) && (dest[i+1]>0) ) { | |
300 | cycles++; | |
301 | // after 16 cycles, measure the frequency | |
302 | if (cycles>15) { | |
303 | cycles=0; | |
304 | samples=i-samples; // number of samples in these 16 cycles | |
305 | ||
306 | // TI bits are coming to us lsb first so shift them | |
307 | // right through our 128 bit right shift register | |
308 | shift0 = (shift0>>1) | (shift1 << 31); | |
309 | shift1 = (shift1>>1) | (shift2 << 31); | |
310 | shift2 = (shift2>>1) | (shift3 << 31); | |
311 | shift3 >>= 1; | |
312 | ||
313 | // check if the cycles fall close to the number | |
314 | // expected for either the low or high frequency | |
315 | if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) { | |
316 | // low frequency represents a 1 | |
317 | shift3 |= (1<<31); | |
318 | } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) { | |
319 | // high frequency represents a 0 | |
320 | } else { | |
321 | // probably detected a gay waveform or noise | |
322 | // use this as gaydar or discard shift register and start again | |
323 | shift3 = shift2 = shift1 = shift0 = 0; | |
324 | } | |
325 | samples = i; | |
326 | ||
327 | // for each bit we receive, test if we've detected a valid tag | |
328 | ||
329 | // if we see 17 zeroes followed by 6 ones, we might have a tag | |
330 | // remember the bits are backwards | |
331 | if ( ((shift0 & 0x7fffff) == 0x7e0000) ) { | |
332 | // if start and end bytes match, we have a tag so break out of the loop | |
333 | if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) { | |
334 | cycles = 0xF0B; //use this as a flag (ugly but whatever) | |
335 | break; | |
336 | } | |
337 | } | |
338 | } | |
339 | } | |
340 | } | |
341 | ||
342 | // if flag is set we have a tag | |
343 | if (cycles!=0xF0B) { | |
344 | DbpString("Info: No valid tag detected."); | |
345 | } else { | |
346 | // put 64 bit data into shift1 and shift0 | |
347 | shift0 = (shift0>>24) | (shift1 << 8); | |
348 | shift1 = (shift1>>24) | (shift2 << 8); | |
349 | ||
350 | // align 16 bit crc into lower half of shift2 | |
351 | shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff; | |
352 | ||
353 | // if r/w tag, check ident match | |
ba1a299c | 354 | if (shift3 & (1<<15) ) { |
ae8e8a43 MHS |
355 | DbpString("Info: TI tag is rewriteable"); |
356 | // only 15 bits compare, last bit of ident is not valid | |
ba1a299c | 357 | if (((shift3 >> 16) ^ shift0) & 0x7fff ) { |
ae8e8a43 MHS |
358 | DbpString("Error: Ident mismatch!"); |
359 | } else { | |
360 | DbpString("Info: TI tag ident is valid"); | |
361 | } | |
362 | } else { | |
363 | DbpString("Info: TI tag is readonly"); | |
364 | } | |
365 | ||
366 | // WARNING the order of the bytes in which we calc crc below needs checking | |
367 | // i'm 99% sure the crc algorithm is correct, but it may need to eat the | |
368 | // bytes in reverse or something | |
369 | // calculate CRC | |
370 | uint32_t crc=0; | |
371 | ||
372 | crc = update_crc16(crc, (shift0)&0xff); | |
373 | crc = update_crc16(crc, (shift0>>8)&0xff); | |
374 | crc = update_crc16(crc, (shift0>>16)&0xff); | |
375 | crc = update_crc16(crc, (shift0>>24)&0xff); | |
376 | crc = update_crc16(crc, (shift1)&0xff); | |
377 | crc = update_crc16(crc, (shift1>>8)&0xff); | |
378 | crc = update_crc16(crc, (shift1>>16)&0xff); | |
379 | crc = update_crc16(crc, (shift1>>24)&0xff); | |
380 | ||
381 | Dbprintf("Info: Tag data: %x%08x, crc=%x", | |
382 | (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF); | |
383 | if (crc != (shift2&0xffff)) { | |
384 | Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc); | |
385 | } else { | |
386 | DbpString("Info: CRC is good"); | |
387 | } | |
388 | } | |
15c4dc5a | 389 | } |
390 | ||
f7e3ed82 | 391 | void WriteTIbyte(uint8_t b) |
15c4dc5a | 392 | { |
ae8e8a43 MHS |
393 | int i = 0; |
394 | ||
395 | // modulate 8 bits out to the antenna | |
396 | for (i=0; i<8; i++) | |
397 | { | |
398 | if (b&(1<<i)) { | |
399 | // stop modulating antenna | |
400 | LOW(GPIO_SSC_DOUT); | |
401 | SpinDelayUs(1000); | |
402 | // modulate antenna | |
403 | HIGH(GPIO_SSC_DOUT); | |
404 | SpinDelayUs(1000); | |
405 | } else { | |
406 | // stop modulating antenna | |
407 | LOW(GPIO_SSC_DOUT); | |
408 | SpinDelayUs(300); | |
409 | // modulate antenna | |
410 | HIGH(GPIO_SSC_DOUT); | |
411 | SpinDelayUs(1700); | |
412 | } | |
413 | } | |
15c4dc5a | 414 | } |
415 | ||
416 | void AcquireTiType(void) | |
417 | { | |
ae8e8a43 MHS |
418 | int i, j, n; |
419 | // tag transmission is <20ms, sampling at 2M gives us 40K samples max | |
420 | // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t | |
ba1a299c | 421 | #define TIBUFLEN 1250 |
ae8e8a43 MHS |
422 | |
423 | // clear buffer | |
424 | memset(BigBuf,0,sizeof(BigBuf)); | |
425 | ||
426 | // Set up the synchronous serial port | |
427 | AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN; | |
428 | AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN; | |
429 | ||
430 | // steal this pin from the SSP and use it to control the modulation | |
431 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; | |
432 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; | |
433 | ||
434 | AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST; | |
435 | AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN; | |
436 | ||
437 | // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long | |
438 | // 48/2 = 24 MHz clock must be divided by 12 | |
439 | AT91C_BASE_SSC->SSC_CMR = 12; | |
440 | ||
441 | AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0); | |
442 | AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF; | |
443 | AT91C_BASE_SSC->SSC_TCMR = 0; | |
444 | AT91C_BASE_SSC->SSC_TFMR = 0; | |
445 | ||
446 | LED_D_ON(); | |
447 | ||
448 | // modulate antenna | |
449 | HIGH(GPIO_SSC_DOUT); | |
450 | ||
451 | // Charge TI tag for 50ms. | |
452 | SpinDelay(50); | |
453 | ||
454 | // stop modulating antenna and listen | |
455 | LOW(GPIO_SSC_DOUT); | |
456 | ||
457 | LED_D_OFF(); | |
458 | ||
459 | i = 0; | |
460 | for(;;) { | |
461 | if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { | |
462 | BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer | |
463 | i++; if(i >= TIBUFLEN) break; | |
464 | } | |
465 | WDT_HIT(); | |
466 | } | |
467 | ||
468 | // return stolen pin to SSP | |
469 | AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT; | |
470 | AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT; | |
471 | ||
472 | char *dest = (char *)BigBuf; | |
473 | n = TIBUFLEN*32; | |
474 | // unpack buffer | |
475 | for (i=TIBUFLEN-1; i>=0; i--) { | |
476 | for (j=0; j<32; j++) { | |
477 | if(BigBuf[i] & (1 << j)) { | |
478 | dest[--n] = 1; | |
479 | } else { | |
480 | dest[--n] = -1; | |
481 | } | |
482 | } | |
483 | } | |
15c4dc5a | 484 | } |
485 | ||
486 | // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc | |
487 | // if crc provided, it will be written with the data verbatim (even if bogus) | |
488 | // if not provided a valid crc will be computed from the data and written. | |
f7e3ed82 | 489 | void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc) |
15c4dc5a | 490 | { |
ae8e8a43 MHS |
491 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
492 | if(crc == 0) { | |
493 | crc = update_crc16(crc, (idlo)&0xff); | |
494 | crc = update_crc16(crc, (idlo>>8)&0xff); | |
495 | crc = update_crc16(crc, (idlo>>16)&0xff); | |
496 | crc = update_crc16(crc, (idlo>>24)&0xff); | |
497 | crc = update_crc16(crc, (idhi)&0xff); | |
498 | crc = update_crc16(crc, (idhi>>8)&0xff); | |
499 | crc = update_crc16(crc, (idhi>>16)&0xff); | |
500 | crc = update_crc16(crc, (idhi>>24)&0xff); | |
501 | } | |
502 | Dbprintf("Writing to tag: %x%08x, crc=%x", | |
503 | (unsigned int) idhi, (unsigned int) idlo, crc); | |
504 | ||
505 | // TI tags charge at 134.2Khz | |
506 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz | |
507 | // Place FPGA in passthrough mode, in this mode the CROSS_LO line | |
508 | // connects to SSP_DIN and the SSP_DOUT logic level controls | |
509 | // whether we're modulating the antenna (high) | |
510 | // or listening to the antenna (low) | |
511 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); | |
512 | LED_A_ON(); | |
513 | ||
514 | // steal this pin from the SSP and use it to control the modulation | |
515 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; | |
516 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; | |
517 | ||
518 | // writing algorithm: | |
519 | // a high bit consists of a field off for 1ms and field on for 1ms | |
520 | // a low bit consists of a field off for 0.3ms and field on for 1.7ms | |
521 | // initiate a charge time of 50ms (field on) then immediately start writing bits | |
522 | // start by writing 0xBB (keyword) and 0xEB (password) | |
523 | // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer) | |
524 | // finally end with 0x0300 (write frame) | |
525 | // all data is sent lsb firts | |
526 | // finish with 15ms programming time | |
527 | ||
528 | // modulate antenna | |
529 | HIGH(GPIO_SSC_DOUT); | |
530 | SpinDelay(50); // charge time | |
531 | ||
532 | WriteTIbyte(0xbb); // keyword | |
533 | WriteTIbyte(0xeb); // password | |
534 | WriteTIbyte( (idlo )&0xff ); | |
535 | WriteTIbyte( (idlo>>8 )&0xff ); | |
536 | WriteTIbyte( (idlo>>16)&0xff ); | |
537 | WriteTIbyte( (idlo>>24)&0xff ); | |
538 | WriteTIbyte( (idhi )&0xff ); | |
539 | WriteTIbyte( (idhi>>8 )&0xff ); | |
540 | WriteTIbyte( (idhi>>16)&0xff ); | |
541 | WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo | |
542 | WriteTIbyte( (crc )&0xff ); // crc lo | |
543 | WriteTIbyte( (crc>>8 )&0xff ); // crc hi | |
544 | WriteTIbyte(0x00); // write frame lo | |
545 | WriteTIbyte(0x03); // write frame hi | |
546 | HIGH(GPIO_SSC_DOUT); | |
547 | SpinDelay(50); // programming time | |
548 | ||
549 | LED_A_OFF(); | |
550 | ||
551 | // get TI tag data into the buffer | |
552 | AcquireTiType(); | |
553 | ||
554 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
555 | DbpString("Now use tiread to check"); | |
15c4dc5a | 556 | } |
557 | ||
558 | void SimulateTagLowFrequency(int period, int gap, int ledcontrol) | |
559 | { | |
ae8e8a43 MHS |
560 | int i; |
561 | uint8_t *tab = (uint8_t *)BigBuf; | |
ba1a299c | 562 | |
ae8e8a43 MHS |
563 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
564 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT); | |
ba1a299c | 565 | |
ae8e8a43 | 566 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK; |
ba1a299c | 567 | |
ae8e8a43 MHS |
568 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; |
569 | AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK; | |
ba1a299c | 570 | |
15c4dc5a | 571 | #define SHORT_COIL() LOW(GPIO_SSC_DOUT) |
572 | #define OPEN_COIL() HIGH(GPIO_SSC_DOUT) | |
ba1a299c | 573 | |
ae8e8a43 MHS |
574 | i = 0; |
575 | for(;;) { | |
576 | while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) { | |
577 | if(BUTTON_PRESS()) { | |
578 | DbpString("Stopped"); | |
579 | return; | |
580 | } | |
581 | WDT_HIT(); | |
582 | } | |
952a8bb5 | 583 | |
ae8e8a43 MHS |
584 | if (ledcontrol) |
585 | LED_D_ON(); | |
952a8bb5 | 586 | |
ae8e8a43 MHS |
587 | if(tab[i]) |
588 | OPEN_COIL(); | |
589 | else | |
590 | SHORT_COIL(); | |
952a8bb5 | 591 | |
ae8e8a43 MHS |
592 | if (ledcontrol) |
593 | LED_D_OFF(); | |
952a8bb5 | 594 | |
ae8e8a43 MHS |
595 | while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) { |
596 | if(BUTTON_PRESS()) { | |
597 | DbpString("Stopped"); | |
598 | return; | |
599 | } | |
600 | WDT_HIT(); | |
601 | } | |
952a8bb5 | 602 | |
ae8e8a43 MHS |
603 | i++; |
604 | if(i == period) { | |
605 | i = 0; | |
606 | if (gap) { | |
607 | SHORT_COIL(); | |
608 | SpinDelayUs(gap); | |
609 | } | |
610 | } | |
611 | } | |
15c4dc5a | 612 | } |
613 | ||
15c4dc5a | 614 | #define DEBUG_FRAME_CONTENTS 1 |
615 | void SimulateTagLowFrequencyBidir(int divisor, int t0) | |
616 | { | |
15c4dc5a | 617 | } |
618 | ||
619 | // compose fc/8 fc/10 waveform | |
620 | static void fc(int c, int *n) { | |
ae8e8a43 MHS |
621 | uint8_t *dest = (uint8_t *)BigBuf; |
622 | int idx; | |
623 | ||
624 | // for when we want an fc8 pattern every 4 logical bits | |
625 | if(c==0) { | |
626 | dest[((*n)++)]=1; | |
627 | dest[((*n)++)]=1; | |
628 | dest[((*n)++)]=0; | |
629 | dest[((*n)++)]=0; | |
630 | dest[((*n)++)]=0; | |
631 | dest[((*n)++)]=0; | |
632 | dest[((*n)++)]=0; | |
633 | dest[((*n)++)]=0; | |
634 | } | |
635 | // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples | |
636 | if(c==8) { | |
637 | for (idx=0; idx<6; idx++) { | |
638 | dest[((*n)++)]=1; | |
639 | dest[((*n)++)]=1; | |
640 | dest[((*n)++)]=0; | |
641 | dest[((*n)++)]=0; | |
642 | dest[((*n)++)]=0; | |
643 | dest[((*n)++)]=0; | |
644 | dest[((*n)++)]=0; | |
645 | dest[((*n)++)]=0; | |
646 | } | |
647 | } | |
648 | ||
649 | // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples | |
650 | if(c==10) { | |
651 | for (idx=0; idx<5; idx++) { | |
652 | dest[((*n)++)]=1; | |
653 | dest[((*n)++)]=1; | |
654 | dest[((*n)++)]=1; | |
655 | dest[((*n)++)]=0; | |
656 | dest[((*n)++)]=0; | |
657 | dest[((*n)++)]=0; | |
658 | dest[((*n)++)]=0; | |
659 | dest[((*n)++)]=0; | |
660 | dest[((*n)++)]=0; | |
661 | dest[((*n)++)]=0; | |
662 | } | |
663 | } | |
15c4dc5a | 664 | } |
665 | ||
666 | // prepare a waveform pattern in the buffer based on the ID given then | |
667 | // simulate a HID tag until the button is pressed | |
668 | void CmdHIDsimTAG(int hi, int lo, int ledcontrol) | |
669 | { | |
ae8e8a43 MHS |
670 | int n=0, i=0; |
671 | /* | |
672 | HID tag bitstream format | |
673 | The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits | |
674 | A 1 bit is represented as 6 fc8 and 5 fc10 patterns | |
675 | A 0 bit is represented as 5 fc10 and 6 fc8 patterns | |
676 | A fc8 is inserted before every 4 bits | |
677 | A special start of frame pattern is used consisting a0b0 where a and b are neither 0 | |
678 | nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10) | |
679 | */ | |
680 | ||
681 | if (hi>0xFFF) { | |
682 | DbpString("Tags can only have 44 bits."); | |
683 | return; | |
684 | } | |
685 | fc(0,&n); | |
686 | // special start of frame marker containing invalid bit sequences | |
687 | fc(8, &n); fc(8, &n); // invalid | |
688 | fc(8, &n); fc(10, &n); // logical 0 | |
689 | fc(10, &n); fc(10, &n); // invalid | |
690 | fc(8, &n); fc(10, &n); // logical 0 | |
691 | ||
692 | WDT_HIT(); | |
693 | // manchester encode bits 43 to 32 | |
694 | for (i=11; i>=0; i--) { | |
695 | if ((i%4)==3) fc(0,&n); | |
696 | if ((hi>>i)&1) { | |
697 | fc(10, &n); fc(8, &n); // low-high transition | |
698 | } else { | |
699 | fc(8, &n); fc(10, &n); // high-low transition | |
700 | } | |
701 | } | |
702 | ||
703 | WDT_HIT(); | |
704 | // manchester encode bits 31 to 0 | |
705 | for (i=31; i>=0; i--) { | |
706 | if ((i%4)==3) fc(0,&n); | |
707 | if ((lo>>i)&1) { | |
708 | fc(10, &n); fc(8, &n); // low-high transition | |
709 | } else { | |
710 | fc(8, &n); fc(10, &n); // high-low transition | |
711 | } | |
712 | } | |
713 | ||
714 | if (ledcontrol) | |
715 | LED_A_ON(); | |
716 | SimulateTagLowFrequency(n, 0, ledcontrol); | |
717 | ||
718 | if (ledcontrol) | |
719 | LED_A_OFF(); | |
15c4dc5a | 720 | } |
eb191de6 | 721 | |
b3b70669 | 722 | // loop to get raw HID waveform then FSK demodulate the TAG ID from it |
69d88ec4 MHS |
723 | void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol) |
724 | { | |
ae8e8a43 MHS |
725 | uint8_t *dest = (uint8_t *)BigBuf; |
726 | ||
727 | size_t size=0; //, found=0; | |
728 | uint32_t hi2=0, hi=0, lo=0; | |
729 | ||
730 | // Configure to go in 125Khz listen mode | |
731 | LFSetupFPGAForADC(95, true); | |
732 | ||
733 | while(!BUTTON_PRESS()) { | |
734 | ||
735 | WDT_HIT(); | |
736 | if (ledcontrol) LED_A_ON(); | |
737 | ||
738 | DoAcquisition125k_internal(-1,true); | |
ae8e8a43 | 739 | // FSK demodulator |
d91a31f9 | 740 | size = HIDdemodFSK(dest, sizeof(BigBuf), &hi2, &hi, &lo); |
ae8e8a43 MHS |
741 | |
742 | WDT_HIT(); | |
743 | ||
d91a31f9 | 744 | if (size>0 && lo>0){ |
ae8e8a43 MHS |
745 | // final loop, go over previously decoded manchester data and decode into usable tag ID |
746 | // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0 | |
747 | if (hi2 != 0){ //extra large HID tags | |
748 | Dbprintf("TAG ID: %x%08x%08x (%d)", | |
749 | (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); | |
750 | }else { //standard HID tags <38 bits | |
751 | //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd | |
752 | uint8_t bitlen = 0; | |
753 | uint32_t fc = 0; | |
754 | uint32_t cardnum = 0; | |
ba1a299c | 755 | if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used |
ae8e8a43 MHS |
756 | uint32_t lo2=0; |
757 | lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit | |
758 | uint8_t idx3 = 1; | |
ba1a299c | 759 | while(lo2 > 1){ //find last bit set to 1 (format len bit) |
760 | lo2=lo2 >> 1; | |
ae8e8a43 MHS |
761 | idx3++; |
762 | } | |
ba1a299c | 763 | bitlen = idx3+19; |
ae8e8a43 MHS |
764 | fc =0; |
765 | cardnum=0; | |
ba1a299c | 766 | if(bitlen == 26){ |
ae8e8a43 MHS |
767 | cardnum = (lo>>1)&0xFFFF; |
768 | fc = (lo>>17)&0xFF; | |
769 | } | |
ba1a299c | 770 | if(bitlen == 37){ |
ae8e8a43 MHS |
771 | cardnum = (lo>>1)&0x7FFFF; |
772 | fc = ((hi&0xF)<<12)|(lo>>20); | |
773 | } | |
ba1a299c | 774 | if(bitlen == 34){ |
ae8e8a43 MHS |
775 | cardnum = (lo>>1)&0xFFFF; |
776 | fc= ((hi&1)<<15)|(lo>>17); | |
777 | } | |
ba1a299c | 778 | if(bitlen == 35){ |
ae8e8a43 MHS |
779 | cardnum = (lo>>1)&0xFFFFF; |
780 | fc = ((hi&1)<<11)|(lo>>21); | |
781 | } | |
782 | } | |
783 | else { //if bit 38 is not set then 37 bit format is used | |
784 | bitlen= 37; | |
785 | fc =0; | |
786 | cardnum=0; | |
787 | if(bitlen==37){ | |
788 | cardnum = (lo>>1)&0x7FFFF; | |
789 | fc = ((hi&0xF)<<12)|(lo>>20); | |
790 | } | |
791 | } | |
792 | //Dbprintf("TAG ID: %x%08x (%d)", | |
793 | // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); | |
794 | Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d", | |
795 | (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF, | |
796 | (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum); | |
797 | } | |
798 | if (findone){ | |
799 | if (ledcontrol) LED_A_OFF(); | |
800 | return; | |
801 | } | |
802 | // reset | |
803 | hi2 = hi = lo = 0; | |
804 | } | |
805 | WDT_HIT(); | |
ae8e8a43 MHS |
806 | } |
807 | DbpString("Stopped"); | |
808 | if (ledcontrol) LED_A_OFF(); | |
eb191de6 | 809 | } |
810 | ||
66707a3b | 811 | void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol) |
eb191de6 | 812 | { |
ae8e8a43 MHS |
813 | uint8_t *dest = (uint8_t *)BigBuf; |
814 | ||
d91a31f9 | 815 | size_t size=0; |
ae8e8a43 MHS |
816 | int clk=0, invert=0, errCnt=0; |
817 | uint64_t lo=0; | |
818 | // Configure to go in 125Khz listen mode | |
819 | LFSetupFPGAForADC(95, true); | |
820 | ||
821 | while(!BUTTON_PRESS()) { | |
822 | ||
823 | WDT_HIT(); | |
824 | if (ledcontrol) LED_A_ON(); | |
825 | ||
826 | DoAcquisition125k_internal(-1,true); | |
827 | size = sizeof(BigBuf); | |
ae8e8a43 | 828 | //Dbprintf("DEBUG: Buffer got"); |
d91a31f9 | 829 | //askdemod and manchester decode |
830 | errCnt = askmandemod(dest, &size, &clk, &invert); | |
ae8e8a43 MHS |
831 | //Dbprintf("DEBUG: ASK Got"); |
832 | WDT_HIT(); | |
833 | ||
834 | if (errCnt>=0){ | |
d91a31f9 | 835 | lo = Em410xDecode(dest,size); |
ae8e8a43 | 836 | //Dbprintf("DEBUG: EM GOT"); |
ae8e8a43 | 837 | if (lo>0){ |
d91a31f9 | 838 | Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)", |
839 | (uint32_t)(lo>>32), | |
840 | (uint32_t)lo, | |
841 | (uint32_t)(lo&0xFFFF), | |
842 | (uint32_t)((lo>>16LL) & 0xFF), | |
843 | (uint32_t)(lo & 0xFFFFFF)); | |
ae8e8a43 MHS |
844 | } |
845 | if (findone){ | |
846 | if (ledcontrol) LED_A_OFF(); | |
847 | return; | |
848 | } | |
849 | } else{ | |
850 | //Dbprintf("DEBUG: No Tag"); | |
851 | } | |
852 | WDT_HIT(); | |
853 | lo = 0; | |
854 | clk=0; | |
855 | invert=0; | |
856 | errCnt=0; | |
857 | size=0; | |
ae8e8a43 MHS |
858 | } |
859 | DbpString("Stopped"); | |
860 | if (ledcontrol) LED_A_OFF(); | |
15c4dc5a | 861 | } |
69d88ec4 | 862 | |
a1f3bb12 | 863 | void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol) |
eb191de6 | 864 | { |
ae8e8a43 | 865 | uint8_t *dest = (uint8_t *)BigBuf; |
ae8e8a43 MHS |
866 | int idx=0; |
867 | uint32_t code=0, code2=0; | |
868 | uint8_t version=0; | |
869 | uint8_t facilitycode=0; | |
870 | uint16_t number=0; | |
871 | // Configure to go in 125Khz listen mode | |
872 | LFSetupFPGAForADC(95, true); | |
873 | ||
874 | while(!BUTTON_PRESS()) { | |
875 | WDT_HIT(); | |
876 | if (ledcontrol) LED_A_ON(); | |
877 | DoAcquisition125k_internal(-1,true); | |
878 | //fskdemod and get start index | |
879 | WDT_HIT(); | |
6ca4c646 | 880 | idx = IOdemodFSK(dest,sizeof(BigBuf)); |
ae8e8a43 MHS |
881 | if (idx>0){ |
882 | //valid tag found | |
883 | ||
884 | //Index map | |
885 | //0 10 20 30 40 50 60 | |
886 | //| | | | | | | | |
887 | //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23 | |
888 | //----------------------------------------------------------------------------- | |
889 | //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11 | |
890 | // | |
891 | //XSF(version)facility:codeone+codetwo | |
892 | //Handle the data | |
893 | if(findone){ //only print binary if we are doing one | |
894 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]); | |
895 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]); | |
896 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]); | |
897 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]); | |
898 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]); | |
899 | Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]); | |
900 | Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]); | |
901 | } | |
902 | code = bytebits_to_byte(dest+idx,32); | |
903 | code2 = bytebits_to_byte(dest+idx+32,32); | |
904 | version = bytebits_to_byte(dest+idx+27,8); //14,4 | |
905 | facilitycode = bytebits_to_byte(dest+idx+18,8) ; | |
906 | number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9 | |
907 | ||
908 | Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2); | |
909 | // if we're only looking for one tag | |
910 | if (findone){ | |
911 | if (ledcontrol) LED_A_OFF(); | |
912 | //LED_A_OFF(); | |
913 | return; | |
914 | } | |
915 | code=code2=0; | |
916 | version=facilitycode=0; | |
917 | number=0; | |
918 | idx=0; | |
919 | } | |
920 | WDT_HIT(); | |
921 | } | |
922 | DbpString("Stopped"); | |
923 | if (ledcontrol) LED_A_OFF(); | |
eb191de6 | 924 | } |
a1f3bb12 | 925 | |
2d4eae76 | 926 | /*------------------------------ |
927 | * T5555/T5557/T5567 routines | |
928 | *------------------------------ | |
929 | */ | |
930 | ||
931 | /* T55x7 configuration register definitions */ | |
932 | #define T55x7_POR_DELAY 0x00000001 | |
933 | #define T55x7_ST_TERMINATOR 0x00000008 | |
934 | #define T55x7_PWD 0x00000010 | |
935 | #define T55x7_MAXBLOCK_SHIFT 5 | |
936 | #define T55x7_AOR 0x00000200 | |
937 | #define T55x7_PSKCF_RF_2 0 | |
938 | #define T55x7_PSKCF_RF_4 0x00000400 | |
939 | #define T55x7_PSKCF_RF_8 0x00000800 | |
940 | #define T55x7_MODULATION_DIRECT 0 | |
941 | #define T55x7_MODULATION_PSK1 0x00001000 | |
942 | #define T55x7_MODULATION_PSK2 0x00002000 | |
943 | #define T55x7_MODULATION_PSK3 0x00003000 | |
944 | #define T55x7_MODULATION_FSK1 0x00004000 | |
945 | #define T55x7_MODULATION_FSK2 0x00005000 | |
946 | #define T55x7_MODULATION_FSK1a 0x00006000 | |
947 | #define T55x7_MODULATION_FSK2a 0x00007000 | |
948 | #define T55x7_MODULATION_MANCHESTER 0x00008000 | |
949 | #define T55x7_MODULATION_BIPHASE 0x00010000 | |
950 | #define T55x7_BITRATE_RF_8 0 | |
951 | #define T55x7_BITRATE_RF_16 0x00040000 | |
952 | #define T55x7_BITRATE_RF_32 0x00080000 | |
953 | #define T55x7_BITRATE_RF_40 0x000C0000 | |
954 | #define T55x7_BITRATE_RF_50 0x00100000 | |
955 | #define T55x7_BITRATE_RF_64 0x00140000 | |
956 | #define T55x7_BITRATE_RF_100 0x00180000 | |
957 | #define T55x7_BITRATE_RF_128 0x001C0000 | |
958 | ||
959 | /* T5555 (Q5) configuration register definitions */ | |
960 | #define T5555_ST_TERMINATOR 0x00000001 | |
961 | #define T5555_MAXBLOCK_SHIFT 0x00000001 | |
962 | #define T5555_MODULATION_MANCHESTER 0 | |
963 | #define T5555_MODULATION_PSK1 0x00000010 | |
964 | #define T5555_MODULATION_PSK2 0x00000020 | |
965 | #define T5555_MODULATION_PSK3 0x00000030 | |
966 | #define T5555_MODULATION_FSK1 0x00000040 | |
967 | #define T5555_MODULATION_FSK2 0x00000050 | |
968 | #define T5555_MODULATION_BIPHASE 0x00000060 | |
969 | #define T5555_MODULATION_DIRECT 0x00000070 | |
970 | #define T5555_INVERT_OUTPUT 0x00000080 | |
971 | #define T5555_PSK_RF_2 0 | |
972 | #define T5555_PSK_RF_4 0x00000100 | |
973 | #define T5555_PSK_RF_8 0x00000200 | |
974 | #define T5555_USE_PWD 0x00000400 | |
975 | #define T5555_USE_AOR 0x00000800 | |
976 | #define T5555_BITRATE_SHIFT 12 | |
977 | #define T5555_FAST_WRITE 0x00004000 | |
978 | #define T5555_PAGE_SELECT 0x00008000 | |
979 | ||
980 | /* | |
981 | * Relevant times in microsecond | |
982 | * To compensate antenna falling times shorten the write times | |
983 | * and enlarge the gap ones. | |
984 | */ | |
985 | #define START_GAP 250 | |
986 | #define WRITE_GAP 160 | |
987 | #define WRITE_0 144 // 192 | |
988 | #define WRITE_1 400 // 432 for T55x7; 448 for E5550 | |
989 | ||
990 | // Write one bit to card | |
991 | void T55xxWriteBit(int bit) | |
ec09b62d | 992 | { |
ae8e8a43 MHS |
993 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); |
994 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
995 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); | |
996 | if (bit == 0) | |
997 | SpinDelayUs(WRITE_0); | |
998 | else | |
999 | SpinDelayUs(WRITE_1); | |
1000 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
1001 | SpinDelayUs(WRITE_GAP); | |
ec09b62d | 1002 | } |
1003 | ||
2d4eae76 | 1004 | // Write one card block in page 0, no lock |
54a942b0 | 1005 | void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode) |
ec09b62d | 1006 | { |
ae8e8a43 MHS |
1007 | //unsigned int i; //enio adjustment 12/10/14 |
1008 | uint32_t i; | |
1009 | ||
1010 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); | |
1011 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
1012 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); | |
1013 | ||
1014 | // Give it a bit of time for the resonant antenna to settle. | |
1015 | // And for the tag to fully power up | |
1016 | SpinDelay(150); | |
1017 | ||
1018 | // Now start writting | |
1019 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
1020 | SpinDelayUs(START_GAP); | |
1021 | ||
1022 | // Opcode | |
1023 | T55xxWriteBit(1); | |
1024 | T55xxWriteBit(0); //Page 0 | |
1025 | if (PwdMode == 1){ | |
1026 | // Pwd | |
1027 | for (i = 0x80000000; i != 0; i >>= 1) | |
1028 | T55xxWriteBit(Pwd & i); | |
1029 | } | |
1030 | // Lock bit | |
1031 | T55xxWriteBit(0); | |
1032 | ||
1033 | // Data | |
54a942b0 | 1034 | for (i = 0x80000000; i != 0; i >>= 1) |
ae8e8a43 MHS |
1035 | T55xxWriteBit(Data & i); |
1036 | ||
1037 | // Block | |
1038 | for (i = 0x04; i != 0; i >>= 1) | |
1039 | T55xxWriteBit(Block & i); | |
1040 | ||
1041 | // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550, | |
1042 | // so wait a little more) | |
1043 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
1044 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); | |
1045 | SpinDelay(20); | |
1046 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
ec09b62d | 1047 | } |
1048 | ||
54a942b0 | 1049 | // Read one card block in page 0 |
1050 | void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode) | |
ec09b62d | 1051 | { |
ae8e8a43 MHS |
1052 | uint8_t *dest = (uint8_t *)BigBuf; |
1053 | //int m=0, i=0; //enio adjustment 12/10/14 | |
1054 | uint32_t m=0, i=0; | |
1055 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); | |
1056 | m = sizeof(BigBuf); | |
1057 | // Clear destination buffer before sending the command | |
1058 | memset(dest, 128, m); | |
1059 | // Connect the A/D to the peak-detected low-frequency path. | |
1060 | SetAdcMuxFor(GPIO_MUXSEL_LOPKD); | |
1061 | // Now set up the SSC to get the ADC samples that are now streaming at us. | |
1062 | FpgaSetupSsc(); | |
1063 | ||
1064 | LED_D_ON(); | |
1065 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
1066 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); | |
1067 | ||
1068 | // Give it a bit of time for the resonant antenna to settle. | |
1069 | // And for the tag to fully power up | |
1070 | SpinDelay(150); | |
1071 | ||
1072 | // Now start writting | |
1073 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
1074 | SpinDelayUs(START_GAP); | |
1075 | ||
1076 | // Opcode | |
1077 | T55xxWriteBit(1); | |
1078 | T55xxWriteBit(0); //Page 0 | |
1079 | if (PwdMode == 1){ | |
1080 | // Pwd | |
1081 | for (i = 0x80000000; i != 0; i >>= 1) | |
1082 | T55xxWriteBit(Pwd & i); | |
1083 | } | |
1084 | // Lock bit | |
1085 | T55xxWriteBit(0); | |
1086 | // Block | |
1087 | for (i = 0x04; i != 0; i >>= 1) | |
1088 | T55xxWriteBit(Block & i); | |
1089 | ||
1090 | // Turn field on to read the response | |
1091 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
1092 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); | |
1093 | ||
1094 | // Now do the acquisition | |
1095 | i = 0; | |
1096 | for(;;) { | |
1097 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { | |
1098 | AT91C_BASE_SSC->SSC_THR = 0x43; | |
1099 | } | |
1100 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { | |
1101 | dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; | |
1102 | // we don't care about actual value, only if it's more or less than a | |
1103 | // threshold essentially we capture zero crossings for later analysis | |
1104 | // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1; | |
1105 | i++; | |
1106 | if (i >= m) break; | |
1107 | } | |
1108 | } | |
1109 | ||
1110 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
1111 | LED_D_OFF(); | |
1112 | DbpString("DONE!"); | |
54a942b0 | 1113 | } |
2d4eae76 | 1114 | |
54a942b0 | 1115 | // Read card traceability data (page 1) |
1116 | void T55xxReadTrace(void){ | |
ae8e8a43 MHS |
1117 | uint8_t *dest = (uint8_t *)BigBuf; |
1118 | int m=0, i=0; | |
1119 | ||
1120 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); | |
1121 | m = sizeof(BigBuf); | |
1122 | // Clear destination buffer before sending the command | |
1123 | memset(dest, 128, m); | |
1124 | // Connect the A/D to the peak-detected low-frequency path. | |
1125 | SetAdcMuxFor(GPIO_MUXSEL_LOPKD); | |
1126 | // Now set up the SSC to get the ADC samples that are now streaming at us. | |
1127 | FpgaSetupSsc(); | |
1128 | ||
1129 | LED_D_ON(); | |
1130 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
1131 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); | |
1132 | ||
1133 | // Give it a bit of time for the resonant antenna to settle. | |
1134 | // And for the tag to fully power up | |
1135 | SpinDelay(150); | |
1136 | ||
1137 | // Now start writting | |
1138 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
1139 | SpinDelayUs(START_GAP); | |
1140 | ||
1141 | // Opcode | |
1142 | T55xxWriteBit(1); | |
1143 | T55xxWriteBit(1); //Page 1 | |
1144 | ||
1145 | // Turn field on to read the response | |
1146 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
1147 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); | |
1148 | ||
1149 | // Now do the acquisition | |
1150 | i = 0; | |
1151 | for(;;) { | |
1152 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { | |
1153 | AT91C_BASE_SSC->SSC_THR = 0x43; | |
1154 | } | |
1155 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { | |
1156 | dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; | |
1157 | i++; | |
1158 | if (i >= m) break; | |
1159 | } | |
1160 | } | |
1161 | ||
1162 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
1163 | LED_D_OFF(); | |
1164 | DbpString("DONE!"); | |
54a942b0 | 1165 | } |
ec09b62d | 1166 | |
54a942b0 | 1167 | /*-------------- Cloning routines -----------*/ |
1168 | // Copy HID id to card and setup block 0 config | |
1169 | void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) | |
1170 | { | |
ae8e8a43 MHS |
1171 | int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format |
1172 | int last_block = 0; | |
1173 | ||
1174 | if (longFMT){ | |
1175 | // Ensure no more than 84 bits supplied | |
1176 | if (hi2>0xFFFFF) { | |
1177 | DbpString("Tags can only have 84 bits."); | |
1178 | return; | |
1179 | } | |
1180 | // Build the 6 data blocks for supplied 84bit ID | |
1181 | last_block = 6; | |
1182 | data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded) | |
1183 | for (int i=0;i<4;i++) { | |
1184 | if (hi2 & (1<<(19-i))) | |
1185 | data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10 | |
1186 | else | |
1187 | data1 |= (1<<((3-i)*2)); // 0 -> 01 | |
1188 | } | |
1189 | ||
1190 | data2 = 0; | |
1191 | for (int i=0;i<16;i++) { | |
1192 | if (hi2 & (1<<(15-i))) | |
1193 | data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10 | |
1194 | else | |
1195 | data2 |= (1<<((15-i)*2)); // 0 -> 01 | |
1196 | } | |
1197 | ||
1198 | data3 = 0; | |
1199 | for (int i=0;i<16;i++) { | |
1200 | if (hi & (1<<(31-i))) | |
1201 | data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10 | |
1202 | else | |
1203 | data3 |= (1<<((15-i)*2)); // 0 -> 01 | |
1204 | } | |
1205 | ||
1206 | data4 = 0; | |
1207 | for (int i=0;i<16;i++) { | |
1208 | if (hi & (1<<(15-i))) | |
1209 | data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10 | |
1210 | else | |
1211 | data4 |= (1<<((15-i)*2)); // 0 -> 01 | |
1212 | } | |
1213 | ||
1214 | data5 = 0; | |
1215 | for (int i=0;i<16;i++) { | |
1216 | if (lo & (1<<(31-i))) | |
1217 | data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10 | |
1218 | else | |
1219 | data5 |= (1<<((15-i)*2)); // 0 -> 01 | |
1220 | } | |
1221 | ||
1222 | data6 = 0; | |
1223 | for (int i=0;i<16;i++) { | |
1224 | if (lo & (1<<(15-i))) | |
1225 | data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10 | |
1226 | else | |
1227 | data6 |= (1<<((15-i)*2)); // 0 -> 01 | |
1228 | } | |
54a942b0 | 1229 | } |
ae8e8a43 MHS |
1230 | else { |
1231 | // Ensure no more than 44 bits supplied | |
1232 | if (hi>0xFFF) { | |
1233 | DbpString("Tags can only have 44 bits."); | |
1234 | return; | |
1235 | } | |
1236 | ||
1237 | // Build the 3 data blocks for supplied 44bit ID | |
1238 | last_block = 3; | |
1239 | ||
1240 | data1 = 0x1D000000; // load preamble | |
1241 | ||
1242 | for (int i=0;i<12;i++) { | |
1243 | if (hi & (1<<(11-i))) | |
1244 | data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10 | |
1245 | else | |
1246 | data1 |= (1<<((11-i)*2)); // 0 -> 01 | |
1247 | } | |
1248 | ||
1249 | data2 = 0; | |
1250 | for (int i=0;i<16;i++) { | |
1251 | if (lo & (1<<(31-i))) | |
1252 | data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10 | |
1253 | else | |
1254 | data2 |= (1<<((15-i)*2)); // 0 -> 01 | |
1255 | } | |
1256 | ||
1257 | data3 = 0; | |
1258 | for (int i=0;i<16;i++) { | |
1259 | if (lo & (1<<(15-i))) | |
1260 | data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10 | |
1261 | else | |
1262 | data3 |= (1<<((15-i)*2)); // 0 -> 01 | |
1263 | } | |
54a942b0 | 1264 | } |
ae8e8a43 MHS |
1265 | |
1266 | LED_D_ON(); | |
1267 | // Program the data blocks for supplied ID | |
1268 | // and the block 0 for HID format | |
1269 | T55xxWriteBlock(data1,1,0,0); | |
1270 | T55xxWriteBlock(data2,2,0,0); | |
1271 | T55xxWriteBlock(data3,3,0,0); | |
1272 | ||
1273 | if (longFMT) { // if long format there are 6 blocks | |
1274 | T55xxWriteBlock(data4,4,0,0); | |
1275 | T55xxWriteBlock(data5,5,0,0); | |
1276 | T55xxWriteBlock(data6,6,0,0); | |
54a942b0 | 1277 | } |
ae8e8a43 MHS |
1278 | |
1279 | // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long) | |
1280 | T55xxWriteBlock(T55x7_BITRATE_RF_50 | | |
1281 | T55x7_MODULATION_FSK2a | | |
1282 | last_block << T55x7_MAXBLOCK_SHIFT, | |
1283 | 0,0,0); | |
1284 | ||
1285 | LED_D_OFF(); | |
1286 | ||
1287 | DbpString("DONE!"); | |
2d4eae76 | 1288 | } |
ec09b62d | 1289 | |
a1f3bb12 | 1290 | void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT) |
1291 | { | |
ae8e8a43 MHS |
1292 | int data1=0, data2=0; //up to six blocks for long format |
1293 | ||
a1f3bb12 | 1294 | data1 = hi; // load preamble |
1295 | data2 = lo; | |
ba1a299c | 1296 | |
a1f3bb12 | 1297 | LED_D_ON(); |
1298 | // Program the data blocks for supplied ID | |
1299 | // and the block 0 for HID format | |
1300 | T55xxWriteBlock(data1,1,0,0); | |
1301 | T55xxWriteBlock(data2,2,0,0); | |
ae8e8a43 | 1302 | |
a1f3bb12 | 1303 | //Config Block |
1304 | T55xxWriteBlock(0x00147040,0,0,0); | |
1305 | LED_D_OFF(); | |
ae8e8a43 | 1306 | |
a1f3bb12 | 1307 | DbpString("DONE!"); |
1308 | } | |
1309 | ||
2d4eae76 | 1310 | // Define 9bit header for EM410x tags |
1311 | #define EM410X_HEADER 0x1FF | |
1312 | #define EM410X_ID_LENGTH 40 | |
ec09b62d | 1313 | |
2d4eae76 | 1314 | void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) |
1315 | { | |
ae8e8a43 MHS |
1316 | int i, id_bit; |
1317 | uint64_t id = EM410X_HEADER; | |
1318 | uint64_t rev_id = 0; // reversed ID | |
1319 | int c_parity[4]; // column parity | |
1320 | int r_parity = 0; // row parity | |
1321 | uint32_t clock = 0; | |
1322 | ||
1323 | // Reverse ID bits given as parameter (for simpler operations) | |
1324 | for (i = 0; i < EM410X_ID_LENGTH; ++i) { | |
1325 | if (i < 32) { | |
1326 | rev_id = (rev_id << 1) | (id_lo & 1); | |
1327 | id_lo >>= 1; | |
1328 | } else { | |
1329 | rev_id = (rev_id << 1) | (id_hi & 1); | |
1330 | id_hi >>= 1; | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | for (i = 0; i < EM410X_ID_LENGTH; ++i) { | |
1335 | id_bit = rev_id & 1; | |
1336 | ||
1337 | if (i % 4 == 0) { | |
1338 | // Don't write row parity bit at start of parsing | |
1339 | if (i) | |
1340 | id = (id << 1) | r_parity; | |
1341 | // Start counting parity for new row | |
1342 | r_parity = id_bit; | |
1343 | } else { | |
1344 | // Count row parity | |
1345 | r_parity ^= id_bit; | |
1346 | } | |
1347 | ||
1348 | // First elements in column? | |
1349 | if (i < 4) | |
1350 | // Fill out first elements | |
1351 | c_parity[i] = id_bit; | |
1352 | else | |
1353 | // Count column parity | |
1354 | c_parity[i % 4] ^= id_bit; | |
1355 | ||
1356 | // Insert ID bit | |
1357 | id = (id << 1) | id_bit; | |
1358 | rev_id >>= 1; | |
1359 | } | |
1360 | ||
1361 | // Insert parity bit of last row | |
1362 | id = (id << 1) | r_parity; | |
1363 | ||
1364 | // Fill out column parity at the end of tag | |
1365 | for (i = 0; i < 4; ++i) | |
1366 | id = (id << 1) | c_parity[i]; | |
1367 | ||
1368 | // Add stop bit | |
1369 | id <<= 1; | |
1370 | ||
1371 | Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555"); | |
1372 | LED_D_ON(); | |
1373 | ||
1374 | // Write EM410x ID | |
1375 | T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0); | |
1376 | T55xxWriteBlock((uint32_t)id, 2, 0, 0); | |
1377 | ||
1378 | // Config for EM410x (RF/64, Manchester, Maxblock=2) | |
1379 | if (card) { | |
1380 | // Clock rate is stored in bits 8-15 of the card value | |
1381 | clock = (card & 0xFF00) >> 8; | |
1382 | Dbprintf("Clock rate: %d", clock); | |
1383 | switch (clock) | |
1384 | { | |
1385 | case 32: | |
1386 | clock = T55x7_BITRATE_RF_32; | |
1387 | break; | |
1388 | case 16: | |
1389 | clock = T55x7_BITRATE_RF_16; | |
1390 | break; | |
1391 | case 0: | |
1392 | // A value of 0 is assumed to be 64 for backwards-compatibility | |
1393 | // Fall through... | |
1394 | case 64: | |
1395 | clock = T55x7_BITRATE_RF_64; | |
1396 | break; | |
1397 | default: | |
1398 | Dbprintf("Invalid clock rate: %d", clock); | |
1399 | return; | |
1400 | } | |
1401 | ||
1402 | // Writing configuration for T55x7 tag | |
1403 | T55xxWriteBlock(clock | | |
1404 | T55x7_MODULATION_MANCHESTER | | |
1405 | 2 << T55x7_MAXBLOCK_SHIFT, | |
1406 | 0, 0, 0); | |
1407 | } | |
1408 | else | |
1409 | // Writing configuration for T5555(Q5) tag | |
1410 | T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT | | |
1411 | T5555_MODULATION_MANCHESTER | | |
1412 | 2 << T5555_MAXBLOCK_SHIFT, | |
1413 | 0, 0, 0); | |
1414 | ||
1415 | LED_D_OFF(); | |
1416 | Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555", | |
1417 | (uint32_t)(id >> 32), (uint32_t)id); | |
2d4eae76 | 1418 | } |
2414f978 | 1419 | |
1420 | // Clone Indala 64-bit tag by UID to T55x7 | |
1421 | void CopyIndala64toT55x7(int hi, int lo) | |
1422 | { | |
2414f978 | 1423 | |
ae8e8a43 MHS |
1424 | //Program the 2 data blocks for supplied 64bit UID |
1425 | // and the block 0 for Indala64 format | |
1426 | T55xxWriteBlock(hi,1,0,0); | |
1427 | T55xxWriteBlock(lo,2,0,0); | |
1428 | //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2) | |
1429 | T55xxWriteBlock(T55x7_BITRATE_RF_32 | | |
1430 | T55x7_MODULATION_PSK1 | | |
1431 | 2 << T55x7_MAXBLOCK_SHIFT, | |
1432 | 0, 0, 0); | |
1433 | //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data) | |
1434 | // T5567WriteBlock(0x603E1042,0); | |
2414f978 | 1435 | |
ae8e8a43 | 1436 | DbpString("DONE!"); |
4118b74d | 1437 | |
ba1a299c | 1438 | } |
2414f978 | 1439 | |
1440 | void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7) | |
1441 | { | |
ae8e8a43 | 1442 | |
ae8e8a43 MHS |
1443 | //Program the 7 data blocks for supplied 224bit UID |
1444 | // and the block 0 for Indala224 format | |
1445 | T55xxWriteBlock(uid1,1,0,0); | |
1446 | T55xxWriteBlock(uid2,2,0,0); | |
1447 | T55xxWriteBlock(uid3,3,0,0); | |
1448 | T55xxWriteBlock(uid4,4,0,0); | |
1449 | T55xxWriteBlock(uid5,5,0,0); | |
1450 | T55xxWriteBlock(uid6,6,0,0); | |
1451 | T55xxWriteBlock(uid7,7,0,0); | |
1452 | //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7) | |
1453 | T55xxWriteBlock(T55x7_BITRATE_RF_32 | | |
1454 | T55x7_MODULATION_PSK1 | | |
1455 | 7 << T55x7_MAXBLOCK_SHIFT, | |
1456 | 0,0,0); | |
1457 | //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data) | |
1458 | // T5567WriteBlock(0x603E10E2,0); | |
1459 | ||
1460 | DbpString("DONE!"); | |
4118b74d | 1461 | |
2414f978 | 1462 | } |
54a942b0 | 1463 | |
1464 | ||
1465 | #define abs(x) ( ((x)<0) ? -(x) : (x) ) | |
1466 | #define max(x,y) ( x<y ? y:x) | |
1467 | ||
1468 | int DemodPCF7931(uint8_t **outBlocks) { | |
ae8e8a43 MHS |
1469 | uint8_t BitStream[256]; |
1470 | uint8_t Blocks[8][16]; | |
1471 | uint8_t *GraphBuffer = (uint8_t *)BigBuf; | |
1472 | int GraphTraceLen = sizeof(BigBuf); | |
1473 | int i, j, lastval, bitidx, half_switch; | |
1474 | int clock = 64; | |
1475 | int tolerance = clock / 8; | |
1476 | int pmc, block_done; | |
1477 | int lc, warnings = 0; | |
1478 | int num_blocks = 0; | |
1479 | int lmin=128, lmax=128; | |
1480 | uint8_t dir; | |
1481 | ||
1482 | AcquireRawAdcSamples125k(0); | |
1483 | ||
1484 | lmin = 64; | |
1485 | lmax = 192; | |
1486 | ||
1487 | i = 2; | |
1488 | ||
1489 | /* Find first local max/min */ | |
1490 | if(GraphBuffer[1] > GraphBuffer[0]) { | |
1491 | while(i < GraphTraceLen) { | |
1492 | if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax) | |
1493 | break; | |
1494 | i++; | |
1495 | } | |
1496 | dir = 0; | |
54a942b0 | 1497 | } |
ae8e8a43 MHS |
1498 | else { |
1499 | while(i < GraphTraceLen) { | |
1500 | if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin) | |
1501 | break; | |
1502 | i++; | |
1503 | } | |
1504 | dir = 1; | |
54a942b0 | 1505 | } |
ae8e8a43 MHS |
1506 | |
1507 | lastval = i++; | |
1508 | half_switch = 0; | |
1509 | pmc = 0; | |
1510 | block_done = 0; | |
1511 | ||
1512 | for (bitidx = 0; i < GraphTraceLen; i++) | |
1513 | { | |
1514 | if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin)) | |
1515 | { | |
1516 | lc = i - lastval; | |
1517 | lastval = i; | |
1518 | ||
1519 | // Switch depending on lc length: | |
1520 | // Tolerance is 1/8 of clock rate (arbitrary) | |
1521 | if (abs(lc-clock/4) < tolerance) { | |
1522 | // 16T0 | |
1523 | if((i - pmc) == lc) { /* 16T0 was previous one */ | |
1524 | /* It's a PMC ! */ | |
1525 | i += (128+127+16+32+33+16)-1; | |
1526 | lastval = i; | |
1527 | pmc = 0; | |
1528 | block_done = 1; | |
1529 | } | |
1530 | else { | |
1531 | pmc = i; | |
1532 | } | |
1533 | } else if (abs(lc-clock/2) < tolerance) { | |
1534 | // 32TO | |
1535 | if((i - pmc) == lc) { /* 16T0 was previous one */ | |
1536 | /* It's a PMC ! */ | |
1537 | i += (128+127+16+32+33)-1; | |
1538 | lastval = i; | |
1539 | pmc = 0; | |
1540 | block_done = 1; | |
1541 | } | |
1542 | else if(half_switch == 1) { | |
1543 | BitStream[bitidx++] = 0; | |
1544 | half_switch = 0; | |
1545 | } | |
1546 | else | |
1547 | half_switch++; | |
1548 | } else if (abs(lc-clock) < tolerance) { | |
1549 | // 64TO | |
1550 | BitStream[bitidx++] = 1; | |
1551 | } else { | |
1552 | // Error | |
1553 | warnings++; | |
1554 | if (warnings > 10) | |
1555 | { | |
1556 | Dbprintf("Error: too many detection errors, aborting."); | |
1557 | return 0; | |
1558 | } | |
1559 | } | |
1560 | ||
1561 | if(block_done == 1) { | |
1562 | if(bitidx == 128) { | |
1563 | for(j=0; j<16; j++) { | |
1564 | Blocks[num_blocks][j] = 128*BitStream[j*8+7]+ | |
1565 | 64*BitStream[j*8+6]+ | |
1566 | 32*BitStream[j*8+5]+ | |
1567 | 16*BitStream[j*8+4]+ | |
1568 | 8*BitStream[j*8+3]+ | |
1569 | 4*BitStream[j*8+2]+ | |
1570 | 2*BitStream[j*8+1]+ | |
1571 | BitStream[j*8]; | |
1572 | } | |
1573 | num_blocks++; | |
1574 | } | |
1575 | bitidx = 0; | |
1576 | block_done = 0; | |
1577 | half_switch = 0; | |
1578 | } | |
1579 | if(i < GraphTraceLen) | |
1580 | { | |
1581 | if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0; | |
1582 | else dir = 1; | |
1583 | } | |
1584 | } | |
1585 | if(bitidx==255) | |
1586 | bitidx=0; | |
1587 | warnings = 0; | |
1588 | if(num_blocks == 4) break; | |
1589 | } | |
1590 | memcpy(outBlocks, Blocks, 16*num_blocks); | |
1591 | return num_blocks; | |
54a942b0 | 1592 | } |
1593 | ||
1594 | int IsBlock0PCF7931(uint8_t *Block) { | |
ae8e8a43 MHS |
1595 | // Assume RFU means 0 :) |
1596 | if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled | |
1597 | return 1; | |
1598 | if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ? | |
1599 | return 1; | |
1600 | return 0; | |
54a942b0 | 1601 | } |
1602 | ||
1603 | int IsBlock1PCF7931(uint8_t *Block) { | |
ae8e8a43 MHS |
1604 | // Assume RFU means 0 :) |
1605 | if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0) | |
1606 | if((Block[14] & 0x7f) <= 9 && Block[15] <= 9) | |
1607 | return 1; | |
1608 | ||
1609 | return 0; | |
54a942b0 | 1610 | } |
d91a31f9 | 1611 | |
54a942b0 | 1612 | #define ALLOC 16 |
1613 | ||
1614 | void ReadPCF7931() { | |
ae8e8a43 MHS |
1615 | uint8_t Blocks[8][17]; |
1616 | uint8_t tmpBlocks[4][16]; | |
1617 | int i, j, ind, ind2, n; | |
1618 | int num_blocks = 0; | |
1619 | int max_blocks = 8; | |
1620 | int ident = 0; | |
1621 | int error = 0; | |
1622 | int tries = 0; | |
1623 | ||
1624 | memset(Blocks, 0, 8*17*sizeof(uint8_t)); | |
1625 | ||
1626 | do { | |
1627 | memset(tmpBlocks, 0, 4*16*sizeof(uint8_t)); | |
1628 | n = DemodPCF7931((uint8_t**)tmpBlocks); | |
1629 | if(!n) | |
1630 | error++; | |
1631 | if(error==10 && num_blocks == 0) { | |
1632 | Dbprintf("Error, no tag or bad tag"); | |
1633 | return; | |
54a942b0 | 1634 | } |
ae8e8a43 MHS |
1635 | else if (tries==20 || error==10) { |
1636 | Dbprintf("Error reading the tag"); | |
1637 | Dbprintf("Here is the partial content"); | |
1638 | goto end; | |
1639 | } | |
1640 | ||
1641 | for(i=0; i<n; i++) | |
1642 | Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", | |
1643 | tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7], | |
1644 | tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]); | |
1645 | if(!ident) { | |
1646 | for(i=0; i<n; i++) { | |
1647 | if(IsBlock0PCF7931(tmpBlocks[i])) { | |
1648 | // Found block 0 ? | |
1649 | if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) { | |
1650 | // Found block 1! | |
1651 | // \o/ | |
1652 | ident = 1; | |
1653 | memcpy(Blocks[0], tmpBlocks[i], 16); | |
1654 | Blocks[0][ALLOC] = 1; | |
1655 | memcpy(Blocks[1], tmpBlocks[i+1], 16); | |
1656 | Blocks[1][ALLOC] = 1; | |
1657 | max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1; | |
1658 | // Debug print | |
1659 | Dbprintf("(dbg) Max blocks: %d", max_blocks); | |
1660 | num_blocks = 2; | |
1661 | // Handle following blocks | |
1662 | for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) { | |
1663 | if(j==n) j=0; | |
1664 | if(j==i) break; | |
1665 | memcpy(Blocks[ind2], tmpBlocks[j], 16); | |
1666 | Blocks[ind2][ALLOC] = 1; | |
1667 | } | |
1668 | break; | |
1669 | } | |
54a942b0 | 1670 | } |
ae8e8a43 MHS |
1671 | } |
1672 | } | |
1673 | else { | |
1674 | for(i=0; i<n; i++) { // Look for identical block in known blocks | |
1675 | if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00 | |
1676 | for(j=0; j<max_blocks; j++) { | |
1677 | if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) { | |
1678 | // Found an identical block | |
1679 | for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) { | |
1680 | if(ind2 < 0) | |
1681 | ind2 = max_blocks; | |
1682 | if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found | |
1683 | // Dbprintf("Tmp %d -> Block %d", ind, ind2); | |
1684 | memcpy(Blocks[ind2], tmpBlocks[ind], 16); | |
1685 | Blocks[ind2][ALLOC] = 1; | |
1686 | num_blocks++; | |
1687 | if(num_blocks == max_blocks) goto end; | |
1688 | } | |
1689 | } | |
1690 | for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) { | |
1691 | if(ind2 > max_blocks) | |
1692 | ind2 = 0; | |
1693 | if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found | |
1694 | // Dbprintf("Tmp %d -> Block %d", ind, ind2); | |
1695 | memcpy(Blocks[ind2], tmpBlocks[ind], 16); | |
1696 | Blocks[ind2][ALLOC] = 1; | |
1697 | num_blocks++; | |
1698 | if(num_blocks == max_blocks) goto end; | |
1699 | } | |
1700 | } | |
1701 | } | |
1702 | } | |
54a942b0 | 1703 | } |
54a942b0 | 1704 | } |
54a942b0 | 1705 | } |
ae8e8a43 MHS |
1706 | tries++; |
1707 | if (BUTTON_PRESS()) return; | |
1708 | } while (num_blocks != max_blocks); | |
54a942b0 | 1709 | end: |
ae8e8a43 MHS |
1710 | Dbprintf("-----------------------------------------"); |
1711 | Dbprintf("Memory content:"); | |
1712 | Dbprintf("-----------------------------------------"); | |
1713 | for(i=0; i<max_blocks; i++) { | |
1714 | if(Blocks[i][ALLOC]==1) | |
1715 | Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", | |
1716 | Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7], | |
1717 | Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]); | |
1718 | else | |
1719 | Dbprintf("<missing block %d>", i); | |
1720 | } | |
1721 | Dbprintf("-----------------------------------------"); | |
1722 | ||
1723 | return ; | |
54a942b0 | 1724 | } |
1725 | ||
1726 | ||
1727 | //----------------------------------- | |
1728 | // EM4469 / EM4305 routines | |
1729 | //----------------------------------- | |
1730 | #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored | |
1731 | #define FWD_CMD_WRITE 0xA | |
1732 | #define FWD_CMD_READ 0x9 | |
1733 | #define FWD_CMD_DISABLE 0x5 | |
1734 | ||
1735 | ||
1736 | uint8_t forwardLink_data[64]; //array of forwarded bits | |
1737 | uint8_t * forward_ptr; //ptr for forward message preparation | |
1738 | uint8_t fwd_bit_sz; //forwardlink bit counter | |
1739 | uint8_t * fwd_write_ptr; //forwardlink bit pointer | |
1740 | ||
1741 | //==================================================================== | |
1742 | // prepares command bits | |
1743 | // see EM4469 spec | |
1744 | //==================================================================== | |
1745 | //-------------------------------------------------------------------- | |
1746 | uint8_t Prepare_Cmd( uint8_t cmd ) { | |
ae8e8a43 MHS |
1747 | //-------------------------------------------------------------------- |
1748 | ||
1749 | *forward_ptr++ = 0; //start bit | |
1750 | *forward_ptr++ = 0; //second pause for 4050 code | |
1751 | ||
1752 | *forward_ptr++ = cmd; | |
1753 | cmd >>= 1; | |
1754 | *forward_ptr++ = cmd; | |
1755 | cmd >>= 1; | |
1756 | *forward_ptr++ = cmd; | |
1757 | cmd >>= 1; | |
1758 | *forward_ptr++ = cmd; | |
1759 | ||
1760 | return 6; //return number of emited bits | |
54a942b0 | 1761 | } |
1762 | ||
1763 | //==================================================================== | |
1764 | // prepares address bits | |
1765 | // see EM4469 spec | |
1766 | //==================================================================== | |
1767 | ||
1768 | //-------------------------------------------------------------------- | |
1769 | uint8_t Prepare_Addr( uint8_t addr ) { | |
ae8e8a43 MHS |
1770 | //-------------------------------------------------------------------- |
1771 | ||
1772 | register uint8_t line_parity; | |
1773 | ||
1774 | uint8_t i; | |
1775 | line_parity = 0; | |
1776 | for(i=0;i<6;i++) { | |
1777 | *forward_ptr++ = addr; | |
1778 | line_parity ^= addr; | |
1779 | addr >>= 1; | |
1780 | } | |
1781 | ||
1782 | *forward_ptr++ = (line_parity & 1); | |
1783 | ||
1784 | return 7; //return number of emited bits | |
54a942b0 | 1785 | } |
1786 | ||
1787 | //==================================================================== | |
1788 | // prepares data bits intreleaved with parity bits | |
1789 | // see EM4469 spec | |
1790 | //==================================================================== | |
1791 | ||
1792 | //-------------------------------------------------------------------- | |
1793 | uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) { | |
ae8e8a43 MHS |
1794 | //-------------------------------------------------------------------- |
1795 | ||
1796 | register uint8_t line_parity; | |
1797 | register uint8_t column_parity; | |
1798 | register uint8_t i, j; | |
1799 | register uint16_t data; | |
1800 | ||
1801 | data = data_low; | |
1802 | column_parity = 0; | |
1803 | ||
1804 | for(i=0; i<4; i++) { | |
1805 | line_parity = 0; | |
1806 | for(j=0; j<8; j++) { | |
1807 | line_parity ^= data; | |
1808 | column_parity ^= (data & 1) << j; | |
1809 | *forward_ptr++ = data; | |
1810 | data >>= 1; | |
1811 | } | |
1812 | *forward_ptr++ = line_parity; | |
1813 | if(i == 1) | |
1814 | data = data_hi; | |
1815 | } | |
1816 | ||
54a942b0 | 1817 | for(j=0; j<8; j++) { |
ae8e8a43 MHS |
1818 | *forward_ptr++ = column_parity; |
1819 | column_parity >>= 1; | |
54a942b0 | 1820 | } |
ae8e8a43 MHS |
1821 | *forward_ptr = 0; |
1822 | ||
1823 | return 45; //return number of emited bits | |
54a942b0 | 1824 | } |
1825 | ||
1826 | //==================================================================== | |
1827 | // Forward Link send function | |
1828 | // Requires: forwarLink_data filled with valid bits (1 bit per byte) | |
1829 | // fwd_bit_count set with number of bits to be sent | |
1830 | //==================================================================== | |
1831 | void SendForward(uint8_t fwd_bit_count) { | |
ae8e8a43 MHS |
1832 | |
1833 | fwd_write_ptr = forwardLink_data; | |
1834 | fwd_bit_sz = fwd_bit_count; | |
1835 | ||
1836 | LED_D_ON(); | |
1837 | ||
1838 | //Field on | |
1839 | FpgaDownloadAndGo(FPGA_BITSTREAM_LF); | |
1840 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
1841 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); | |
1842 | ||
1843 | // Give it a bit of time for the resonant antenna to settle. | |
1844 | // And for the tag to fully power up | |
1845 | SpinDelay(150); | |
1846 | ||
1847 | // force 1st mod pulse (start gap must be longer for 4305) | |
1848 | fwd_bit_sz--; //prepare next bit modulation | |
1849 | fwd_write_ptr++; | |
1850 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
1851 | SpinDelayUs(55*8); //55 cycles off (8us each)for 4305 | |
1852 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
1853 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on | |
1854 | SpinDelayUs(16*8); //16 cycles on (8us each) | |
1855 | ||
1856 | // now start writting | |
1857 | while(fwd_bit_sz-- > 0) { //prepare next bit modulation | |
1858 | if(((*fwd_write_ptr++) & 1) == 1) | |
1859 | SpinDelayUs(32*8); //32 cycles at 125Khz (8us each) | |
1860 | else { | |
1861 | //These timings work for 4469/4269/4305 (with the 55*8 above) | |
1862 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
1863 | SpinDelayUs(23*8); //16-4 cycles off (8us each) | |
1864 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz | |
1865 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on | |
1866 | SpinDelayUs(9*8); //16 cycles on (8us each) | |
1867 | } | |
54a942b0 | 1868 | } |
54a942b0 | 1869 | } |
1870 | ||
1871 | void EM4xLogin(uint32_t Password) { | |
ae8e8a43 MHS |
1872 | |
1873 | uint8_t fwd_bit_count; | |
1874 | ||
1875 | forward_ptr = forwardLink_data; | |
1876 | fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN ); | |
1877 | fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 ); | |
1878 | ||
1879 | SendForward(fwd_bit_count); | |
1880 | ||
1881 | //Wait for command to complete | |
1882 | SpinDelay(20); | |
1883 | ||
54a942b0 | 1884 | } |
1885 | ||
1886 | void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { | |
ae8e8a43 MHS |
1887 | |
1888 | uint8_t fwd_bit_count; | |
1889 | uint8_t *dest = (uint8_t *)BigBuf; | |
1890 | int m=0, i=0; | |
1891 | ||
1892 | //If password mode do login | |
1893 | if (PwdMode == 1) EM4xLogin(Pwd); | |
1894 | ||
1895 | forward_ptr = forwardLink_data; | |
1896 | fwd_bit_count = Prepare_Cmd( FWD_CMD_READ ); | |
1897 | fwd_bit_count += Prepare_Addr( Address ); | |
1898 | ||
1899 | m = sizeof(BigBuf); | |
1900 | // Clear destination buffer before sending the command | |
1901 | memset(dest, 128, m); | |
1902 | // Connect the A/D to the peak-detected low-frequency path. | |
1903 | SetAdcMuxFor(GPIO_MUXSEL_LOPKD); | |
1904 | // Now set up the SSC to get the ADC samples that are now streaming at us. | |
1905 | FpgaSetupSsc(); | |
1906 | ||
1907 | SendForward(fwd_bit_count); | |
1908 | ||
1909 | // Now do the acquisition | |
1910 | i = 0; | |
1911 | for(;;) { | |
1912 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { | |
1913 | AT91C_BASE_SSC->SSC_THR = 0x43; | |
1914 | } | |
1915 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { | |
1916 | dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; | |
1917 | i++; | |
1918 | if (i >= m) break; | |
1919 | } | |
54a942b0 | 1920 | } |
ae8e8a43 MHS |
1921 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off |
1922 | LED_D_OFF(); | |
54a942b0 | 1923 | } |
1924 | ||
1925 | void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { | |
ae8e8a43 MHS |
1926 | |
1927 | uint8_t fwd_bit_count; | |
1928 | ||
1929 | //If password mode do login | |
1930 | if (PwdMode == 1) EM4xLogin(Pwd); | |
1931 | ||
1932 | forward_ptr = forwardLink_data; | |
1933 | fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE ); | |
1934 | fwd_bit_count += Prepare_Addr( Address ); | |
1935 | fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 ); | |
1936 | ||
1937 | SendForward(fwd_bit_count); | |
1938 | ||
1939 | //Wait for write to complete | |
1940 | SpinDelay(20); | |
1941 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off | |
1942 | LED_D_OFF(); | |
54a942b0 | 1943 | } |