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ec1bef8e | 1 | /* Name: usbdrvasm18.inc |
2 | * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers | |
3 | * Author: Lukas Schrittwieser (based on 20 MHz usbdrvasm20.inc by Jeroen Benschop) | |
4 | * Creation Date: 2009-01-20 | |
5 | * Tabsize: 4 | |
6 | * Copyright: (c) 2008 by Lukas Schrittwieser and OBJECTIVE DEVELOPMENT Software GmbH | |
7 | * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) | |
8 | * Revision: $Id: usbdrvasm18-crc.inc 740 2009-04-13 18:23:31Z cs $ | |
9 | */ | |
10 | ||
11 | /* Do not link this file! Link usbdrvasm.S instead, which includes the | |
12 | * appropriate implementation! | |
13 | */ | |
14 | ||
15 | /* | |
16 | General Description: | |
17 | This file is the 18 MHz version of the asssembler part of the USB driver. It | |
18 | requires a 18 MHz crystal (not a ceramic resonator and not a calibrated RC | |
19 | oscillator). | |
20 | ||
21 | See usbdrv.h for a description of the entire driver. | |
22 | ||
23 | Since almost all of this code is timing critical, don't change unless you | |
24 | really know what you are doing! Many parts require not only a maximum number | |
25 | of CPU cycles, but even an exact number of cycles! | |
26 | */ | |
27 | ||
28 | ||
29 | ;max stack usage: [ret(2), YL, SREG, YH, [sofError], bitcnt(x5), shift, x1, x2, x3, x4, cnt, ZL, ZH] = 14 bytes | |
30 | ;nominal frequency: 18 MHz -> 12 cycles per bit | |
31 | ; Numbers in brackets are clocks counted from center of last sync bit | |
32 | ; when instruction starts | |
33 | ;register use in receive loop to receive the data bytes: | |
34 | ; shift assembles the byte currently being received | |
35 | ; x1 holds the D+ and D- line state | |
36 | ; x2 holds the previous line state | |
37 | ; cnt holds the number of bytes left in the receive buffer | |
38 | ; x3 holds the higher crc byte (see algorithm below) | |
39 | ; x4 is used as temporary register for the crc algorithm | |
40 | ; x5 is used for unstuffing: when unstuffing the last received bit is inverted in shift (to prevent further | |
41 | ; unstuffing calls. In the same time the corresponding bit in x5 is cleared to mark the bit as beening iverted | |
42 | ; zl lower crc value and crc table index | |
43 | ; zh used for crc table accesses | |
44 | ||
45 | ;-------------------------------------------------------------------------------------------------------------- | |
46 | ; CRC mods: | |
47 | ; table driven crc checker, Z points to table in prog space | |
48 | ; ZL is the lower crc byte, x3 is the higher crc byte | |
49 | ; x4 is used as temp register to store different results | |
50 | ; the initialization of the crc register is not 0xFFFF but 0xFE54. This is because during the receipt of the | |
51 | ; first data byte an virtual zero data byte is added to the crc register, this results in the correct initial | |
52 | ; value of 0xFFFF at beginning of the second data byte before the first data byte is added to the crc. | |
53 | ; The magic number 0xFE54 results form the crc table: At tabH[0x54] = 0xFF = crcH (required) and | |
54 | ; tabL[0x54] = 0x01 -> crcL = 0x01 xor 0xFE = 0xFF | |
55 | ; bitcnt is renamed to x5 and is used for unstuffing purposes, the unstuffing works like in the 12MHz version | |
56 | ;-------------------------------------------------------------------------------------------------------------- | |
57 | ; CRC algorithm: | |
58 | ; The crc register is formed by x3 (higher byte) and ZL (lower byte). The algorithm uses a 'reversed' form | |
59 | ; i.e. that it takes the least significant bit first and shifts to the right. So in fact the highest order | |
60 | ; bit seen from the polynomial devision point of view is the lsb of ZL. (If this sounds strange to you i | |
61 | ; propose a research on CRC :-) ) | |
62 | ; Each data byte received is xored to ZL, the lower crc byte. This byte now builds the crc | |
63 | ; table index. Next the new high byte is loaded from the table and stored in x4 until we have space in x3 | |
64 | ; (its destination). | |
65 | ; Afterwards the lower table is loaded from the table and stored in ZL (the old index is overwritten as | |
66 | ; we don't need it anymore. In fact this is a right shift by 8 bits.) Now the old crc high value is xored | |
67 | ; to ZL, this is the second shift of the old crc value. Now x4 (the temp reg) is moved to x3 and the crc | |
68 | ; calculation is done. | |
69 | ; Prior to the first byte the two CRC register have to be initialized to 0xFFFF (as defined in usb spec) | |
70 | ; however the crc engine also runs during the receipt of the first byte, therefore x3 and zl are initialized | |
71 | ; to a magic number which results in a crc value of 0xFFFF after the first complete byte. | |
72 | ; | |
73 | ; This algorithm is split into the extra cycles of the different bits: | |
74 | ; bit7: XOR the received byte to ZL | |
75 | ; bit5: load the new high byte to x4 | |
76 | ; bit6: load the lower xor byte from the table, xor zl and x3, store result in zl (=the new crc low value) | |
77 | ; move x4 (the new high byte) to x3, the crc value is ready | |
78 | ; | |
79 | ||
80 | ||
81 | macro POP_STANDARD ; 18 cycles | |
82 | pop ZH | |
83 | pop ZL | |
84 | pop cnt | |
85 | pop x5 | |
86 | pop x3 | |
87 | pop x2 | |
88 | pop x1 | |
89 | pop shift | |
90 | pop x4 | |
91 | endm | |
92 | macro POP_RETI ; 7 cycles | |
93 | pop YH | |
94 | pop YL | |
95 | out SREG, YL | |
96 | pop YL | |
97 | endm | |
98 | ||
99 | macro CRC_CLEANUP_AND_CHECK | |
100 | ; the last byte has already been xored with the lower crc byte, we have to do the table lookup and xor | |
101 | ; x3 is the higher crc byte, zl the lower one | |
102 | ldi ZH, hi8(usbCrcTableHigh);[+1] get the new high byte from the table | |
103 | lpm x2, Z ;[+2][+3][+4] | |
104 | ldi ZH, hi8(usbCrcTableLow);[+5] get the new low xor byte from the table | |
105 | lpm ZL, Z ;[+6][+7][+8] | |
106 | eor ZL, x3 ;[+7] xor the old high byte with the value from the table, x2:ZL now holds the crc value | |
107 | cpi ZL, 0x01 ;[+8] if the crc is ok we have a fixed remainder value of 0xb001 in x2:ZL (see usb spec) | |
108 | brne ignorePacket ;[+9] detected a crc fault -> paket is ignored and retransmitted by the host | |
109 | cpi x2, 0xb0 ;[+10] | |
110 | brne ignorePacket ;[+11] detected a crc fault -> paket is ignored and retransmitted by the host | |
111 | endm | |
112 | ||
113 | ||
114 | USB_INTR_VECTOR: | |
115 | ;order of registers pushed: YL, SREG, YH, [sofError], x4, shift, x1, x2, x3, x5, cnt, ZL, ZH | |
116 | push YL ;[-28] push only what is necessary to sync with edge ASAP | |
117 | in YL, SREG ;[-26] | |
118 | push YL ;[-25] | |
119 | push YH ;[-23] | |
120 | ;---------------------------------------------------------------------------- | |
121 | ; Synchronize with sync pattern: | |
122 | ;---------------------------------------------------------------------------- | |
123 | ;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] | |
124 | ;sync up with J to K edge during sync pattern -- use fastest possible loops | |
125 | ;The first part waits at most 1 bit long since we must be in sync pattern. | |
126 | ;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to | |
127 | ;waitForJ, ensure that this prerequisite is met. | |
128 | waitForJ: | |
129 | inc YL | |
130 | sbis USBIN, USBMINUS | |
131 | brne waitForJ ; just make sure we have ANY timeout | |
132 | waitForK: | |
133 | ;The following code results in a sampling window of < 1/4 bit which meets the spec. | |
134 | sbis USBIN, USBMINUS ;[-17] | |
135 | rjmp foundK ;[-16] | |
136 | sbis USBIN, USBMINUS | |
137 | rjmp foundK | |
138 | sbis USBIN, USBMINUS | |
139 | rjmp foundK | |
140 | sbis USBIN, USBMINUS | |
141 | rjmp foundK | |
142 | sbis USBIN, USBMINUS | |
143 | rjmp foundK | |
144 | sbis USBIN, USBMINUS | |
145 | rjmp foundK | |
146 | sbis USBIN, USBMINUS | |
147 | rjmp foundK | |
148 | sbis USBIN, USBMINUS | |
149 | rjmp foundK | |
150 | sbis USBIN, USBMINUS | |
151 | rjmp foundK | |
152 | #if USB_COUNT_SOF | |
153 | lds YL, usbSofCount | |
154 | inc YL | |
155 | sts usbSofCount, YL | |
156 | #endif /* USB_COUNT_SOF */ | |
157 | #ifdef USB_SOF_HOOK | |
158 | USB_SOF_HOOK | |
159 | #endif | |
160 | rjmp sofError | |
161 | foundK: ;[-15] | |
162 | ;{3, 5} after falling D- edge, average delay: 4 cycles | |
163 | ;bit0 should be at 30 (2.5 bits) for center sampling. Currently at 4 so 26 cylces till bit 0 sample | |
164 | ;use 1 bit time for setup purposes, then sample again. Numbers in brackets | |
165 | ;are cycles from center of first sync (double K) bit after the instruction | |
166 | push x4 ;[-14] | |
167 | ; [---] ;[-13] | |
168 | lds YL, usbInputBufOffset;[-12] used to toggle the two usb receive buffers | |
169 | ; [---] ;[-11] | |
170 | clr YH ;[-10] | |
171 | subi YL, lo8(-(usbRxBuf));[-9] [rx loop init] | |
172 | sbci YH, hi8(-(usbRxBuf));[-8] [rx loop init] | |
173 | push shift ;[-7] | |
174 | ; [---] ;[-6] | |
175 | ldi shift, 0x80 ;[-5] the last bit is the end of byte marker for the pid receiver loop | |
176 | clc ;[-4] the carry has to be clear for receipt of pid bit 0 | |
177 | sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early) | |
178 | rjmp haveTwoBitsK ;[-2] | |
179 | pop shift ;[-1] undo the push from before | |
180 | pop x4 ;[1] | |
181 | rjmp waitForK ;[3] this was not the end of sync, retry | |
182 | ; The entire loop from waitForK until rjmp waitForK above must not exceed two | |
183 | ; bit times (= 24 cycles). | |
184 | ||
185 | ;---------------------------------------------------------------------------- | |
186 | ; push more registers and initialize values while we sample the first bits: | |
187 | ;---------------------------------------------------------------------------- | |
188 | haveTwoBitsK: | |
189 | push x1 ;[0] | |
190 | push x2 ;[2] | |
191 | push x3 ;[4] crc high byte | |
192 | ldi x2, 1<<USBPLUS ;[6] [rx loop init] current line state is K state. D+=="1", D-=="0" | |
193 | push x5 ;[7] | |
194 | push cnt ;[9] | |
195 | ldi cnt, USB_BUFSIZE ;[11] | |
196 | ||
197 | ||
198 | ;-------------------------------------------------------------------------------------------------------------- | |
199 | ; receives the pid byte | |
200 | ; there is no real unstuffing algorithm implemented here as a stuffing bit is impossible in the pid byte. | |
201 | ; That's because the last four bits of the byte are the inverted of the first four bits. If we detect a | |
202 | ; unstuffing condition something went wrong and abort | |
203 | ; shift has to be initialized to 0x80 | |
204 | ;-------------------------------------------------------------------------------------------------------------- | |
205 | ||
206 | ; pid bit 0 - used for even more register saving (we need the z pointer) | |
207 | in x1, USBIN ;[0] sample line state | |
208 | andi x1, USBMASK ;[1] filter only D+ and D- bits | |
209 | eor x2, x1 ;[2] generate inverted of actual bit | |
210 | sbrc x2, USBMINUS ;[3] if the bit is set we received a zero | |
211 | sec ;[4] | |
212 | ror shift ;[5] we perform no unstuffing check here as this is the first bit | |
213 | mov x2, x1 ;[6] | |
214 | push ZL ;[7] | |
215 | ;[8] | |
216 | push ZH ;[9] | |
217 | ;[10] | |
218 | ldi x3, 0xFE ;[11] x3 is the high order crc value | |
219 | ||
220 | ||
221 | bitloopPid: | |
222 | in x1, USBIN ;[0] sample line state | |
223 | andi x1, USBMASK ;[1] filter only D+ and D- bits | |
224 | breq nse0 ;[2] both lines are low so handle se0 | |
225 | eor x2, x1 ;[3] generate inverted of actual bit | |
226 | sbrc x2, USBMINUS ;[4] set the carry if we received a zero | |
227 | sec ;[5] | |
228 | ror shift ;[6] | |
229 | ldi ZL, 0x54 ;[7] ZL is the low order crc value | |
230 | ser x4 ;[8] the is no bit stuffing check here as the pid bit can't be stuffed. if so | |
231 | ; some error occured. In this case the paket is discarded later on anyway. | |
232 | mov x2, x1 ;[9] prepare for the next cycle | |
233 | brcc bitloopPid ;[10] while 0s drop out of shift we get the next bit | |
234 | eor x4, shift ;[11] invert all bits in shift and store result in x4 | |
235 | ||
236 | ;-------------------------------------------------------------------------------------------------------------- | |
237 | ; receives data bytes and calculates the crc | |
238 | ; the last USBIN state has to be in x2 | |
239 | ; this is only the first half, due to branch distanc limitations the second half of the loop is near the end | |
240 | ; of this asm file | |
241 | ;-------------------------------------------------------------------------------------------------------------- | |
242 | ||
243 | rxDataStart: | |
244 | in x1, USBIN ;[0] sample line state (note: a se0 check is not useful due to bit dribbling) | |
245 | ser x5 ;[1] prepare the unstuff marker register | |
246 | eor x2, x1 ;[2] generates the inverted of the actual bit | |
247 | bst x2, USBMINUS ;[3] copy the bit from x2 | |
248 | bld shift, 0 ;[4] and store it in shift | |
249 | mov x2, shift ;[5] make a copy of shift for unstuffing check | |
250 | andi x2, 0xF9 ;[6] mask the last six bits, if we got six zeros (which are six ones in fact) | |
251 | breq unstuff0 ;[7] then Z is set now and we branch to the unstuffing handler | |
252 | didunstuff0: | |
253 | subi cnt, 1 ;[8] cannot use dec because it doesn't affect the carry flag | |
254 | brcs nOverflow ;[9] Too many bytes received. Ignore packet | |
255 | st Y+, x4 ;[10] store the last received byte | |
256 | ;[11] st needs two cycles | |
257 | ||
258 | ; bit1 | |
259 | in x2, USBIN ;[0] sample line state | |
260 | andi x1, USBMASK ;[1] check for se0 during bit 0 | |
261 | breq nse0 ;[2] | |
262 | andi x2, USBMASK ;[3] check se0 during bit 1 | |
263 | breq nse0 ;[4] | |
264 | eor x1, x2 ;[5] | |
265 | bst x1, USBMINUS ;[6] | |
266 | bld shift, 1 ;[7] | |
267 | mov x1, shift ;[8] | |
268 | andi x1, 0xF3 ;[9] | |
269 | breq unstuff1 ;[10] | |
270 | didunstuff1: | |
271 | nop ;[11] | |
272 | ||
273 | ; bit2 | |
274 | in x1, USBIN ;[0] sample line state | |
275 | andi x1, USBMASK ;[1] check for se0 (as there is nothing else to do here | |
276 | breq nOverflow ;[2] | |
277 | eor x2, x1 ;[3] generates the inverted of the actual bit | |
278 | bst x2, USBMINUS ;[4] | |
279 | bld shift, 2 ;[5] store the bit | |
280 | mov x2, shift ;[6] | |
281 | andi x2, 0xE7 ;[7] if we have six zeros here (which means six 1 in the stream) | |
282 | breq unstuff2 ;[8] the next bit is a stuffing bit | |
283 | didunstuff2: | |
284 | nop2 ;[9] | |
285 | ;[10] | |
286 | nop ;[11] | |
287 | ||
288 | ; bit3 | |
289 | in x2, USBIN ;[0] sample line state | |
290 | andi x2, USBMASK ;[1] check for se0 | |
291 | breq nOverflow ;[2] | |
292 | eor x1, x2 ;[3] | |
293 | bst x1, USBMINUS ;[4] | |
294 | bld shift, 3 ;[5] | |
295 | mov x1, shift ;[6] | |
296 | andi x1, 0xCF ;[7] | |
297 | breq unstuff3 ;[8] | |
298 | didunstuff3: | |
299 | nop ;[9] | |
300 | rjmp rxDataBit4 ;[10] | |
301 | ;[11] | |
302 | ||
303 | ; the avr branch instructions allow an offset of +63 insturction only, so we need this | |
304 | ; 'local copy' of se0 | |
305 | nse0: | |
306 | rjmp se0 ;[4] | |
307 | ;[5] | |
308 | ; the same same as for se0 is needed for overflow and StuffErr | |
309 | nOverflow: | |
310 | stuffErr: | |
311 | rjmp overflow | |
312 | ||
313 | ||
314 | unstuff0: ;[8] this is the branch delay of breq unstuffX | |
315 | andi x1, USBMASK ;[9] do an se0 check here (if the last crc byte ends with 5 one's we might end up here | |
316 | breq didunstuff0 ;[10] event tough the message is complete -> jump back and store the byte | |
317 | ori shift, 0x01 ;[11] invert the last received bit to prevent furhter unstuffing | |
318 | in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors | |
319 | andi x5, 0xFE ;[1] mark this bit as inverted (will be corrected before storing shift) | |
320 | eor x1, x2 ;[2] x1 and x2 have to be different because the stuff bit is always a zero | |
321 | andi x1, USBMASK ;[3] mask the interesting bits | |
322 | breq stuffErr ;[4] if the stuff bit is a 1-bit something went wrong | |
323 | mov x1, x2 ;[5] the next bit expects the last state to be in x1 | |
324 | rjmp didunstuff0 ;[6] | |
325 | ;[7] jump delay of rjmp didunstuffX | |
326 | ||
327 | unstuff1: ;[11] this is the jump delay of breq unstuffX | |
328 | in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors | |
329 | ori shift, 0x02 ;[1] invert the last received bit to prevent furhter unstuffing | |
330 | andi x5, 0xFD ;[2] mark this bit as inverted (will be corrected before storing shift) | |
331 | eor x2, x1 ;[3] x1 and x2 have to be different because the stuff bit is always a zero | |
332 | andi x2, USBMASK ;[4] mask the interesting bits | |
333 | breq stuffErr ;[5] if the stuff bit is a 1-bit something went wrong | |
334 | mov x2, x1 ;[6] the next bit expects the last state to be in x2 | |
335 | nop2 ;[7] | |
336 | ;[8] | |
337 | rjmp didunstuff1 ;[9] | |
338 | ;[10] jump delay of rjmp didunstuffX | |
339 | ||
340 | unstuff2: ;[9] this is the jump delay of breq unstuffX | |
341 | ori shift, 0x04 ;[10] invert the last received bit to prevent furhter unstuffing | |
342 | andi x5, 0xFB ;[11] mark this bit as inverted (will be corrected before storing shift) | |
343 | in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors | |
344 | eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero | |
345 | andi x1, USBMASK ;[2] mask the interesting bits | |
346 | breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong | |
347 | mov x1, x2 ;[4] the next bit expects the last state to be in x1 | |
348 | nop2 ;[5] | |
349 | ;[6] | |
350 | rjmp didunstuff2 ;[7] | |
351 | ;[8] jump delay of rjmp didunstuffX | |
352 | ||
353 | unstuff3: ;[9] this is the jump delay of breq unstuffX | |
354 | ori shift, 0x08 ;[10] invert the last received bit to prevent furhter unstuffing | |
355 | andi x5, 0xF7 ;[11] mark this bit as inverted (will be corrected before storing shift) | |
356 | in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors | |
357 | eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero | |
358 | andi x2, USBMASK ;[2] mask the interesting bits | |
359 | breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong | |
360 | mov x2, x1 ;[4] the next bit expects the last state to be in x2 | |
361 | nop2 ;[5] | |
362 | ;[6] | |
363 | rjmp didunstuff3 ;[7] | |
364 | ;[8] jump delay of rjmp didunstuffX | |
365 | ||
366 | ||
367 | ||
368 | ; the include has to be here due to branch distance restirctions | |
369 | #define __USE_CRC__ | |
370 | #include "asmcommon.inc" | |
371 | ||
372 | ||
373 | ||
374 | ; USB spec says: | |
375 | ; idle = J | |
376 | ; J = (D+ = 0), (D- = 1) | |
377 | ; K = (D+ = 1), (D- = 0) | |
378 | ; Spec allows 7.5 bit times from EOP to SOP for replies | |
379 | ; 7.5 bit times is 90 cycles. ...there is plenty of time | |
380 | ||
381 | ||
382 | sendNakAndReti: | |
383 | ldi x3, USBPID_NAK ;[-18] | |
384 | rjmp sendX3AndReti ;[-17] | |
385 | sendAckAndReti: | |
386 | ldi cnt, USBPID_ACK ;[-17] | |
387 | sendCntAndReti: | |
388 | mov x3, cnt ;[-16] | |
389 | sendX3AndReti: | |
390 | ldi YL, 20 ;[-15] x3==r20 address is 20 | |
391 | ldi YH, 0 ;[-14] | |
392 | ldi cnt, 2 ;[-13] | |
393 | ; rjmp usbSendAndReti fallthrough | |
394 | ||
395 | ;usbSend: | |
396 | ;pointer to data in 'Y' | |
397 | ;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] | |
398 | ;uses: x1...x4, btcnt, shift, cnt, Y | |
399 | ;Numbers in brackets are time since first bit of sync pattern is sent | |
400 | ||
401 | usbSendAndReti: ; 12 cycles until SOP | |
402 | in x2, USBDDR ;[-12] | |
403 | ori x2, USBMASK ;[-11] | |
404 | sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) | |
405 | in x1, USBOUT ;[-8] port mirror for tx loop | |
406 | out USBDDR, x2 ;[-6] <- acquire bus | |
407 | ldi x2, 0 ;[-6] init x2 (bitstuff history) because sync starts with 0 | |
408 | ldi x4, USBMASK ;[-5] exor mask | |
409 | ldi shift, 0x80 ;[-4] sync byte is first byte sent | |
410 | txByteLoop: | |
411 | ldi bitcnt, 0x40 ;[-3]=[9] binary 01000000 | |
412 | txBitLoop: ; the loop sends the first 7 bits of the byte | |
413 | sbrs shift, 0 ;[-2]=[10] if we have to send a 1 don't change the line state | |
414 | eor x1, x4 ;[-1]=[11] | |
415 | out USBOUT, x1 ;[0] | |
416 | ror shift ;[1] | |
417 | ror x2 ;[2] transfers the last sent bit to the stuffing history | |
418 | didStuffN: | |
419 | nop ;[3] | |
420 | nop ;[4] | |
421 | cpi x2, 0xfc ;[5] if we sent six consecutive ones | |
422 | brcc bitstuffN ;[6] | |
423 | lsr bitcnt ;[7] | |
424 | brne txBitLoop ;[8] restart the loop while the 1 is still in the bitcount | |
425 | ||
426 | ; transmit bit 7 | |
427 | sbrs shift, 0 ;[9] | |
428 | eor x1, x4 ;[10] | |
429 | didStuff7: | |
430 | ror shift ;[11] | |
431 | out USBOUT, x1 ;[0] transfer bit 7 to the pins | |
432 | ror x2 ;[1] move the bit into the stuffing history | |
433 | cpi x2, 0xfc ;[2] | |
434 | brcc bitstuff7 ;[3] | |
435 | ld shift, y+ ;[4] get next byte to transmit | |
436 | dec cnt ;[5] decrement byte counter | |
437 | brne txByteLoop ;[7] if we have more bytes start next one | |
438 | ;[8] branch delay | |
439 | ||
440 | ;make SE0: | |
441 | cbr x1, USBMASK ;[8] prepare SE0 [spec says EOP may be 25 to 30 cycles] | |
442 | lds x2, usbNewDeviceAddr;[9] | |
443 | lsl x2 ;[11] we compare with left shifted address | |
444 | out USBOUT, x1 ;[0] <-- out SE0 -- from now 2 bits = 24 cycles until bus idle | |
445 | subi YL, 20 + 2 ;[1] Only assign address on data packets, not ACK/NAK in x3 | |
446 | sbci YH, 0 ;[2] | |
447 | ;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: | |
448 | ;set address only after data packet was sent, not after handshake | |
449 | breq skipAddrAssign ;[3] | |
450 | sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer | |
451 | skipAddrAssign: | |
452 | ;end of usbDeviceAddress transfer | |
453 | ldi x2, 1<<USB_INTR_PENDING_BIT;[5] int0 occurred during TX -- clear pending flag | |
454 | USB_STORE_PENDING(x2) ;[6] | |
455 | ori x1, USBIDLE ;[7] | |
456 | in x2, USBDDR ;[8] | |
457 | cbr x2, USBMASK ;[9] set both pins to input | |
458 | mov x3, x1 ;[10] | |
459 | cbr x3, USBMASK ;[11] configure no pullup on both pins | |
460 | ldi x4, 4 ;[12] | |
461 | se0Delay: | |
462 | dec x4 ;[13] [16] [19] [22] | |
463 | brne se0Delay ;[14] [17] [20] [23] | |
464 | out USBOUT, x1 ;[24] <-- out J (idle) -- end of SE0 (EOP signal) | |
465 | out USBDDR, x2 ;[25] <-- release bus now | |
466 | out USBOUT, x3 ;[26] <-- ensure no pull-up resistors are active | |
467 | rjmp doReturn | |
468 | ||
469 | bitstuffN: | |
470 | eor x1, x4 ;[8] generate a zero | |
471 | ldi x2, 0 ;[9] reset the bit stuffing history | |
472 | nop2 ;[10] | |
473 | out USBOUT, x1 ;[0] <-- send the stuffing bit | |
474 | rjmp didStuffN ;[1] | |
475 | ||
476 | bitstuff7: | |
477 | eor x1, x4 ;[5] | |
478 | ldi x2, 0 ;[6] reset bit stuffing history | |
479 | clc ;[7] fill a zero into the shift register | |
480 | rol shift ;[8] compensate for ror shift at branch destination | |
481 | rjmp didStuff7 ;[9] | |
482 | ;[10] jump delay | |
483 | ||
484 | ;-------------------------------------------------------------------------------------------------------------- | |
485 | ; receives data bytes and calculates the crc | |
486 | ; second half of the data byte receiver loop | |
487 | ; most parts of the crc algorithm are here | |
488 | ;-------------------------------------------------------------------------------------------------------------- | |
489 | ||
490 | nOverflow2: | |
491 | rjmp overflow | |
492 | ||
493 | rxDataBit4: | |
494 | in x1, USBIN ;[0] sample line state | |
495 | andi x1, USBMASK ;[1] check for se0 | |
496 | breq nOverflow2 ;[2] | |
497 | eor x2, x1 ;[3] | |
498 | bst x2, USBMINUS ;[4] | |
499 | bld shift, 4 ;[5] | |
500 | mov x2, shift ;[6] | |
501 | andi x2, 0x9F ;[7] | |
502 | breq unstuff4 ;[8] | |
503 | didunstuff4: | |
504 | nop2 ;[9][10] | |
505 | nop ;[11] | |
506 | ||
507 | ; bit5 | |
508 | in x2, USBIN ;[0] sample line state | |
509 | ldi ZH, hi8(usbCrcTableHigh);[1] use the table for the higher byte | |
510 | eor x1, x2 ;[2] | |
511 | bst x1, USBMINUS ;[3] | |
512 | bld shift, 5 ;[4] | |
513 | mov x1, shift ;[5] | |
514 | andi x1, 0x3F ;[6] | |
515 | breq unstuff5 ;[7] | |
516 | didunstuff5: | |
517 | lpm x4, Z ;[8] load the higher crc xor-byte and store it for later use | |
518 | ;[9] lpm needs 3 cycles | |
519 | ;[10] | |
520 | ldi ZH, hi8(usbCrcTableLow);[11] load the lower crc xor byte adress | |
521 | ||
522 | ; bit6 | |
523 | in x1, USBIN ;[0] sample line state | |
524 | eor x2, x1 ;[1] | |
525 | bst x2, USBMINUS ;[2] | |
526 | bld shift, 6 ;[3] | |
527 | mov x2, shift ;[4] | |
528 | andi x2, 0x7E ;[5] | |
529 | breq unstuff6 ;[6] | |
530 | didunstuff6: | |
531 | lpm ZL, Z ;[7] load the lower xor crc byte | |
532 | ;[8] lpm needs 3 cycles | |
533 | ;[9] | |
534 | eor ZL, x3 ;[10] xor the old high crc byte with the low xor-byte | |
535 | mov x3, x4 ;[11] move the new high order crc value from temp to its destination | |
536 | ||
537 | ; bit7 | |
538 | in x2, USBIN ;[0] sample line state | |
539 | eor x1, x2 ;[1] | |
540 | bst x1, USBMINUS ;[2] | |
541 | bld shift, 7 ;[3] now shift holds the complete but inverted data byte | |
542 | mov x1, shift ;[4] | |
543 | andi x1, 0xFC ;[5] | |
544 | breq unstuff7 ;[6] | |
545 | didunstuff7: | |
546 | eor x5, shift ;[7] x5 marks all bits which have not been inverted by the unstuffing subs | |
547 | mov x4, x5 ;[8] keep a copy of the data byte it will be stored during next bit0 | |
548 | eor ZL, x4 ;[9] feed the actual byte into the crc algorithm | |
549 | rjmp rxDataStart ;[10] next byte | |
550 | ;[11] during the reception of the next byte this one will be fed int the crc algorithm | |
551 | ||
552 | unstuff4: ;[9] this is the jump delay of rjmp unstuffX | |
553 | ori shift, 0x10 ;[10] invert the last received bit to prevent furhter unstuffing | |
554 | andi x5, 0xEF ;[11] mark this bit as inverted (will be corrected before storing shift) | |
555 | in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors | |
556 | eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero | |
557 | andi x1, USBMASK ;[2] mask the interesting bits | |
558 | breq stuffErr2 ;[3] if the stuff bit is a 1-bit something went wrong | |
559 | mov x1, x2 ;[4] the next bit expects the last state to be in x1 | |
560 | nop2 ;[5] | |
561 | ;[6] | |
562 | rjmp didunstuff4 ;[7] | |
563 | ;[8] jump delay of rjmp didunstuffX | |
564 | ||
565 | unstuff5: ;[8] this is the jump delay of rjmp unstuffX | |
566 | nop ;[9] | |
567 | ori shift, 0x20 ;[10] invert the last received bit to prevent furhter unstuffing | |
568 | andi x5, 0xDF ;[11] mark this bit as inverted (will be corrected before storing shift) | |
569 | in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors | |
570 | eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero | |
571 | andi x2, USBMASK ;[2] mask the interesting bits | |
572 | breq stuffErr2 ;[3] if the stuff bit is a 1-bit something went wrong | |
573 | mov x2, x1 ;[4] the next bit expects the last state to be in x2 | |
574 | nop ;[5] | |
575 | rjmp didunstuff5 ;[6] | |
576 | ;[7] jump delay of rjmp didunstuffX | |
577 | ||
578 | unstuff6: ;[7] this is the jump delay of rjmp unstuffX | |
579 | nop2 ;[8] | |
580 | ;[9] | |
581 | ori shift, 0x40 ;[10] invert the last received bit to prevent furhter unstuffing | |
582 | andi x5, 0xBF ;[11] mark this bit as inverted (will be corrected before storing shift) | |
583 | in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors | |
584 | eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero | |
585 | andi x1, USBMASK ;[2] mask the interesting bits | |
586 | breq stuffErr2 ;[3] if the stuff bit is a 1-bit something went wrong | |
587 | mov x1, x2 ;[4] the next bit expects the last state to be in x1 | |
588 | rjmp didunstuff6 ;[5] | |
589 | ;[6] jump delay of rjmp didunstuffX | |
590 | ||
591 | unstuff7: ;[7] this is the jump delay of rjmp unstuffX | |
592 | nop ;[8] | |
593 | nop ;[9] | |
594 | ori shift, 0x80 ;[10] invert the last received bit to prevent furhter unstuffing | |
595 | andi x5, 0x7F ;[11] mark this bit as inverted (will be corrected before storing shift) | |
596 | in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors | |
597 | eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero | |
598 | andi x2, USBMASK ;[2] mask the interesting bits | |
599 | breq stuffErr2 ;[3] if the stuff bit is a 1-bit something went wrong | |
600 | mov x2, x1 ;[4] the next bit expects the last state to be in x2 | |
601 | rjmp didunstuff7 ;[5] | |
602 | ;[6] jump delay of rjmp didunstuff7 | |
603 | ||
604 | ; local copy of the stuffErr desitnation for the second half of the receiver loop | |
605 | stuffErr2: | |
606 | rjmp stuffErr | |
607 | ||
608 | ;-------------------------------------------------------------------------------------------------------------- | |
609 | ; The crc table follows. It has to be aligned to enable a fast loading of the needed bytes. | |
610 | ; There are two tables of 256 entries each, the low and the high byte table. | |
611 | ; Table values were generated with the following C code: | |
612 | /* | |
613 | #include <stdio.h> | |
614 | int main (int argc, char **argv) | |
615 | { | |
616 | int i, j; | |
617 | for (i=0; i<512; i++){ | |
618 | unsigned short crc = i & 0xff; | |
619 | for(j=0; j<8; j++) crc = (crc >> 1) ^ ((crc & 1) ? 0xa001 : 0); | |
620 | if((i & 7) == 0) printf("\n.byte "); | |
621 | printf("0x%02x, ", (i > 0xff ? (crc >> 8) : crc) & 0xff); | |
622 | if(i == 255) printf("\n"); | |
623 | } | |
624 | return 0; | |
625 | } | |
626 | ||
627 | // Use the following algorithm to compute CRC values: | |
628 | ushort computeCrc(uchar *msg, uchar msgLen) | |
629 | { | |
630 | uchar i; | |
631 | ushort crc = 0xffff; | |
632 | for(i = 0; i < msgLen; i++) | |
633 | crc = usbCrcTable16[lo8(crc) ^ msg[i]] ^ hi8(crc); | |
634 | return crc; | |
635 | } | |
636 | */ | |
637 | ||
638 | .balign 256 | |
639 | usbCrcTableLow: | |
640 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
641 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
642 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
643 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
644 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
645 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
646 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
647 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
648 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
649 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
650 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
651 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
652 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
653 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
654 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
655 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
656 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
657 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
658 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
659 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
660 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
661 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
662 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
663 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
664 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
665 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
666 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
667 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
668 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
669 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
670 | .byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41 | |
671 | .byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 | |
672 | ||
673 | ; .balign 256 | |
674 | usbCrcTableHigh: | |
675 | .byte 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2 | |
676 | .byte 0xC6, 0x06, 0x07, 0xC7, 0x05, 0xC5, 0xC4, 0x04 | |
677 | .byte 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E | |
678 | .byte 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8 | |
679 | .byte 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A | |
680 | .byte 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC | |
681 | .byte 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6 | |
682 | .byte 0xD2, 0x12, 0x13, 0xD3, 0x11, 0xD1, 0xD0, 0x10 | |
683 | .byte 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32 | |
684 | .byte 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4 | |
685 | .byte 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE | |
686 | .byte 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38 | |
687 | .byte 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA | |
688 | .byte 0xEE, 0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C | |
689 | .byte 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26 | |
690 | .byte 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0 | |
691 | .byte 0xA0, 0x60, 0x61, 0xA1, 0x63, 0xA3, 0xA2, 0x62 | |
692 | .byte 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4 | |
693 | .byte 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE | |
694 | .byte 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68 | |
695 | .byte 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA | |
696 | .byte 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C | |
697 | .byte 0xB4, 0x74, 0x75, 0xB5, 0x77, 0xB7, 0xB6, 0x76 | |
698 | .byte 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0 | |
699 | .byte 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92 | |
700 | .byte 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54 | |
701 | .byte 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E | |
702 | .byte 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98 | |
703 | .byte 0x88, 0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A | |
704 | .byte 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C | |
705 | .byte 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86 | |
706 | .byte 0x82, 0x42, 0x43, 0x83, 0x41, 0x81, 0x80, 0x40 | |
707 |