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   1 ------------------------------------------------------------------------------
   2 -- t80as.vhd : The non-tristate signal edition of t80a.vhd
   3 --
   4 -- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
   5 --
   6 -- 1.separate 'D' to 'DO' and 'DI'.
   7 -- 2.added 'DOE' to 'DO' enable signal.(data direction)
   8 -- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'.
   9 --
  10 -- There is a mark of "--AS" in all the change points.
  11 --
  12 ------------------------------------------------------------------------------
  13
  14 --
  15 -- Z80 compatible microprocessor core, asynchronous top level
  16 --
  17 -- Version : 0247
  18 --
  19 -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
  20 --
  21 -- All rights reserved
  22 --
  23 -- Redistribution and use in source and synthezised forms, with or without
  24 -- modification, are permitted provided that the following conditions are met:
  25 --
  26 -- Redistributions of source code must retain the above copyright notice,
  27 -- this list of conditions and the following disclaimer.
  28 --
  29 -- Redistributions in synthesized form must reproduce the above copyright
  30 -- notice, this list of conditions and the following disclaimer in the
  31 -- documentation and/or other materials provided with the distribution.
  32 --
  33 -- Neither the name of the author nor the names of other contributors may
  34 -- be used to endorse or promote products derived from this software without
  35 -- specific prior written permission.
  36 --
  37 -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  38 -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  39 -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  40 -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
  41 -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  42 -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  43 -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  44 -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  45 -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  46 -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  47 -- POSSIBILITY OF SUCH DAMAGE.
  48 --
  49 -- Please report bugs to the author, but before you do so, please
  50 -- make sure that this is not a derivative work and that
  51 -- you have the latest version of this file.
  52 --
  53 -- The latest version of this file can be found at:
  54 --      http://www.opencores.org/cvsweb.shtml/t80/
  55 --
  56 -- Limitations :
  57 --
  58 -- File history :
  59 --
  60 --      0208 : First complete release
  61 --
  62 --      0211 : Fixed interrupt cycle
  63 --
  64 --      0235 : Updated for T80 interface change
  65 --
  66 --      0238 : Updated for T80 interface change
  67 --
  68 --      0240 : Updated for T80 interface change
  69 --
  70 --      0242 : Updated for T80 interface change
  71 --
  72 --      0247 : Fixed bus req/ack cycle
  73 --
  74
  75 library IEEE;
  76 use IEEE.std_logic_1164.all;
  77 use IEEE.numeric_std.all;
  78 use work.T80_Pack.all;
  79
  80 entity T80as is
  81         generic(
  82                 Mode : integer := 0     -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
  83         );
  84         port(
  85                 RESET_n         : in std_logic;
  86                 CLK_n           : in std_logic;
  87                 WAIT_n          : in std_logic;
  88                 INT_n           : in std_logic;
  89                 NMI_n           : in std_logic;
  90                 BUSRQ_n         : in std_logic;
  91                 M1_n            : out std_logic;
  92                 MREQ_n          : out std_logic;
  93                 IORQ_n          : out std_logic;
  94                 RD_n            : out std_logic;
  95                 WR_n            : out std_logic;
  96                 RFSH_n          : out std_logic;
  97                 HALT_n          : out std_logic;
  98                 BUSAK_n         : out std_logic;
  99                 A                       : out std_logic_vector(15 downto 0);
 100 --AS--  D                       : inout std_logic_vector(7 downto 0)
 101 --AS>>
 102                 DI                      : in  std_logic_vector(7 downto 0);
 103                 DO                      : out std_logic_vector(7 downto 0);
 104                 DOE                     : out std_logic
 105 --<<AS
 106         );
 107 end T80as;
 108
 109 architecture rtl of T80as is
 110
 111         signal CEN                      : std_logic;
 112         signal Reset_s          : std_logic;
 113         signal IntCycle_n       : std_logic;
 114         signal IORQ                     : std_logic;
 115         signal NoRead           : std_logic;
 116         signal Write            : std_logic;
 117         signal MREQ                     : std_logic;
 118         signal MReq_Inhibit     : std_logic;
 119         signal Req_Inhibit      : std_logic;
 120         signal RD                       : std_logic;
 121         signal MREQ_n_i         : std_logic;
 122         signal IORQ_n_i         : std_logic;
 123         signal RD_n_i           : std_logic;
 124         signal WR_n_i           : std_logic;
 125         signal RFSH_n_i         : std_logic;
 126         signal BUSAK_n_i        : std_logic;
 127         signal A_i                      : std_logic_vector(15 downto 0);
 128 --AS--  signal DO                       : std_logic_vector(7 downto 0);
 129         signal DI_Reg           : std_logic_vector (7 downto 0);        -- Input synchroniser
 130         signal Wait_s           : std_logic;
 131         signal MCycle           : std_logic_vector(2 downto 0);
 132         signal TState           : std_logic_vector(2 downto 0);
 133
 134 begin
 135
 136         CEN <= '1';
 137
 138         BUSAK_n <= BUSAK_n_i;
 139         MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
 140         RD_n_i <= not RD or Req_Inhibit;
 141
 142 --AS--  MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
 143 --AS--  IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
 144 --AS--  RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
 145 --AS--  WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
 146 --AS--  RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
 147 --AS--  A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
 148 --AS--  D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
 149 --AS>>
 150         MREQ_n <= MREQ_n_i;
 151         IORQ_n <= IORQ_n_i;
 152         RD_n <= RD_n_i;
 153         WR_n <= WR_n_i;
 154         RFSH_n <= RFSH_n_i;
 155         A <= A_i;
 156         DOE <= Write when BUSAK_n_i = '1' else '0';
 157 --<<AS
 158         process (RESET_n, CLK_n)
 159         begin
 160                 if RESET_n = '0' then
 161                         Reset_s <= '0';
 162                 elsif CLK_n'event and CLK_n = '1' then
 163                         Reset_s <= '1';
 164                 end if;
 165         end process;
 166
 167         u0 : T80
 168                 generic map(
 169                         Mode => Mode,
 170                         IOWait => 1)
 171                 port map(
 172                         CEN => CEN,
 173                         M1_n => M1_n,
 174                         IORQ => IORQ,
 175                         NoRead => NoRead,
 176                         Write => Write,
 177                         RFSH_n => RFSH_n_i,
 178                         HALT_n => HALT_n,
 179                         WAIT_n => Wait_s,
 180                         INT_n => INT_n,
 181                         NMI_n => NMI_n,
 182                         RESET_n => Reset_s,
 183                         BUSRQ_n => BUSRQ_n,
 184                         BUSAK_n => BUSAK_n_i,
 185                         CLK_n => CLK_n,
 186                         A => A_i,
 187 --                      DInst => D,
 188                         DInst => DI,
 189                         DI => DI_Reg,
 190                         DO => DO,
 191                         MC => MCycle,
 192                         TS => TState,
 193                         IntCycle_n => IntCycle_n);
 194
 195         process (CLK_n)
 196         begin
 197                 if CLK_n'event and CLK_n = '0' then
 198                         Wait_s <= WAIT_n;
 199                         if TState = "011" and BUSAK_n_i = '1' then
 200 --AS--                          DI_Reg <= to_x01(D);
 201 --AS>>
 202                                 DI_Reg <= to_x01(DI);
 203 --<<AS
 204                         end if;
 205                 end if;
 206         end process;
 207
 208         process (Reset_s,CLK_n)
 209         begin
 210                 if Reset_s = '0' then
 211                         WR_n_i <= '1';
 212                 elsif CLK_n'event and CLK_n = '1' then
 213                         WR_n_i <= '1';
 214                         if TState = "001" then  -- To short for IO writes !!!!!!!!!!!!!!!!!!!
 215                                 WR_n_i <= not Write;
 216                         end if;
 217                 end if;
 218         end process;
 219
 220         process (Reset_s,CLK_n)
 221         begin
 222                 if Reset_s = '0' then
 223                         Req_Inhibit <= '0';
 224                 elsif CLK_n'event and CLK_n = '1' then
 225                         if MCycle = "001" and TState = "010" then
 226                                 Req_Inhibit <= '1';
 227                         else
 228                                 Req_Inhibit <= '0';
 229                         end if;
 230                 end if;
 231         end process;
 232
 233         process (Reset_s,CLK_n)
 234         begin
 235                 if Reset_s = '0' then
 236                         MReq_Inhibit <= '0';
 237                 elsif CLK_n'event and CLK_n = '0' then
 238                         if MCycle = "001" and TState = "010" then
 239                                 MReq_Inhibit <= '1';
 240                         else
 241                                 MReq_Inhibit <= '0';
 242                         end if;
 243                 end if;
 244         end process;
 245
 246         process(Reset_s,CLK_n)
 247         begin
 248                 if Reset_s = '0' then
 249                         RD <= '0';
 250                         IORQ_n_i <= '1';
 251                         MREQ <= '0';
 252                 elsif CLK_n'event and CLK_n = '0' then
 253
 254                         if MCycle = "001" then
 255                                 if TState = "001" then
 256                                         RD <= IntCycle_n;
 257                                         MREQ <= IntCycle_n;
 258                                         IORQ_n_i <= IntCycle_n;
 259                                 end if;
 260                                 if TState = "011" then
 261                                         RD <= '0';
 262                                         IORQ_n_i <= '1';
 263                                         MREQ <= '1';
 264                                 end if;
 265                                 if TState = "100" then
 266                                         MREQ <= '0';
 267                                 end if;
 268                         else
 269                                 if TState = "001" and NoRead = '0' then
 270                                         RD <= not Write;
 271                                         IORQ_n_i <= not IORQ;
 272                                         MREQ <= not IORQ;
 273                                 end if;
 274                                 if TState = "011" then
 275                                         RD <= '0';
 276                                         IORQ_n_i <= '1';
 277                                         MREQ <= '0';
 278                                 end if;
 279                         end if;
 280                 end if;
 281         end process;
 282
 283 end;