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a126332a 1 //-----------------------------------------------------------------------------
b62a5a84 2// Merlok - June 2011, 2012
15c4dc5a 3// Gerhard de Koning Gans - May 2008
534983d7 4// Hagen Fritsch - June 2010
bd20f8f4 5//
6// This code is licensed to you under the terms of the GNU GPL, version 2 or,
7// at your option, any later version. See the LICENSE.txt file for the text of
8// the license.
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10// Routines to support ISO 14443 type A.
11//-----------------------------------------------------------------------------
12
e30c654b 13#include "proxmark3.h"
15c4dc5a 14#include "apps.h"
f7e3ed82 15#include "util.h"
9ab7a6c7 16#include "string.h"
902cb3c0 17#include "cmd.h"
15c4dc5a 18#include "iso14443crc.h"
534983d7 19#include "iso14443a.h"
20f9a2a1
M
20#include "crapto1.h"
21#include "mifareutil.h"
3000dc4e 22#include "BigBuf.h"
f8ada309 23#include "parity.h"
24
534983d7 25static uint32_t iso14a_timeout;
1e262141 26int rsamples = 0;
1e262141 27uint8_t trigger = 0;
b0127e65 28// the block number for the ISO14443-4 PCB
29static uint8_t iso14_pcb_blocknum = 0;
15c4dc5a 30
7bc95e2e 31//
32// ISO14443 timing:
33//
34// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
35#define REQUEST_GUARD_TIME (7000/16 + 1)
36// minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
37#define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
38// bool LastCommandWasRequest = FALSE;
39
40//
41// Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
42//
d714d3ef 43// When the PM acts as reader and is receiving tag data, it takes
44// 3 ticks delay in the AD converter
45// 16 ticks until the modulation detector completes and sets curbit
46// 8 ticks until bit_to_arm is assigned from curbit
47// 8*16 ticks for the transfer from FPGA to ARM
7bc95e2e 48// 4*16 ticks until we measure the time
49// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 50#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
7bc95e2e 51
52// When the PM acts as a reader and is sending, it takes
53// 4*16 ticks until we can write data to the sending hold register
54// 8*16 ticks until the SHR is transferred to the Sending Shift Register
55// 8 ticks until the first transfer starts
56// 8 ticks later the FPGA samples the data
57// 1 tick to assign mod_sig_coil
58#define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
59
60// When the PM acts as tag and is receiving it takes
d714d3ef 61// 2 ticks delay in the RF part (for the first falling edge),
7bc95e2e 62// 3 ticks for the A/D conversion,
63// 8 ticks on average until the start of the SSC transfer,
64// 8 ticks until the SSC samples the first data
65// 7*16 ticks to complete the transfer from FPGA to ARM
66// 8 ticks until the next ssp_clk rising edge
d714d3ef 67// 4*16 ticks until we measure the time
7bc95e2e 68// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 69#define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
7bc95e2e 70
71// The FPGA will report its internal sending delay in
72uint16_t FpgaSendQueueDelay;
73// the 5 first bits are the number of bits buffered in mod_sig_buf
74// the last three bits are the remaining ticks/2 after the mod_sig_buf shift
75#define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
76
77// When the PM acts as tag and is sending, it takes
d714d3ef 78// 4*16 ticks until we can write data to the sending hold register
7bc95e2e 79// 8*16 ticks until the SHR is transferred to the Sending Shift Register
80// 8 ticks until the first transfer starts
81// 8 ticks later the FPGA samples the data
82// + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
83// + 1 tick to assign mod_sig_coil
d714d3ef 84#define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
7bc95e2e 85
86// When the PM acts as sniffer and is receiving tag data, it takes
87// 3 ticks A/D conversion
d714d3ef 88// 14 ticks to complete the modulation detection
89// 8 ticks (on average) until the result is stored in to_arm
7bc95e2e 90// + the delays in transferring data - which is the same for
91// sniffing reader and tag data and therefore not relevant
d714d3ef 92#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
7bc95e2e 93
d714d3ef 94// When the PM acts as sniffer and is receiving reader data, it takes
95// 2 ticks delay in analogue RF receiver (for the falling edge of the
96// start bit, which marks the start of the communication)
7bc95e2e 97// 3 ticks A/D conversion
d714d3ef 98// 8 ticks on average until the data is stored in to_arm.
7bc95e2e 99// + the delays in transferring data - which is the same for
100// sniffing reader and tag data and therefore not relevant
d714d3ef 101#define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
7bc95e2e 102
103//variables used for timing purposes:
104//these are in ssp_clk cycles:
6a1f2d82 105static uint32_t NextTransferTime;
106static uint32_t LastTimeProxToAirStart;
107static uint32_t LastProxToAirDuration;
7bc95e2e 108
109
110
8f51ddb0 111// CARD TO READER - manchester
72934aa3 112// Sequence D: 11110000 modulation with subcarrier during first half
113// Sequence E: 00001111 modulation with subcarrier during second half
114// Sequence F: 00000000 no modulation with subcarrier
8f51ddb0 115// READER TO CARD - miller
72934aa3 116// Sequence X: 00001100 drop after half a period
117// Sequence Y: 00000000 no drop
118// Sequence Z: 11000000 drop at start
119#define SEC_D 0xf0
120#define SEC_E 0x0f
121#define SEC_F 0x00
122#define SEC_X 0x0c
123#define SEC_Y 0x00
124#define SEC_Z 0xc0
15c4dc5a 125
902cb3c0 126void iso14a_set_trigger(bool enable) {
534983d7 127 trigger = enable;
128}
129
d19929cb 130
b0127e65 131void iso14a_set_timeout(uint32_t timeout) {
132 iso14a_timeout = timeout;
19a700a8 133 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
b0127e65 134}
8556b852 135
19a700a8 136
137void iso14a_set_ATS_timeout(uint8_t *ats) {
138
139 uint8_t tb1;
140 uint8_t fwi;
141 uint32_t fwt;
142
143 if (ats[0] > 1) { // there is a format byte T0
144 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
145 if ((ats[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
146 tb1 = ats[3];
147 } else {
148 tb1 = ats[2];
149 }
150 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
151 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
152
153 iso14a_set_timeout(fwt/(8*16));
154 }
155 }
156}
157
158
15c4dc5a 159//-----------------------------------------------------------------------------
160// Generate the parity value for a byte sequence
e30c654b 161//
15c4dc5a 162//-----------------------------------------------------------------------------
6a1f2d82 163void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
15c4dc5a 164{
6a1f2d82 165 uint16_t paritybit_cnt = 0;
166 uint16_t paritybyte_cnt = 0;
167 uint8_t parityBits = 0;
168
169 for (uint16_t i = 0; i < iLen; i++) {
170 // Generate the parity bits
f8ada309 171 parityBits |= ((oddparity8(pbtCmd[i])) << (7-paritybit_cnt));
6a1f2d82 172 if (paritybit_cnt == 7) {
173 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
174 parityBits = 0; // and advance to next Parity Byte
175 paritybyte_cnt++;
176 paritybit_cnt = 0;
177 } else {
178 paritybit_cnt++;
179 }
5f6d6c90 180 }
6a1f2d82 181
182 // save remaining parity bits
183 par[paritybyte_cnt] = parityBits;
184
15c4dc5a 185}
186
534983d7 187void AppendCrc14443a(uint8_t* data, int len)
15c4dc5a 188{
5f6d6c90 189 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
15c4dc5a 190}
191
0ec548dc 192void AppendCrc14443b(uint8_t* data, int len)
193{
194 ComputeCrc14443(CRC_14443_B,data,len,data+len,data+len+1);
195}
196
197
7bc95e2e 198//=============================================================================
199// ISO 14443 Type A - Miller decoder
200//=============================================================================
201// Basics:
202// This decoder is used when the PM3 acts as a tag.
203// The reader will generate "pauses" by temporarily switching of the field.
204// At the PM3 antenna we will therefore measure a modulated antenna voltage.
205// The FPGA does a comparison with a threshold and would deliver e.g.:
206// ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
207// The Miller decoder needs to identify the following sequences:
208// 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
209// 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
210// 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
211// Note 1: the bitstream may start at any time. We therefore need to sync.
212// Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
15c4dc5a 213//-----------------------------------------------------------------------------
b62a5a84 214static tUart Uart;
15c4dc5a 215
d7aa3739 216// Lookup-Table to decide if 4 raw bits are a modulation.
0ec548dc 217// We accept the following:
218// 0001 - a 3 tick wide pause
219// 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
220// 0111 - a 2 tick wide pause shifted left
221// 1001 - a 2 tick wide pause shifted right
d7aa3739 222const bool Mod_Miller_LUT[] = {
0ec548dc 223 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
224 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
d7aa3739 225};
0ec548dc 226#define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
227#define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
d7aa3739 228
7bc95e2e 229void UartReset()
15c4dc5a 230{
7bc95e2e 231 Uart.state = STATE_UNSYNCD;
232 Uart.bitCount = 0;
233 Uart.len = 0; // number of decoded data bytes
6a1f2d82 234 Uart.parityLen = 0; // number of decoded parity bytes
7bc95e2e 235 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
6a1f2d82 236 Uart.parityBits = 0; // holds 8 parity bits
7bc95e2e 237 Uart.startTime = 0;
238 Uart.endTime = 0;
46c65fed 239
240 Uart.byteCntMax = 0;
241 Uart.posCnt = 0;
242 Uart.syncBit = 9999;
7bc95e2e 243}
15c4dc5a 244
6a1f2d82 245void UartInit(uint8_t *data, uint8_t *parity)
246{
247 Uart.output = data;
248 Uart.parity = parity;
0ec548dc 249 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
6a1f2d82 250 UartReset();
251}
d714d3ef 252
7bc95e2e 253// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
254static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
255{
15c4dc5a 256
0ec548dc 257 Uart.fourBits = (Uart.fourBits << 8) | bit;
7bc95e2e 258
0c8d25eb 259 if (Uart.state == STATE_UNSYNCD) { // not yet synced
3fe4ff4f 260
0ec548dc 261 Uart.syncBit = 9999; // not set
46c65fed 262
263 // 00x11111 2|3 ticks pause followed by 6|5 ticks unmodulated Sequence Z (a "0" or "start of communication")
264 // 11111111 8 ticks unmodulation Sequence Y (a "0" or "end of communication" or "no information")
265 // 111100x1 4 ticks unmodulated followed by 2|3 ticks pause Sequence X (a "1")
266
0ec548dc 267 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
46c65fed 268 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
269 // we therefore look for a ...xx1111 11111111 00x11111xxxxxx... pattern
0ec548dc 270 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
46c65fed 271 //
272#define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00001111 11111111 1110 1111 10000000
273#define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00001111 11111111 1000 1111 10000000
274
0ec548dc 275 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
276 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
277 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
278 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
279 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
280 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
281 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
282 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
283
284 if (Uart.syncBit != 9999) { // found a sync bit
7bc95e2e 285 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
286 Uart.startTime -= Uart.syncBit;
d7aa3739 287 Uart.endTime = Uart.startTime;
7bc95e2e 288 Uart.state = STATE_START_OF_COMMUNICATION;
15c4dc5a 289 }
290
7bc95e2e 291 } else {
15c4dc5a 292
0ec548dc 293 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
294 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
d7aa3739 295 UartReset();
d7aa3739 296 } else { // Modulation in first half = Sequence Z = logic "0"
7bc95e2e 297 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
298 UartReset();
7bc95e2e 299 } else {
300 Uart.bitCount++;
301 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
302 Uart.state = STATE_MILLER_Z;
303 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
304 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
305 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
306 Uart.parityBits <<= 1; // make room for the parity bit
307 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
308 Uart.bitCount = 0;
309 Uart.shiftReg = 0;
6a1f2d82 310 if((Uart.len&0x0007) == 0) { // every 8 data bytes
311 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
312 Uart.parityBits = 0;
313 }
15c4dc5a 314 }
7bc95e2e 315 }
d7aa3739 316 }
317 } else {
0ec548dc 318 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
7bc95e2e 319 Uart.bitCount++;
320 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
321 Uart.state = STATE_MILLER_X;
322 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
323 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
324 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
325 Uart.parityBits <<= 1; // make room for the new parity bit
326 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
327 Uart.bitCount = 0;
328 Uart.shiftReg = 0;
6a1f2d82 329 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
330 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
331 Uart.parityBits = 0;
332 }
7bc95e2e 333 }
d7aa3739 334 } else { // no modulation in both halves - Sequence Y
7bc95e2e 335 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
15c4dc5a 336 Uart.state = STATE_UNSYNCD;
6a1f2d82 337 Uart.bitCount--; // last "0" was part of EOC sequence
338 Uart.shiftReg <<= 1; // drop it
339 if(Uart.bitCount > 0) { // if we decoded some bits
340 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
341 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
342 Uart.parityBits <<= 1; // add a (void) parity bit
343 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
344 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
345 return TRUE;
346 } else if (Uart.len & 0x0007) { // there are some parity bits to store
347 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
348 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
52bfb955 349 }
350 if (Uart.len) {
6a1f2d82 351 return TRUE; // we are finished with decoding the raw data sequence
52bfb955 352 } else {
0c8d25eb 353 UartReset(); // Nothing received - start over
7bc95e2e 354 }
15c4dc5a 355 }
7bc95e2e 356 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
357 UartReset();
7bc95e2e 358 } else { // a logic "0"
359 Uart.bitCount++;
360 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
361 Uart.state = STATE_MILLER_Y;
362 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
363 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
364 Uart.parityBits <<= 1; // make room for the parity bit
365 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
366 Uart.bitCount = 0;
367 Uart.shiftReg = 0;
6a1f2d82 368 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
369 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
370 Uart.parityBits = 0;
371 }
15c4dc5a 372 }
373 }
d7aa3739 374 }
15c4dc5a 375 }
7bc95e2e 376
377 }
15c4dc5a 378
7bc95e2e 379 return FALSE; // not finished yet, need more data
15c4dc5a 380}
381
7bc95e2e 382
383
15c4dc5a 384//=============================================================================
e691fc45 385// ISO 14443 Type A - Manchester decoder
15c4dc5a 386//=============================================================================
e691fc45 387// Basics:
7bc95e2e 388// This decoder is used when the PM3 acts as a reader.
e691fc45 389// The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
390// at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
391// ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
392// The Manchester decoder needs to identify the following sequences:
393// 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
394// 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
395// 8 ticks unmodulated: Sequence F = end of communication
396// 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
7bc95e2e 397// Note 1: the bitstream may start at any time. We therefore need to sync.
e691fc45 398// Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
b62a5a84 399static tDemod Demod;
15c4dc5a 400
d7aa3739 401// Lookup-Table to decide if 4 raw bits are a modulation.
d714d3ef 402// We accept three or four "1" in any position
7bc95e2e 403const bool Mod_Manchester_LUT[] = {
d7aa3739 404 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
d714d3ef 405 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
7bc95e2e 406};
407
408#define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
409#define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
15c4dc5a 410
2f2d9fc5 411
7bc95e2e 412void DemodReset()
e691fc45 413{
7bc95e2e 414 Demod.state = DEMOD_UNSYNCD;
415 Demod.len = 0; // number of decoded data bytes
6a1f2d82 416 Demod.parityLen = 0;
7bc95e2e 417 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
418 Demod.parityBits = 0; //
419 Demod.collisionPos = 0; // Position of collision bit
420 Demod.twoBits = 0xffff; // buffer for 2 Bits
421 Demod.highCnt = 0;
422 Demod.startTime = 0;
423 Demod.endTime = 0;
46c65fed 424
425 //
426 Demod.bitCount = 0;
427 Demod.syncBit = 0xFFFF;
428 Demod.samples = 0;
e691fc45 429}
15c4dc5a 430
6a1f2d82 431void DemodInit(uint8_t *data, uint8_t *parity)
432{
433 Demod.output = data;
434 Demod.parity = parity;
435 DemodReset();
436}
437
7bc95e2e 438// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
439static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
e691fc45 440{
7bc95e2e 441
442 Demod.twoBits = (Demod.twoBits << 8) | bit;
e691fc45 443
7bc95e2e 444 if (Demod.state == DEMOD_UNSYNCD) {
445
446 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
447 if (Demod.twoBits == 0x0000) {
448 Demod.highCnt++;
449 } else {
450 Demod.highCnt = 0;
451 }
452 } else {
453 Demod.syncBit = 0xFFFF; // not set
454 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
455 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
456 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
457 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
458 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
459 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
460 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
461 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
d7aa3739 462 if (Demod.syncBit != 0xFFFF) {
7bc95e2e 463 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
464 Demod.startTime -= Demod.syncBit;
465 Demod.bitCount = offset; // number of decoded data bits
e691fc45 466 Demod.state = DEMOD_MANCHESTER_DATA;
2f2d9fc5 467 }
7bc95e2e 468 }
15c4dc5a 469
7bc95e2e 470 } else {
15c4dc5a 471
7bc95e2e 472 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
473 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
e691fc45 474 if (!Demod.collisionPos) {
475 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
476 }
477 } // modulation in first half only - Sequence D = 1
7bc95e2e 478 Demod.bitCount++;
479 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
480 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
e691fc45 481 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 482 Demod.parityBits <<= 1; // make room for the parity bit
e691fc45 483 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
484 Demod.bitCount = 0;
485 Demod.shiftReg = 0;
6a1f2d82 486 if((Demod.len&0x0007) == 0) { // every 8 data bytes
487 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
488 Demod.parityBits = 0;
489 }
15c4dc5a 490 }
7bc95e2e 491 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
492 } else { // no modulation in first half
493 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
e691fc45 494 Demod.bitCount++;
7bc95e2e 495 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
e691fc45 496 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
e691fc45 497 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 498 Demod.parityBits <<= 1; // make room for the new parity bit
e691fc45 499 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
500 Demod.bitCount = 0;
501 Demod.shiftReg = 0;
6a1f2d82 502 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
503 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
504 Demod.parityBits = 0;
505 }
15c4dc5a 506 }
7bc95e2e 507 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
e691fc45 508 } else { // no modulation in both halves - End of communication
6a1f2d82 509 if(Demod.bitCount > 0) { // there are some remaining data bits
510 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
511 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
512 Demod.parityBits <<= 1; // add a (void) parity bit
513 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
514 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
515 return TRUE;
516 } else if (Demod.len & 0x0007) { // there are some parity bits to store
517 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
518 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
52bfb955 519 }
520 if (Demod.len) {
d7aa3739 521 return TRUE; // we are finished with decoding the raw data sequence
522 } else { // nothing received. Start over
523 DemodReset();
e691fc45 524 }
15c4dc5a 525 }
7bc95e2e 526 }
e691fc45 527 }
e691fc45 528 return FALSE; // not finished yet, need more data
15c4dc5a 529}
530
531//=============================================================================
532// Finally, a `sniffer' for ISO 14443 Type A
533// Both sides of communication!
534//=============================================================================
535
536//-----------------------------------------------------------------------------
537// Record the sequence of commands sent by the reader to the tag, with
538// triggering so that we start recording at the point that the tag is moved
539// near the reader.
540//-----------------------------------------------------------------------------
d26849d4 541void RAMFUNC SniffIso14443a(uint8_t param) {
5cd9ec01
M
542 // param:
543 // bit 0 - trigger from first card answer
544 // bit 1 - trigger from first reader 7-bit request
5cd9ec01 545 LEDsoff();
5cd9ec01 546
99cf19d9 547 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
7bc95e2e 548
f71f4deb 549 // Allocate memory from BigBuf for some buffers
550 // free all previous allocations first
551 BigBuf_free();
7838f4be 552
553 // init trace buffer
554 clear_trace();
555 set_tracing(TRUE);
556
5cd9ec01 557 // The command (reader -> tag) that we're receiving.
f71f4deb 558 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
559 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
6a1f2d82 560
5cd9ec01 561 // The response (tag -> reader) that we're receiving.
f71f4deb 562 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
563 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
5cd9ec01
M
564
565 // The DMA buffer, used to stream samples from the FPGA
f71f4deb 566 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
567
7bc95e2e 568 uint8_t *data = dmaBuf;
569 uint8_t previous_data = 0;
5cd9ec01
M
570 int maxDataLen = 0;
571 int dataLen = 0;
7bc95e2e 572 bool TagIsActive = FALSE;
573 bool ReaderIsActive = FALSE;
574
5cd9ec01 575 // Set up the demodulator for tag -> reader responses.
6a1f2d82 576 DemodInit(receivedResponse, receivedResponsePar);
577
5cd9ec01 578 // Set up the demodulator for the reader -> tag commands
6a1f2d82 579 UartInit(receivedCmd, receivedCmdPar);
580
7bc95e2e 581 // Setup and start DMA.
5cd9ec01 582 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
7bc95e2e 583
99cf19d9 584 // We won't start recording the frames that we acquire until we trigger;
585 // a good trigger condition to get started is probably when we see a
586 // response from the tag.
587 // triggered == FALSE -- to wait first for card
588 bool triggered = !(param & 0x03);
589
5cd9ec01 590 // And now we loop, receiving samples.
7bc95e2e 591 for(uint32_t rsamples = 0; TRUE; ) {
592
5cd9ec01
M
593 if(BUTTON_PRESS()) {
594 DbpString("cancelled by button");
7bc95e2e 595 break;
5cd9ec01 596 }
15c4dc5a 597
5cd9ec01
M
598 LED_A_ON();
599 WDT_HIT();
15c4dc5a 600
5cd9ec01
M
601 int register readBufDataP = data - dmaBuf;
602 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
603 if (readBufDataP <= dmaBufDataP){
604 dataLen = dmaBufDataP - readBufDataP;
605 } else {
7bc95e2e 606 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
5cd9ec01
M
607 }
608 // test for length of buffer
609 if(dataLen > maxDataLen) {
610 maxDataLen = dataLen;
f71f4deb 611 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
7bc95e2e 612 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
613 break;
5cd9ec01
M
614 }
615 }
616 if(dataLen < 1) continue;
617
618 // primary buffer was stopped( <-- we lost data!
619 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
620 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
621 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
7bc95e2e 622 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
623 }
624 // secondary buffer sets as primary, secondary buffer was stopped
625 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
626 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
627 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
628 }
629
630 LED_A_OFF();
7bc95e2e 631
632 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
3be2a5ae 633
7bc95e2e 634 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
635 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
636 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
637 LED_C_ON();
5cd9ec01 638
7bc95e2e 639 // check - if there is a short 7bit request from reader
640 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
5cd9ec01 641
7bc95e2e 642 if(triggered) {
6a1f2d82 643 if (!LogTrace(receivedCmd,
644 Uart.len,
645 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
646 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
647 Uart.parity,
648 TRUE)) break;
7bc95e2e 649 }
650 /* And ready to receive another command. */
651 UartReset();
652 /* And also reset the demod code, which might have been */
653 /* false-triggered by the commands from the reader. */
654 DemodReset();
655 LED_B_OFF();
656 }
657 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
5cd9ec01 658 }
3be2a5ae 659
7bc95e2e 660 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
661 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
662 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
663 LED_B_ON();
5cd9ec01 664
6a1f2d82 665 if (!LogTrace(receivedResponse,
666 Demod.len,
667 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
668 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
669 Demod.parity,
670 FALSE)) break;
5cd9ec01 671
7bc95e2e 672 if ((!triggered) && (param & 0x01)) triggered = TRUE;
5cd9ec01 673
7bc95e2e 674 // And ready to receive another response.
675 DemodReset();
0ec548dc 676 // And reset the Miller decoder including itS (now outdated) input buffer
677 UartInit(receivedCmd, receivedCmdPar);
678
7bc95e2e 679 LED_C_OFF();
680 }
681 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
682 }
5cd9ec01
M
683 }
684
7bc95e2e 685 previous_data = *data;
686 rsamples++;
5cd9ec01 687 data++;
d714d3ef 688 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01
M
689 data = dmaBuf;
690 }
691 } // main cycle
692
7bc95e2e 693 FpgaDisableSscDma();
7838f4be 694 LEDsoff();
695
7bc95e2e 696 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
3000dc4e 697 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
5ee53a0e 698
699 set_tracing(FALSE);
15c4dc5a 700}
701
15c4dc5a 702//-----------------------------------------------------------------------------
703// Prepare tag messages
704//-----------------------------------------------------------------------------
6a1f2d82 705static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
15c4dc5a 706{
8f51ddb0 707 ToSendReset();
15c4dc5a 708
709 // Correction bit, might be removed when not needed
710 ToSendStuffBit(0);
711 ToSendStuffBit(0);
712 ToSendStuffBit(0);
713 ToSendStuffBit(0);
714 ToSendStuffBit(1); // 1
715 ToSendStuffBit(0);
716 ToSendStuffBit(0);
717 ToSendStuffBit(0);
8f51ddb0 718
15c4dc5a 719 // Send startbit
72934aa3 720 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 721 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 722
6a1f2d82 723 for(uint16_t i = 0; i < len; i++) {
8f51ddb0 724 uint8_t b = cmd[i];
15c4dc5a 725
726 // Data bits
6a1f2d82 727 for(uint16_t j = 0; j < 8; j++) {
15c4dc5a 728 if(b & 1) {
72934aa3 729 ToSend[++ToSendMax] = SEC_D;
15c4dc5a 730 } else {
72934aa3 731 ToSend[++ToSendMax] = SEC_E;
8f51ddb0
M
732 }
733 b >>= 1;
734 }
15c4dc5a 735
0014cb46 736 // Get the parity bit
6a1f2d82 737 if (parity[i>>3] & (0x80>>(i&0x0007))) {
8f51ddb0 738 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 739 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 740 } else {
72934aa3 741 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 742 LastProxToAirDuration = 8 * ToSendMax;
15c4dc5a 743 }
8f51ddb0 744 }
15c4dc5a 745
8f51ddb0
M
746 // Send stopbit
747 ToSend[++ToSendMax] = SEC_F;
15c4dc5a 748
8f51ddb0
M
749 // Convert from last byte pos to length
750 ToSendMax++;
8f51ddb0
M
751}
752
6a1f2d82 753static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
754{
755 uint8_t par[MAX_PARITY_SIZE];
756
757 GetParity(cmd, len, par);
758 CodeIso14443aAsTagPar(cmd, len, par);
15c4dc5a 759}
760
15c4dc5a 761
8f51ddb0
M
762static void Code4bitAnswerAsTag(uint8_t cmd)
763{
764 int i;
765
5f6d6c90 766 ToSendReset();
8f51ddb0
M
767
768 // Correction bit, might be removed when not needed
769 ToSendStuffBit(0);
770 ToSendStuffBit(0);
771 ToSendStuffBit(0);
772 ToSendStuffBit(0);
773 ToSendStuffBit(1); // 1
774 ToSendStuffBit(0);
775 ToSendStuffBit(0);
776 ToSendStuffBit(0);
777
778 // Send startbit
779 ToSend[++ToSendMax] = SEC_D;
780
781 uint8_t b = cmd;
782 for(i = 0; i < 4; i++) {
783 if(b & 1) {
784 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 785 LastProxToAirDuration = 8 * ToSendMax - 4;
8f51ddb0
M
786 } else {
787 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 788 LastProxToAirDuration = 8 * ToSendMax;
8f51ddb0
M
789 }
790 b >>= 1;
791 }
792
793 // Send stopbit
794 ToSend[++ToSendMax] = SEC_F;
795
5f6d6c90 796 // Convert from last byte pos to length
797 ToSendMax++;
15c4dc5a 798}
799
800//-----------------------------------------------------------------------------
801// Wait for commands from reader
802// Stop when button is pressed
803// Or return TRUE when command is captured
804//-----------------------------------------------------------------------------
6a1f2d82 805static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
15c4dc5a 806{
807 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
808 // only, since we are receiving, not transmitting).
809 // Signal field is off with the appropriate LED
810 LED_D_OFF();
811 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
812
813 // Now run a `software UART' on the stream of incoming samples.
6a1f2d82 814 UartInit(received, parity);
7bc95e2e 815
816 // clear RXRDY:
817 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 818
819 for(;;) {
820 WDT_HIT();
821
822 if(BUTTON_PRESS()) return FALSE;
7bc95e2e 823
15c4dc5a 824 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
7bc95e2e 825 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
826 if(MillerDecoding(b, 0)) {
827 *len = Uart.len;
15c4dc5a 828 return TRUE;
829 }
7bc95e2e 830 }
15c4dc5a 831 }
832}
28afbd2b 833
6a1f2d82 834static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
7bc95e2e 835int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
28afbd2b 836int EmSend4bit(uint8_t resp);
6a1f2d82 837int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
838int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
839int EmSendCmd(uint8_t *resp, uint16_t respLen);
840int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
841bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
842 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
15c4dc5a 843
117d9ec2 844static uint8_t* free_buffer_pointer;
ce02f6f9 845
846typedef struct {
847 uint8_t* response;
848 size_t response_n;
849 uint8_t* modulation;
850 size_t modulation_n;
7bc95e2e 851 uint32_t ProxToAirDuration;
ce02f6f9 852} tag_response_info_t;
853
ce02f6f9 854bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
7bc95e2e 855 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
ce02f6f9 856 // This will need the following byte array for a modulation sequence
857 // 144 data bits (18 * 8)
858 // 18 parity bits
859 // 2 Start and stop
860 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
861 // 1 just for the case
862 // ----------- +
863 // 166 bytes, since every bit that needs to be send costs us a byte
864 //
f71f4deb 865
866
ce02f6f9 867 // Prepare the tag modulation bits from the message
868 CodeIso14443aAsTag(response_info->response,response_info->response_n);
869
870 // Make sure we do not exceed the free buffer space
871 if (ToSendMax > max_buffer_size) {
872 Dbprintf("Out of memory, when modulating bits for tag answer:");
873 Dbhexdump(response_info->response_n,response_info->response,false);
874 return false;
875 }
876
877 // Copy the byte array, used for this modulation to the buffer position
878 memcpy(response_info->modulation,ToSend,ToSendMax);
879
7bc95e2e 880 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
ce02f6f9 881 response_info->modulation_n = ToSendMax;
7bc95e2e 882 response_info->ProxToAirDuration = LastProxToAirDuration;
ce02f6f9 883
884 return true;
885}
886
f71f4deb 887
888// "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
889// Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
890// 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
891// -> need 273 bytes buffer
c9216a92 892// 44 * 8 data bits, 44 * 1 parity bits, 9 start bits, 9 stop bits, 9 correction bits --370
893// 47 * 8 data bits, 47 * 1 parity bits, 10 start bits, 10 stop bits, 10 correction bits
894#define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 453
f71f4deb 895
ce02f6f9 896bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
897 // Retrieve and store the current buffer index
898 response_info->modulation = free_buffer_pointer;
899
900 // Determine the maximum size we can use from our buffer
f71f4deb 901 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
ce02f6f9 902
903 // Forward the prepare tag modulation function to the inner function
f71f4deb 904 if (prepare_tag_modulation(response_info, max_buffer_size)) {
ce02f6f9 905 // Update the free buffer offset
906 free_buffer_pointer += ToSendMax;
907 return true;
908 } else {
909 return false;
910 }
911}
912
15c4dc5a 913//-----------------------------------------------------------------------------
914// Main loop of simulated tag: receive commands from reader, decide what
915// response to send, and send it.
916//-----------------------------------------------------------------------------
0db6ed9a 917void SimulateIso14443aTag(int tagType, int flags, byte_t* data)
15c4dc5a 918{
a126332a 919 uint32_t counters[] = {0,0,0};
d26849d4 920 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
921 // This can be used in a reader-only attack.
922 // (it can also be retrieved via 'hf 14a list', but hey...
923 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0,0,0};
924 uint8_t ar_nr_collected = 0;
925
81cd0474 926 uint8_t sak;
32719adf 927
928 // PACK response to PWD AUTH for EV1/NTAG
e98572a1 929 uint8_t response8[4] = {0,0,0,0};
32719adf 930
81cd0474 931 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
e98572a1 932 uint8_t response1[2] = {0,0};
81cd0474 933
934 switch (tagType) {
935 case 1: { // MIFARE Classic
936 // Says: I am Mifare 1k - original line
937 response1[0] = 0x04;
938 response1[1] = 0x00;
939 sak = 0x08;
940 } break;
941 case 2: { // MIFARE Ultralight
942 // Says: I am a stupid memory tag, no crypto
32719adf 943 response1[0] = 0x44;
81cd0474 944 response1[1] = 0x00;
945 sak = 0x00;
946 } break;
947 case 3: { // MIFARE DESFire
948 // Says: I am a DESFire tag, ph33r me
949 response1[0] = 0x04;
950 response1[1] = 0x03;
951 sak = 0x20;
952 } break;
953 case 4: { // ISO/IEC 14443-4
954 // Says: I am a javacard (JCOP)
955 response1[0] = 0x04;
956 response1[1] = 0x00;
957 sak = 0x28;
958 } break;
3fe4ff4f 959 case 5: { // MIFARE TNP3XXX
960 // Says: I am a toy
961 response1[0] = 0x01;
962 response1[1] = 0x0f;
963 sak = 0x01;
d26849d4 964 } break;
965 case 6: { // MIFARE Mini
966 // Says: I am a Mifare Mini, 320b
967 response1[0] = 0x44;
968 response1[1] = 0x00;
969 sak = 0x09;
970 } break;
32719adf 971 case 7: { // NTAG?
972 // Says: I am a NTAG,
973 response1[0] = 0x44;
974 response1[1] = 0x00;
975 sak = 0x00;
976 // PACK
977 response8[0] = 0x80;
978 response8[1] = 0x80;
979 ComputeCrc14443(CRC_14443_A, response8, 2, &response8[2], &response8[3]);
2b1f4228 980 // uid not supplied then get from emulator memory
981 if (data[0]==0) {
982 uint16_t start = 4 * (0+12);
983 uint8_t emdata[8];
984 emlGetMemBt( emdata, start, sizeof(emdata));
985 memcpy(data, emdata, 3); //uid bytes 0-2
986 memcpy(data+3, emdata+4, 4); //uid bytes 3-7
987 flags |= FLAG_7B_UID_IN_DATA;
988 }
32719adf 989 } break;
81cd0474 990 default: {
991 Dbprintf("Error: unkown tagtype (%d)",tagType);
992 return;
993 } break;
994 }
995
996 // The second response contains the (mandatory) first 24 bits of the UID
c8b6da22 997 uint8_t response2[5] = {0x00};
81cd0474 998
999 // Check if the uid uses the (optional) part
c8b6da22 1000 uint8_t response2a[5] = {0x00};
1001
d26849d4 1002 if (flags & FLAG_7B_UID_IN_DATA) {
81cd0474 1003 response2[0] = 0x88;
d26849d4 1004 response2[1] = data[0];
1005 response2[2] = data[1];
1006 response2[3] = data[2];
1007
1008 response2a[0] = data[3];
1009 response2a[1] = data[4];
1010 response2a[2] = data[5];
c3c241f3 1011 response2a[3] = data[6]; //??
81cd0474 1012 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
1013
1014 // Configure the ATQA and SAK accordingly
1015 response1[0] |= 0x40;
1016 sak |= 0x04;
1017 } else {
d26849d4 1018 memcpy(response2, data, 4);
1019 //num_to_bytes(uid_1st,4,response2);
81cd0474 1020 // Configure the ATQA and SAK accordingly
1021 response1[0] &= 0xBF;
1022 sak &= 0xFB;
1023 }
1024
1025 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
1026 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
1027
1028 // Prepare the mandatory SAK (for 4 and 7 byte UID)
c8b6da22 1029 uint8_t response3[3] = {0x00};
81cd0474 1030 response3[0] = sak;
1031 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
1032
1033 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
c8b6da22 1034 uint8_t response3a[3] = {0x00};
81cd0474 1035 response3a[0] = sak & 0xFB;
1036 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
1037
0de8e387 1038 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
6a1f2d82 1039 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1040 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1041 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1042 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1043 // TC(1) = 0x02: CID supported, NAD not supported
ce02f6f9 1044 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1045
2b1f4228 1046 // Prepare GET_VERSION (different for UL EV-1 / NTAG)
32719adf 1047 //uint8_t response7_EV1[] = {0x00, 0x04, 0x03, 0x01, 0x01, 0x00, 0x0b, 0x03, 0xfd, 0xf7}; //EV1 48bytes VERSION.
2b1f4228 1048 //uint8_t response7_NTAG[] = {0x00, 0x04, 0x04, 0x02, 0x01, 0x00, 0x11, 0x03, 0x01, 0x9e}; //NTAG 215
32719adf 1049
c9216a92 1050 // Prepare CHK_TEARING
2b1f4228 1051 //uint8_t response9[] = {0xBD,0x90,0x3f};
c9216a92 1052
1053 #define TAG_RESPONSE_COUNT 10
7bc95e2e 1054 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1055 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1056 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1057 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1058 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1059 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1060 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1061 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
2b1f4228 1062 //{ .response = response7_NTAG, .response_n = sizeof(response7_NTAG)}, // EV1/NTAG GET_VERSION response
495d7f13 1063 { .response = response8, .response_n = sizeof(response8) } // EV1/NTAG PACK response
2b1f4228 1064 //{ .response = response9, .response_n = sizeof(response9) } // EV1/NTAG CHK_TEAR response
7bc95e2e 1065 };
1066
1067 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1068 // Such a response is less time critical, so we can prepare them on the fly
1069 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1070 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1071 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1072 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1073 tag_response_info_t dynamic_response_info = {
1074 .response = dynamic_response_buffer,
1075 .response_n = 0,
1076 .modulation = dynamic_modulation_buffer,
1077 .modulation_n = 0
1078 };
ce02f6f9 1079
99cf19d9 1080 // We need to listen to the high-frequency, peak-detected path.
1081 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1082
f71f4deb 1083 BigBuf_free_keep_EM();
1084
1085 // allocate buffers:
1086 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1087 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1088 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1089
1090 // clear trace
3000dc4e
MHS
1091 clear_trace();
1092 set_tracing(TRUE);
f71f4deb 1093
7bc95e2e 1094 // Prepare the responses of the anticollision phase
ce02f6f9 1095 // there will be not enough time to do this at the moment the reader sends it REQA
495d7f13 1096 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++)
7bc95e2e 1097 prepare_allocated_tag_modulation(&responses[i]);
15c4dc5a 1098
7bc95e2e 1099 int len = 0;
15c4dc5a 1100
1101 // To control where we are in the protocol
1102 int order = 0;
1103 int lastorder;
1104
1105 // Just to allow some checks
1106 int happened = 0;
1107 int happened2 = 0;
81cd0474 1108 int cmdsRecvd = 0;
15c4dc5a 1109
254b70a4 1110 cmdsRecvd = 0;
7bc95e2e 1111 tag_response_info_t* p_response;
15c4dc5a 1112
254b70a4 1113 LED_A_ON();
1114 for(;;) {
7bc95e2e 1115 // Clean receive command buffer
6a1f2d82 1116 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
ce02f6f9 1117 DbpString("Button press");
254b70a4 1118 break;
1119 }
7bc95e2e 1120
1121 p_response = NULL;
1122
254b70a4 1123 // Okay, look at the command now.
1124 lastorder = order;
1125 if(receivedCmd[0] == 0x26) { // Received a REQUEST
ce02f6f9 1126 p_response = &responses[0]; order = 1;
254b70a4 1127 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
ce02f6f9 1128 p_response = &responses[0]; order = 6;
254b70a4 1129 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
ce02f6f9 1130 p_response = &responses[1]; order = 2;
6a1f2d82 1131 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
ce02f6f9 1132 p_response = &responses[2]; order = 20;
254b70a4 1133 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
ce02f6f9 1134 p_response = &responses[3]; order = 3;
254b70a4 1135 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
ce02f6f9 1136 p_response = &responses[4]; order = 30;
254b70a4 1137 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
32719adf 1138 uint8_t block = receivedCmd[1];
2b1f4228 1139 // if Ultralight or NTAG (4 byte blocks)
1140 if ( tagType == 7 || tagType == 2 ) {
1141 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1142 uint16_t start = 4 * (block+12);
5e428463 1143 uint8_t emdata[MAX_MIFARE_FRAME_SIZE];
1144 emlGetMemBt( emdata, start, 16);
1145 AppendCrc14443a(emdata, 16);
1146 EmSendCmdEx(emdata, sizeof(emdata), false);
2b1f4228 1147 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
32719adf 1148 p_response = NULL;
2b1f4228 1149 } else { // all other tags (16 byte block tags)
1150 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
32719adf 1151 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1152 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1153 p_response = NULL;
1154 }
a126332a 1155 } else if(receivedCmd[0] == 0x3A) { // Received a FAST READ (ranged read)
5e428463 1156
1157 uint8_t emdata[MAX_FRAME_SIZE];
2b1f4228 1158 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1159 int start = (receivedCmd[1]+12) * 4;
ce3d6bd2 1160 int len = (receivedCmd[2] - receivedCmd[1] + 1) * 4;
5e428463 1161 emlGetMemBt( emdata, start, len);
1162 AppendCrc14443a(emdata, len);
1163 EmSendCmdEx(emdata, len+2, false);
1164 p_response = NULL;
1165
839a53ae 1166 } else if(receivedCmd[0] == 0x3C && tagType == 7) { // Received a READ SIGNATURE --
1167 // ECC data, taken from a NTAG215 amiibo token. might work. LEN: 32, + 2 crc
2b1f4228 1168 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1169 uint16_t start = 4 * 4;
1170 uint8_t emdata[34];
1171 emlGetMemBt( emdata, start, 32);
1172 AppendCrc14443a(emdata, 32);
1173 EmSendCmdEx(emdata, sizeof(emdata), false);
1174 //uint8_t data[] = {0x56,0x06,0xa6,0x4f,0x43,0x32,0x53,0x6f,
1175 // 0x43,0xda,0x45,0xd6,0x61,0x38,0xaa,0x1e,
1176 // 0xcf,0xd3,0x61,0x36,0xca,0x5f,0xbb,0x05,
1177 // 0xce,0x21,0x24,0x5b,0xa6,0x7a,0x79,0x07,
1178 // 0x00,0x00};
1179 //AppendCrc14443a(data, sizeof(data)-2);
1180 //EmSendCmdEx(data,sizeof(data),false);
839a53ae 1181 p_response = NULL;
a126332a 1182 } else if (receivedCmd[0] == 0x39 && tagType == 7) { // Received a READ COUNTER --
e9a92fe2 1183 uint8_t index = receivedCmd[1];
a126332a 1184 uint8_t data[] = {0x00,0x00,0x00,0x14,0xa5};
e9a92fe2 1185 if ( counters[index] > 0) {
1186 num_to_bytes(counters[index], 3, data);
1187 AppendCrc14443a(data, sizeof(data)-2);
1188 }
a126332a 1189 EmSendCmdEx(data,sizeof(data),false);
1190 p_response = NULL;
1191 } else if (receivedCmd[0] == 0xA5 && tagType == 7) { // Received a INC COUNTER --
ce3d6bd2 1192 // number of counter
a126332a 1193 uint8_t counter = receivedCmd[1];
1194 uint32_t val = bytes_to_num(receivedCmd+2,4);
1195 counters[counter] = val;
1196
ce3d6bd2 1197 // send ACK
1198 uint8_t ack[] = {0x0a};
1199 EmSendCmdEx(ack,sizeof(ack),false);
1200 p_response = NULL;
1201
c9216a92 1202 } else if(receivedCmd[0] == 0x3E && tagType == 7) { // Received a CHECK_TEARING_EVENT --
2b1f4228 1203 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1204 uint8_t emdata[3];
1205 uint8_t counter=0;
1206 if (receivedCmd[1]<3) counter = receivedCmd[1];
1207 emlGetMemBt( emdata, 10+counter, 1);
1208 AppendCrc14443a(emdata, sizeof(emdata)-2);
1209 EmSendCmdEx(emdata, sizeof(emdata), false);
1210 p_response = NULL;
1211 //p_response = &responses[9];
1212
254b70a4 1213 } else if(receivedCmd[0] == 0x50) { // Received a HALT
3fe4ff4f 1214
7bc95e2e 1215 if (tracing) {
6a1f2d82 1216 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1217 }
1218 p_response = NULL;
254b70a4 1219 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
32719adf 1220
1221 if ( tagType == 7 ) { // IF NTAG /EV1 0x60 == GET_VERSION, not a authentication request.
2b1f4228 1222 uint8_t emdata[10];
1223 emlGetMemBt( emdata, 0, 8 );
1224 AppendCrc14443a(emdata, sizeof(emdata)-2);
1225 EmSendCmdEx(emdata, sizeof(emdata), false);
1226 p_response = NULL;
1227 //p_response = &responses[7];
32719adf 1228 } else {
1229 p_response = &responses[5]; order = 7;
1230 }
254b70a4 1231 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
7bc95e2e 1232 if (tagType == 1 || tagType == 2) { // RATS not supported
1233 EmSend4bit(CARD_NACK_NA);
1234 p_response = NULL;
1235 } else {
1236 p_response = &responses[6]; order = 70;
1237 }
6a1f2d82 1238 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
7bc95e2e 1239 if (tracing) {
6a1f2d82 1240 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1241 }
d26849d4 1242 uint32_t nonce = bytes_to_num(response5,4);
7bc95e2e 1243 uint32_t nr = bytes_to_num(receivedCmd,4);
1244 uint32_t ar = bytes_to_num(receivedCmd+4,4);
d26849d4 1245 //Dbprintf("Auth attempt {nonce}{nr}{ar}: %08x %08x %08x", nonce, nr, ar);
1246
1247 if(flags & FLAG_NR_AR_ATTACK )
1248 {
1249 if(ar_nr_collected < 2){
1250 // Avoid duplicates... probably not necessary, nr should vary.
1251 //if(ar_nr_responses[3] != nr){
1252 ar_nr_responses[ar_nr_collected*5] = 0;
1253 ar_nr_responses[ar_nr_collected*5+1] = 0;
1254 ar_nr_responses[ar_nr_collected*5+2] = nonce;
1255 ar_nr_responses[ar_nr_collected*5+3] = nr;
1256 ar_nr_responses[ar_nr_collected*5+4] = ar;
1257 ar_nr_collected++;
1258 //}
1259 }
1260
1261 if(ar_nr_collected > 1 ) {
1262
1263 if (MF_DBGLEVEL >= 2) {
1264 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
1265 Dbprintf("../tools/mfkey/mfkey32 %07x%08x %08x %08x %08x %08x %08x",
1266 ar_nr_responses[0], // UID1
1267 ar_nr_responses[1], // UID2
1268 ar_nr_responses[2], // NT
1269 ar_nr_responses[3], // AR1
1270 ar_nr_responses[4], // NR1
1271 ar_nr_responses[8], // AR2
1272 ar_nr_responses[9] // NR2
1273 );
7838f4be 1274 Dbprintf("../tools/mfkey/mfkey32v2 %06x%08x %08x %08x %08x %08x %08x %08x",
1275 ar_nr_responses[0], // UID1
1276 ar_nr_responses[1], // UID2
1277 ar_nr_responses[2], // NT1
1278 ar_nr_responses[3], // AR1
1279 ar_nr_responses[4], // NR1
1280 ar_nr_responses[7], // NT2
1281 ar_nr_responses[8], // AR2
1282 ar_nr_responses[9] // NR2
1283 );
d26849d4 1284 }
1285 uint8_t len = ar_nr_collected*5*4;
1286 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,len,0,&ar_nr_responses,len);
1287 ar_nr_collected = 0;
1288 memset(ar_nr_responses, 0x00, len);
d26849d4 1289 }
1290 }
32719adf 1291 } else if (receivedCmd[0] == 0x1a ) // ULC authentication
1292 {
1293
1294 }
1295 else if (receivedCmd[0] == 0x1b) // NTAG / EV-1 authentication
1296 {
1297 if ( tagType == 7 ) {
2b1f4228 1298 uint16_t start = 13; //first 4 blocks of emu are [getversion answer - check tearing - pack - 0x00]
1299 uint8_t emdata[4];
1300 emlGetMemBt( emdata, start, 2);
1301 AppendCrc14443a(emdata, 2);
1302 EmSendCmdEx(emdata, sizeof(emdata), false);
1303 p_response = NULL;
1304 //p_response = &responses[8]; // PACK response
ce3d6bd2 1305 uint32_t pwd = bytes_to_num(receivedCmd+1,4);
e98572a1 1306
1307 if ( MF_DBGLEVEL >= 3) Dbprintf("Auth attempt: %08x", pwd);
32719adf 1308 }
2b1f4228 1309 } else {
7bc95e2e 1310 // Check for ISO 14443A-4 compliant commands, look at left nibble
1311 switch (receivedCmd[0]) {
7838f4be 1312 case 0x02:
1313 case 0x03: { // IBlock (command no CID)
1314 dynamic_response_info.response[0] = receivedCmd[0];
1315 dynamic_response_info.response[1] = 0x90;
1316 dynamic_response_info.response[2] = 0x00;
1317 dynamic_response_info.response_n = 3;
1318 } break;
7bc95e2e 1319 case 0x0B:
7838f4be 1320 case 0x0A: { // IBlock (command CID)
7bc95e2e 1321 dynamic_response_info.response[0] = receivedCmd[0];
1322 dynamic_response_info.response[1] = 0x00;
1323 dynamic_response_info.response[2] = 0x90;
1324 dynamic_response_info.response[3] = 0x00;
1325 dynamic_response_info.response_n = 4;
1326 } break;
1327
1328 case 0x1A:
1329 case 0x1B: { // Chaining command
1330 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1331 dynamic_response_info.response_n = 2;
1332 } break;
1333
1334 case 0xaa:
1335 case 0xbb: {
1336 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1337 dynamic_response_info.response_n = 2;
1338 } break;
1339
7838f4be 1340 case 0xBA: { // ping / pong
1341 dynamic_response_info.response[0] = 0xAB;
1342 dynamic_response_info.response[1] = 0x00;
1343 dynamic_response_info.response_n = 2;
7bc95e2e 1344 } break;
1345
1346 case 0xCA:
1347 case 0xC2: { // Readers sends deselect command
7838f4be 1348 dynamic_response_info.response[0] = 0xCA;
1349 dynamic_response_info.response[1] = 0x00;
1350 dynamic_response_info.response_n = 2;
7bc95e2e 1351 } break;
1352
1353 default: {
1354 // Never seen this command before
1355 if (tracing) {
6a1f2d82 1356 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1357 }
1358 Dbprintf("Received unknown command (len=%d):",len);
1359 Dbhexdump(len,receivedCmd,false);
1360 // Do not respond
1361 dynamic_response_info.response_n = 0;
1362 } break;
1363 }
ce02f6f9 1364
7bc95e2e 1365 if (dynamic_response_info.response_n > 0) {
1366 // Copy the CID from the reader query
1367 dynamic_response_info.response[1] = receivedCmd[1];
ce02f6f9 1368
7bc95e2e 1369 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1370 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1371 dynamic_response_info.response_n += 2;
ce02f6f9 1372
7bc95e2e 1373 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1374 Dbprintf("Error preparing tag response");
1375 if (tracing) {
6a1f2d82 1376 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1377 }
1378 break;
1379 }
1380 p_response = &dynamic_response_info;
1381 }
81cd0474 1382 }
15c4dc5a 1383
1384 // Count number of wakeups received after a halt
1385 if(order == 6 && lastorder == 5) { happened++; }
1386
1387 // Count number of other messages after a halt
1388 if(order != 6 && lastorder == 5) { happened2++; }
1389
15c4dc5a 1390 if(cmdsRecvd > 999) {
1391 DbpString("1000 commands later...");
254b70a4 1392 break;
15c4dc5a 1393 }
ce02f6f9 1394 cmdsRecvd++;
1395
1396 if (p_response != NULL) {
7bc95e2e 1397 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1398 // do the tracing for the previous reader request and this tag answer:
6a1f2d82 1399 uint8_t par[MAX_PARITY_SIZE];
1400 GetParity(p_response->response, p_response->response_n, par);
3fe4ff4f 1401
7bc95e2e 1402 EmLogTrace(Uart.output,
1403 Uart.len,
1404 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1405 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1406 Uart.parity,
7bc95e2e 1407 p_response->response,
1408 p_response->response_n,
1409 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1410 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1411 par);
7bc95e2e 1412 }
1413
1414 if (!tracing) {
1415 Dbprintf("Trace Full. Simulation stopped.");
1416 break;
1417 }
1418 }
15c4dc5a 1419
d26849d4 1420 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
5ee53a0e 1421 set_tracing(FALSE);
f71f4deb 1422 BigBuf_free_keep_EM();
c9216a92 1423 LED_A_OFF();
1424
0de8e387 1425 if (MF_DBGLEVEL >= 4){
5ee53a0e 1426 Dbprintf("-[ Wake ups after halt [%d]", happened);
1427 Dbprintf("-[ Messages after halt [%d]", happened2);
1428 Dbprintf("-[ Num of received cmd [%d]", cmdsRecvd);
0de8e387 1429 }
15c4dc5a 1430}
1431
9492e0b0 1432
1433// prepare a delayed transfer. This simply shifts ToSend[] by a number
1434// of bits specified in the delay parameter.
1435void PrepareDelayedTransfer(uint16_t delay)
1436{
1437 uint8_t bitmask = 0;
1438 uint8_t bits_to_shift = 0;
1439 uint8_t bits_shifted = 0;
2285d9dd 1440
9492e0b0 1441 delay &= 0x07;
1442 if (delay) {
1443 for (uint16_t i = 0; i < delay; i++) {
1444 bitmask |= (0x01 << i);
1445 }
7bc95e2e 1446 ToSend[ToSendMax++] = 0x00;
9492e0b0 1447 for (uint16_t i = 0; i < ToSendMax; i++) {
1448 bits_to_shift = ToSend[i] & bitmask;
1449 ToSend[i] = ToSend[i] >> delay;
1450 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1451 bits_shifted = bits_to_shift;
1452 }
1453 }
1454}
1455
7bc95e2e 1456
1457//-------------------------------------------------------------------------------------
15c4dc5a 1458// Transmit the command (to the tag) that was placed in ToSend[].
9492e0b0 1459// Parameter timing:
7bc95e2e 1460// if NULL: transfer at next possible time, taking into account
1461// request guard time and frame delay time
1462// if == 0: transfer immediately and return time of transfer
9492e0b0 1463// if != 0: delay transfer until time specified
7bc95e2e 1464//-------------------------------------------------------------------------------------
6a1f2d82 1465static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
15c4dc5a 1466{
9492e0b0 1467 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
e30c654b 1468
7bc95e2e 1469 uint32_t ThisTransferTime = 0;
e30c654b 1470
9492e0b0 1471 if (timing) {
1472 if(*timing == 0) { // Measure time
7bc95e2e 1473 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
9492e0b0 1474 } else {
1475 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1476 }
7bc95e2e 1477 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1478 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1479 LastTimeProxToAirStart = *timing;
1480 } else {
1481 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1482 while(GetCountSspClk() < ThisTransferTime);
1483 LastTimeProxToAirStart = ThisTransferTime;
9492e0b0 1484 }
1485
7bc95e2e 1486 // clear TXRDY
1487 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1488
7bc95e2e 1489 uint16_t c = 0;
9492e0b0 1490 for(;;) {
1491 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1492 AT91C_BASE_SSC->SSC_THR = cmd[c];
1493 c++;
5ebcb867 1494 if(c >= len)
9492e0b0 1495 break;
9492e0b0 1496 }
1497 }
7bc95e2e 1498
1499 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
15c4dc5a 1500}
1501
7bc95e2e 1502
15c4dc5a 1503//-----------------------------------------------------------------------------
195af472 1504// Prepare reader command (in bits, support short frames) to send to FPGA
15c4dc5a 1505//-----------------------------------------------------------------------------
6a1f2d82 1506void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
15c4dc5a 1507{
7bc95e2e 1508 int i, j;
5ebcb867 1509 int last = 0;
7bc95e2e 1510 uint8_t b;
e30c654b 1511
7bc95e2e 1512 ToSendReset();
e30c654b 1513
7bc95e2e 1514 // Start of Communication (Seq. Z)
1515 ToSend[++ToSendMax] = SEC_Z;
1516 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
7bc95e2e 1517
1518 size_t bytecount = nbytes(bits);
1519 // Generate send structure for the data bits
1520 for (i = 0; i < bytecount; i++) {
1521 // Get the current byte to send
1522 b = cmd[i];
1523 size_t bitsleft = MIN((bits-(i*8)),8);
1524
1525 for (j = 0; j < bitsleft; j++) {
1526 if (b & 1) {
1527 // Sequence X
1528 ToSend[++ToSendMax] = SEC_X;
1529 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1530 last = 1;
1531 } else {
1532 if (last == 0) {
1533 // Sequence Z
1534 ToSend[++ToSendMax] = SEC_Z;
1535 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1536 } else {
1537 // Sequence Y
1538 ToSend[++ToSendMax] = SEC_Y;
1539 last = 0;
1540 }
1541 }
1542 b >>= 1;
1543 }
1544
6a1f2d82 1545 // Only transmit parity bit if we transmitted a complete byte
0ec548dc 1546 if (j == 8 && parity != NULL) {
7bc95e2e 1547 // Get the parity bit
6a1f2d82 1548 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
7bc95e2e 1549 // Sequence X
1550 ToSend[++ToSendMax] = SEC_X;
1551 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1552 last = 1;
1553 } else {
1554 if (last == 0) {
1555 // Sequence Z
1556 ToSend[++ToSendMax] = SEC_Z;
1557 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1558 } else {
1559 // Sequence Y
1560 ToSend[++ToSendMax] = SEC_Y;
1561 last = 0;
1562 }
1563 }
1564 }
1565 }
e30c654b 1566
7bc95e2e 1567 // End of Communication: Logic 0 followed by Sequence Y
1568 if (last == 0) {
1569 // Sequence Z
1570 ToSend[++ToSendMax] = SEC_Z;
1571 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1572 } else {
1573 // Sequence Y
1574 ToSend[++ToSendMax] = SEC_Y;
1575 last = 0;
1576 }
1577 ToSend[++ToSendMax] = SEC_Y;
e30c654b 1578
7bc95e2e 1579 // Convert to length of command:
1580 ToSendMax++;
15c4dc5a 1581}
1582
195af472 1583//-----------------------------------------------------------------------------
1584// Prepare reader command to send to FPGA
1585//-----------------------------------------------------------------------------
6a1f2d82 1586void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
195af472 1587{
6a1f2d82 1588 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
195af472 1589}
1590
0c8d25eb 1591
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1592//-----------------------------------------------------------------------------
1593// Wait for commands from reader
1594// Stop when button is pressed (return 1) or field was gone (return 2)
1595// Or return 0 when command is captured
1596//-----------------------------------------------------------------------------
6a1f2d82 1597static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
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1598{
1599 *len = 0;
1600
1601 uint32_t timer = 0, vtime = 0;
1602 int analogCnt = 0;
1603 int analogAVG = 0;
1604
1605 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1606 // only, since we are receiving, not transmitting).
1607 // Signal field is off with the appropriate LED
1608 LED_D_OFF();
1609 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1610
1611 // Set ADC to read field strength
1612 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1613 AT91C_BASE_ADC->ADC_MR =
0c8d25eb 1614 ADC_MODE_PRESCALE(63) |
1615 ADC_MODE_STARTUP_TIME(1) |
1616 ADC_MODE_SAMPLE_HOLD_TIME(15);
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1617 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1618 // start ADC
1619 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1620
1621 // Now run a 'software UART' on the stream of incoming samples.
6a1f2d82 1622 UartInit(received, parity);
7bc95e2e 1623
1624 // Clear RXRDY:
1625 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1626
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1627 for(;;) {
1628 WDT_HIT();
1629
1630 if (BUTTON_PRESS()) return 1;
1631
1632 // test if the field exists
1633 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1634 analogCnt++;
1635 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1636 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1637 if (analogCnt >= 32) {
0c8d25eb 1638 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
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1639 vtime = GetTickCount();
1640 if (!timer) timer = vtime;
1641 // 50ms no field --> card to idle state
1642 if (vtime - timer > 50) return 2;
1643 } else
1644 if (timer) timer = 0;
1645 analogCnt = 0;
1646 analogAVG = 0;
1647 }
1648 }
7bc95e2e 1649
9ca155ba 1650 // receive and test the miller decoding
7bc95e2e 1651 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1652 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1653 if(MillerDecoding(b, 0)) {
1654 *len = Uart.len;
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1655 return 0;
1656 }
7bc95e2e 1657 }
1658
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1659 }
1660}
1661
9ca155ba 1662
6a1f2d82 1663static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
7bc95e2e 1664{
1665 uint8_t b;
1666 uint16_t i = 0;
1667 uint32_t ThisTransferTime;
1668
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1669 // Modulate Manchester
1670 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
7bc95e2e 1671
1672 // include correction bit if necessary
1673 if (Uart.parityBits & 0x01) {
1674 correctionNeeded = TRUE;
1675 }
1676 if(correctionNeeded) {
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1677 // 1236, so correction bit needed
1678 i = 0;
7bc95e2e 1679 } else {
1680 i = 1;
9ca155ba 1681 }
7bc95e2e 1682
d714d3ef 1683 // clear receiving shift register and holding register
7bc95e2e 1684 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1685 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1686 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1687 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
9ca155ba 1688
7bc95e2e 1689 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1690 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1691 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1692 if (AT91C_BASE_SSC->SSC_RHR) break;
1693 }
1694
1695 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1696
1697 // Clear TXRDY:
1698 AT91C_BASE_SSC->SSC_THR = SEC_F;
1699
9ca155ba 1700 // send cycle
bb42a03e 1701 for(; i < respLen; ) {
9ca155ba 1702 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
7bc95e2e 1703 AT91C_BASE_SSC->SSC_THR = resp[i++];
1704 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba 1705 }
7bc95e2e 1706
17ad0e09 1707 if(BUTTON_PRESS()) break;
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1708 }
1709
7bc95e2e 1710 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
0c8d25eb 1711 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
1712 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
7bc95e2e 1713 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1714 AT91C_BASE_SSC->SSC_THR = SEC_F;
1715 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1716 i++;
1717 }
1718 }
0c8d25eb 1719
7bc95e2e 1720 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1721
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1722 return 0;
1723}
1724
7bc95e2e 1725int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1726 Code4bitAnswerAsTag(resp);
0a39986e 1727 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1728 // do the tracing for the previous reader request and this tag answer:
5ebcb867 1729 uint8_t par[1] = {0x00};
6a1f2d82 1730 GetParity(&resp, 1, par);
7bc95e2e 1731 EmLogTrace(Uart.output,
1732 Uart.len,
1733 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1734 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1735 Uart.parity,
7bc95e2e 1736 &resp,
1737 1,
1738 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1739 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1740 par);
0a39986e 1741 return res;
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1742}
1743
8f51ddb0 1744int EmSend4bit(uint8_t resp){
7bc95e2e 1745 return EmSend4bitEx(resp, false);
8f51ddb0
M
1746}
1747
6a1f2d82 1748int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
7bc95e2e 1749 CodeIso14443aAsTagPar(resp, respLen, par);
8f51ddb0 1750 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1751 // do the tracing for the previous reader request and this tag answer:
1752 EmLogTrace(Uart.output,
1753 Uart.len,
1754 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1755 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1756 Uart.parity,
7bc95e2e 1757 resp,
1758 respLen,
1759 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1760 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1761 par);
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1762 return res;
1763}
1764
6a1f2d82 1765int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
5ebcb867 1766 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1767 GetParity(resp, respLen, par);
1768 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
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1769}
1770
6a1f2d82 1771int EmSendCmd(uint8_t *resp, uint16_t respLen){
5ebcb867 1772 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1773 GetParity(resp, respLen, par);
1774 return EmSendCmdExPar(resp, respLen, false, par);
8f51ddb0
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1775}
1776
6a1f2d82 1777int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
7bc95e2e 1778 return EmSendCmdExPar(resp, respLen, false, par);
1779}
1780
6a1f2d82 1781bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1782 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
7bc95e2e 1783{
1784 if (tracing) {
1785 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1786 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1787 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1788 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1789 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1790 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1791 reader_EndTime = tag_StartTime - exact_fdt;
1792 reader_StartTime = reader_EndTime - reader_modlen;
5ebcb867 1793
1794 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE))
7bc95e2e 1795 return FALSE;
5ebcb867 1796 else
1797 return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1798
7bc95e2e 1799 } else {
1800 return TRUE;
1801 }
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1802}
1803
15c4dc5a 1804//-----------------------------------------------------------------------------
1805// Wait a certain time for tag response
1806// If a response is captured return TRUE
e691fc45 1807// If it takes too long return FALSE
15c4dc5a 1808//-----------------------------------------------------------------------------
6a1f2d82 1809static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
15c4dc5a 1810{
46c65fed 1811 uint32_t c = 0x00;
e691fc45 1812
15c4dc5a 1813 // Set FPGA mode to "reader listen mode", no modulation (listen
534983d7 1814 // only, since we are receiving, not transmitting).
1815 // Signal field is on with the appropriate LED
1816 LED_D_ON();
1817 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1c611bbd 1818
534983d7 1819 // Now get the answer from the card
6a1f2d82 1820 DemodInit(receivedResponse, receivedResponsePar);
15c4dc5a 1821
7bc95e2e 1822 // clear RXRDY:
1823 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1824
15c4dc5a 1825 for(;;) {
534983d7 1826 WDT_HIT();
15c4dc5a 1827
534983d7 1828 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
534983d7 1829 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 1830 if(ManchesterDecoding(b, offset, 0)) {
1831 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
15c4dc5a 1832 return TRUE;
19a700a8 1833 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
7bc95e2e 1834 return FALSE;
15c4dc5a 1835 }
534983d7 1836 }
1837 }
15c4dc5a 1838}
1839
6a1f2d82 1840void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
15c4dc5a 1841{
6a1f2d82 1842 CodeIso14443aBitsAsReaderPar(frame, bits, par);
dfc3c505 1843
7bc95e2e 1844 // Send command to tag
1845 TransmitFor14443a(ToSend, ToSendMax, timing);
1846 if(trigger)
1847 LED_A_ON();
dfc3c505 1848
7bc95e2e 1849 // Log reader command in trace buffer
5ebcb867 1850 if (tracing)
6a1f2d82 1851 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
15c4dc5a 1852}
1853
6a1f2d82 1854void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
dfc3c505 1855{
6a1f2d82 1856 ReaderTransmitBitsPar(frame, len*8, par, timing);
dfc3c505 1857}
15c4dc5a 1858
6a1f2d82 1859void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
e691fc45 1860{
1861 // Generate parity and redirect
5ebcb867 1862 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1863 GetParity(frame, len/8, par);
1864 ReaderTransmitBitsPar(frame, len, par, timing);
e691fc45 1865}
1866
6a1f2d82 1867void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
15c4dc5a 1868{
1869 // Generate parity and redirect
5ebcb867 1870 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1871 GetParity(frame, len, par);
1872 ReaderTransmitBitsPar(frame, len*8, par, timing);
15c4dc5a 1873}
1874
6a1f2d82 1875int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
e691fc45 1876{
5ebcb867 1877 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset))
1878 return FALSE;
1879
1880 if (tracing)
6a1f2d82 1881 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
5ebcb867 1882
e691fc45 1883 return Demod.len;
1884}
1885
6a1f2d82 1886int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
15c4dc5a 1887{
5ebcb867 1888 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0))
1889 return FALSE;
1890
1891 if (tracing)
6a1f2d82 1892 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
5ebcb867 1893
e691fc45 1894 return Demod.len;
f89c7050
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1895}
1896
c188b1b9 1897// performs iso14443a anticollision (optional) and card select procedure
1898// fills the uid and cuid pointer unless NULL
1899// fills the card info record unless NULL
1900// if anticollision is false, then the UID must be provided in uid_ptr[]
1901// and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
1902int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr, bool anticollision, uint8_t num_cascades) {
6a1f2d82 1903 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1904 uint8_t sel_all[] = { 0x93,0x20 };
1905 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1906 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
f71f4deb 1907 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1908 uint8_t resp_par[MAX_PARITY_SIZE];
6a1f2d82 1909 byte_t uid_resp[4];
1910 size_t uid_resp_len;
1911
1912 uint8_t sak = 0x04; // cascade uid
1913 int cascade_level = 0;
1914 int len;
1915
1916 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
c188b1b9 1917 ReaderTransmitBitsPar(wupa, 7, NULL, NULL);
7bc95e2e 1918
6a1f2d82 1919 // Receive the ATQA
1920 if(!ReaderReceive(resp, resp_par)) return 0;
6a1f2d82 1921
1922 if(p_hi14a_card) {
1923 memcpy(p_hi14a_card->atqa, resp, 2);
1924 p_hi14a_card->uidlen = 0;
1925 memset(p_hi14a_card->uid,0,10);
1926 }
5f6d6c90 1927
c188b1b9 1928 if (anticollision) {
6a1f2d82 1929 // clear uid
1930 if (uid_ptr) {
1931 memset(uid_ptr,0,10);
1932 }
c188b1b9 1933 }
79a73ab2 1934
0ec548dc 1935 // check for proprietary anticollision:
1936 if ((resp[0] & 0x1F) == 0) {
1937 return 3;
1938 }
1939
6a1f2d82 1940 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1941 // which case we need to make a cascade 2 request and select - this is a long UID
1942 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1943 for(; sak & 0x04; cascade_level++) {
1944 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1945 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1946
c188b1b9 1947 if (anticollision) {
6a1f2d82 1948 // SELECT_ALL
1949 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1950 if (!ReaderReceive(resp, resp_par)) return 0;
1951
1952 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1953 memset(uid_resp, 0, 4);
1954 uint16_t uid_resp_bits = 0;
1955 uint16_t collision_answer_offset = 0;
1956 // anti-collision-loop:
1957 while (Demod.collisionPos) {
1958 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1959 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1960 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
758f1fd1 1961 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
6a1f2d82 1962 }
1963 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1964 uid_resp_bits++;
1965 // construct anticollosion command:
1966 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1967 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1968 sel_uid[2+i] = uid_resp[i];
1969 }
1970 collision_answer_offset = uid_resp_bits%8;
1971 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1972 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
e691fc45 1973 }
6a1f2d82 1974 // finally, add the last bits and BCC of the UID
1975 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1976 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1977 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
e691fc45 1978 }
e691fc45 1979
6a1f2d82 1980 } else { // no collision, use the response to SELECT_ALL as current uid
1981 memcpy(uid_resp, resp, 4);
1982 }
c188b1b9 1983 } else {
1984 if (cascade_level < num_cascades - 1) {
1985 uid_resp[0] = 0x88;
1986 memcpy(uid_resp+1, uid_ptr+cascade_level*3, 3);
1987 } else {
1988 memcpy(uid_resp, uid_ptr+cascade_level*3, 4);
1989 }
1990 }
6a1f2d82 1991 uid_resp_len = 4;
5f6d6c90 1992
6a1f2d82 1993 // calculate crypto UID. Always use last 4 Bytes.
1994 if(cuid_ptr) {
1995 *cuid_ptr = bytes_to_num(uid_resp, 4);
1996 }
e30c654b 1997
6a1f2d82 1998 // Construct SELECT UID command
1999 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
c188b1b9 2000 memcpy(sel_uid+2, uid_resp, 4); // the UID received during anticollision, or the provided UID
6a1f2d82 2001 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
2002 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
2003 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
2004
2005 // Receive the SAK
2006 if (!ReaderReceive(resp, resp_par)) return 0;
2007 sak = resp[0];
2008
52ab55ab 2009 // Test if more parts of the uid are coming
6a1f2d82 2010 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
2011 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
2012 // http://www.nxp.com/documents/application_note/AN10927.pdf
6a1f2d82 2013 uid_resp[0] = uid_resp[1];
2014 uid_resp[1] = uid_resp[2];
2015 uid_resp[2] = uid_resp[3];
6a1f2d82 2016 uid_resp_len = 3;
2017 }
5f6d6c90 2018
c188b1b9 2019 if(uid_ptr && anticollision) {
6a1f2d82 2020 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
2021 }
5f6d6c90 2022
6a1f2d82 2023 if(p_hi14a_card) {
2024 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
2025 p_hi14a_card->uidlen += uid_resp_len;
2026 }
2027 }
79a73ab2 2028
6a1f2d82 2029 if(p_hi14a_card) {
2030 p_hi14a_card->sak = sak;
2031 p_hi14a_card->ats_len = 0;
2032 }
534983d7 2033
3fe4ff4f 2034 // non iso14443a compliant tag
2035 if( (sak & 0x20) == 0) return 2;
534983d7 2036
6a1f2d82 2037 // Request for answer to select
2038 AppendCrc14443a(rats, 2);
2039 ReaderTransmit(rats, sizeof(rats), NULL);
1c611bbd 2040
6a1f2d82 2041 if (!(len = ReaderReceive(resp, resp_par))) return 0;
5191b3d1 2042
3fe4ff4f 2043
6a1f2d82 2044 if(p_hi14a_card) {
2045 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
2046 p_hi14a_card->ats_len = len;
2047 }
5f6d6c90 2048
6a1f2d82 2049 // reset the PCB block number
2050 iso14_pcb_blocknum = 0;
19a700a8 2051
2052 // set default timeout based on ATS
2053 iso14a_set_ATS_timeout(resp);
2054
6a1f2d82 2055 return 1;
7e758047 2056}
15c4dc5a 2057
7bc95e2e 2058void iso14443a_setup(uint8_t fpga_minor_mode) {
7cc204bf 2059 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
9492e0b0 2060 // Set up the synchronous serial port
2061 FpgaSetupSsc();
7bc95e2e 2062 // connect Demodulated Signal to ADC:
7e758047 2063 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
e30c654b 2064
7e758047 2065 // Signal field is on with the appropriate LED
7bc95e2e 2066 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
2067 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
2068 LED_D_ON();
2069 } else {
2070 LED_D_OFF();
2071 }
2072 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
534983d7 2073
7bc95e2e 2074 // Start the timer
2075 StartCountSspClk();
2076
2077 DemodReset();
2078 UartReset();
2079 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
46c65fed 2080 iso14a_set_timeout(10*106); // 10ms default
7e758047 2081}
15c4dc5a 2082
6a1f2d82 2083int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
2084 uint8_t parity[MAX_PARITY_SIZE];
534983d7 2085 uint8_t real_cmd[cmd_len+4];
2086 real_cmd[0] = 0x0a; //I-Block
b0127e65 2087 // put block number into the PCB
2088 real_cmd[0] |= iso14_pcb_blocknum;
534983d7 2089 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
2090 memcpy(real_cmd+2, cmd, cmd_len);
2091 AppendCrc14443a(real_cmd,cmd_len+2);
2092
9492e0b0 2093 ReaderTransmit(real_cmd, cmd_len+4, NULL);
6a1f2d82 2094 size_t len = ReaderReceive(data, parity);
2095 uint8_t *data_bytes = (uint8_t *) data;
b0127e65 2096 if (!len)
2097 return 0; //DATA LINK ERROR
2098 // if we received an I- or R(ACK)-Block with a block number equal to the
2099 // current block number, toggle the current block number
2100 else if (len >= 4 // PCB+CID+CRC = 4 bytes
2101 && ((data_bytes[0] & 0xC0) == 0 // I-Block
2102 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
2103 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
2104 {
2105 iso14_pcb_blocknum ^= 1;
2106 }
2107
534983d7 2108 return len;
2109}
2110
7e758047 2111//-----------------------------------------------------------------------------
2112// Read an ISO 14443a tag. Send out commands and store answers.
2113//
2114//-----------------------------------------------------------------------------
7bc95e2e 2115void ReaderIso14443a(UsbCommand *c)
7e758047 2116{
534983d7 2117 iso14a_command_t param = c->arg[0];
7bc95e2e 2118 uint8_t *cmd = c->d.asBytes;
04bc1c66 2119 size_t len = c->arg[1] & 0xffff;
2120 size_t lenbits = c->arg[1] >> 16;
2121 uint32_t timeout = c->arg[2];
9492e0b0 2122 uint32_t arg0 = 0;
2123 byte_t buf[USB_CMD_DATA_SIZE];
6a1f2d82 2124 uint8_t par[MAX_PARITY_SIZE];
902cb3c0 2125
5f6d6c90 2126 if(param & ISO14A_CONNECT) {
3000dc4e 2127 clear_trace();
5f6d6c90 2128 }
e691fc45 2129
3000dc4e 2130 set_tracing(TRUE);
e30c654b 2131
79a73ab2 2132 if(param & ISO14A_REQUEST_TRIGGER) {
7bc95e2e 2133 iso14a_set_trigger(TRUE);
9492e0b0 2134 }
15c4dc5a 2135
534983d7 2136 if(param & ISO14A_CONNECT) {
7bc95e2e 2137 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
5f6d6c90 2138 if(!(param & ISO14A_NO_SELECT)) {
2139 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
c188b1b9 2140 arg0 = iso14443a_select_card(NULL,card,NULL, true, 0);
5f6d6c90 2141 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
2142 }
534983d7 2143 }
e30c654b 2144
534983d7 2145 if(param & ISO14A_SET_TIMEOUT) {
04bc1c66 2146 iso14a_set_timeout(timeout);
534983d7 2147 }
e30c654b 2148
534983d7 2149 if(param & ISO14A_APDU) {
902cb3c0 2150 arg0 = iso14_apdu(cmd, len, buf);
79a73ab2 2151 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 2152 }
e30c654b 2153
534983d7 2154 if(param & ISO14A_RAW) {
2155 if(param & ISO14A_APPEND_CRC) {
0ec548dc 2156 if(param & ISO14A_TOPAZMODE) {
2157 AppendCrc14443b(cmd,len);
2158 } else {
d26849d4 2159 AppendCrc14443a(cmd,len);
0ec548dc 2160 }
534983d7 2161 len += 2;
c7324bef 2162 if (lenbits) lenbits += 16;
15c4dc5a 2163 }
0ec548dc 2164 if(lenbits>0) { // want to send a specific number of bits (e.g. short commands)
2165 if(param & ISO14A_TOPAZMODE) {
2166 int bits_to_send = lenbits;
2167 uint16_t i = 0;
2168 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
2169 bits_to_send -= 7;
2170 while (bits_to_send > 0) {
2171 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
2172 bits_to_send -= 8;
2173 }
2174 } else {
6a1f2d82 2175 GetParity(cmd, lenbits/8, par);
0ec548dc 2176 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
2177 }
2178 } else { // want to send complete bytes only
2179 if(param & ISO14A_TOPAZMODE) {
2180 uint16_t i = 0;
2181 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
2182 while (i < len) {
2183 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
2184 }
5f6d6c90 2185 } else {
0ec548dc 2186 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
2187 }
5f6d6c90 2188 }
6a1f2d82 2189 arg0 = ReaderReceive(buf, par);
9492e0b0 2190 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 2191 }
15c4dc5a 2192
79a73ab2 2193 if(param & ISO14A_REQUEST_TRIGGER) {
7bc95e2e 2194 iso14a_set_trigger(FALSE);
9492e0b0 2195 }
15c4dc5a 2196
79a73ab2 2197 if(param & ISO14A_NO_DISCONNECT) {
534983d7 2198 return;
9492e0b0 2199 }
15c4dc5a 2200
15c4dc5a 2201 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
5ee53a0e 2202 set_tracing(FALSE);
15c4dc5a 2203 LEDsoff();
15c4dc5a 2204}
b0127e65 2205
1c611bbd 2206
1c611bbd 2207// Determine the distance between two nonces.
2208// Assume that the difference is small, but we don't know which is first.
2209// Therefore try in alternating directions.
2210int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2211
c830303d 2212 uint16_t i;
2213 uint32_t nttmp1, nttmp2;
2214
1c611bbd 2215 if (nt1 == nt2) return 0;
2216
c830303d 2217 nttmp1 = nt1;
2218 nttmp2 = nt2;
1c611bbd 2219
0de8e387 2220 for (i = 1; i < 0xFFFF; i++) {
1c611bbd 2221 nttmp1 = prng_successor(nttmp1, 1);
2222 if (nttmp1 == nt2) return i;
2223 nttmp2 = prng_successor(nttmp2, 1);
2224 if (nttmp2 == nt1) return -i;
2225 }
2226
2227 return(-99999); // either nt1 or nt2 are invalid nonces
e772353f 2228}
2229
e772353f 2230
1c611bbd 2231//-----------------------------------------------------------------------------
2232// Recover several bits of the cypher stream. This implements (first stages of)
2233// the algorithm described in "The Dark Side of Security by Obscurity and
2234// Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2235// (article by Nicolas T. Courtois, 2009)
2236//-----------------------------------------------------------------------------
c830303d 2237void ReaderMifare(bool first_try)
2238{
2239 // Mifare AUTH
2240 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2241 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2242 static uint8_t mf_nr_ar3;
2243
495d7f13 2244 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE] = {0x00};
2245 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
c830303d 2246
495d7f13 2247 if (first_try)
99cf19d9 2248 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
99cf19d9 2249
f71f4deb 2250 // free eventually allocated BigBuf memory. We want all for tracing.
2251 BigBuf_free();
3000dc4e
MHS
2252 clear_trace();
2253 set_tracing(TRUE);
e772353f 2254
1c611bbd 2255 byte_t nt_diff = 0;
6a1f2d82 2256 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
1c611bbd 2257 static byte_t par_low = 0;
2258 bool led_on = TRUE;
495d7f13 2259 uint8_t uid[10] = {0};
5ebcb867 2260 uint32_t cuid = 0;
e772353f 2261
6a1f2d82 2262 uint32_t nt = 0;
2ed270a8 2263 uint32_t previous_nt = 0;
1c611bbd 2264 static uint32_t nt_attacked = 0;
3fe4ff4f 2265 byte_t par_list[8] = {0x00};
2266 byte_t ks_list[8] = {0x00};
e772353f 2267
495d7f13 2268 #define PRNG_SEQUENCE_LENGTH (1 << 16);
d26849d4 2269 static uint32_t sync_time = 0;
3bc7b13d 2270 static int32_t sync_cycles = 0;
1c611bbd 2271 int catch_up_cycles = 0;
2272 int last_catch_up = 0;
5ebcb867 2273 uint16_t elapsed_prng_sequences = 0;
1c611bbd 2274 uint16_t consecutive_resyncs = 0;
2275 int isOK = 0;
e772353f 2276
1c611bbd 2277 if (first_try) {
1c611bbd 2278 mf_nr_ar3 = 0;
7bc95e2e 2279 sync_time = GetCountSspClk() & 0xfffffff8;
0de8e387 2280 sync_cycles = PRNG_SEQUENCE_LENGTH; //65536; //0x10000 // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
1c611bbd 2281 nt_attacked = 0;
6a1f2d82 2282 par[0] = 0;
1c611bbd 2283 }
2284 else {
2285 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
1c611bbd 2286 mf_nr_ar3++;
2287 mf_nr_ar[3] = mf_nr_ar3;
6a1f2d82 2288 par[0] = par_low;
1c611bbd 2289 }
e30c654b 2290
15c4dc5a 2291 LED_A_ON();
2292 LED_B_OFF();
2293 LED_C_OFF();
c830303d 2294
2295
3bc7b13d 2296 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2297 #define MAX_SYNC_TRIES 32
2298 #define NUM_DEBUG_INFOS 8 // per strategy
2299 #define MAX_STRATEGY 3
0de8e387 2300 uint16_t unexpected_random = 0;
2301 uint16_t sync_tries = 0;
2302 int16_t debug_info_nr = -1;
3bc7b13d 2303 uint16_t strategy = 0;
2304 int32_t debug_info[MAX_STRATEGY][NUM_DEBUG_INFOS];
5ebcb867 2305 uint32_t select_time = 0;
2306 uint32_t halt_time = 0;
7bc95e2e 2307
495d7f13 2308 for(uint16_t i = 0; TRUE; ++i) {
1c611bbd 2309
c830303d 2310 LED_C_ON();
1c611bbd 2311 WDT_HIT();
e30c654b 2312
1c611bbd 2313 // Test if the action was cancelled
c830303d 2314 if(BUTTON_PRESS()) {
2315 isOK = -1;
1c611bbd 2316 break;
2317 }
2318
3bc7b13d 2319 if (strategy == 2) {
2320 // test with additional hlt command
2321 halt_time = 0;
2322 int len = mifare_sendcmd_short(NULL, false, 0x50, 0x00, receivedAnswer, receivedAnswerPar, &halt_time);
2323 if (len && MF_DBGLEVEL >= 3) {
2324 Dbprintf("Unexpected response of %d bytes to hlt command (additional debugging).", len);
2325 }
2326 }
2327
2328 if (strategy == 3) {
2329 // test with FPGA power off/on
2330 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2331 SpinDelay(200);
2332 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2333 SpinDelay(100);
5ebcb867 2334 WDT_HIT();
3bc7b13d 2335 }
2336
c188b1b9 2337 if(!iso14443a_select_card(uid, NULL, &cuid, true, 0)) {
9492e0b0 2338 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
1c611bbd 2339 continue;
2340 }
3bc7b13d 2341 select_time = GetCountSspClk();
1c611bbd 2342
3bc7b13d 2343 elapsed_prng_sequences = 1;
0de8e387 2344 if (debug_info_nr == -1) {
2345 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
2346 catch_up_cycles = 0;
1c611bbd 2347
0de8e387 2348 // if we missed the sync time already, advance to the next nonce repeat
2349 while(GetCountSspClk() > sync_time) {
3bc7b13d 2350 elapsed_prng_sequences++;
0de8e387 2351 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
5ebcb867 2352 }
e30c654b 2353
0de8e387 2354 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2355 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
5ebcb867 2356
0de8e387 2357 } else {
3bc7b13d 2358 // collect some information on tag nonces for debugging:
2359 #define DEBUG_FIXED_SYNC_CYCLES PRNG_SEQUENCE_LENGTH
2360 if (strategy == 0) {
2361 // nonce distances at fixed time after card select:
2362 sync_time = select_time + DEBUG_FIXED_SYNC_CYCLES;
2363 } else if (strategy == 1) {
2364 // nonce distances at fixed time between authentications:
2365 sync_time = sync_time + DEBUG_FIXED_SYNC_CYCLES;
2366 } else if (strategy == 2) {
2367 // nonce distances at fixed time after halt:
2368 sync_time = halt_time + DEBUG_FIXED_SYNC_CYCLES;
2369 } else {
2370 // nonce_distances at fixed time after power on
2371 sync_time = DEBUG_FIXED_SYNC_CYCLES;
2372 }
2373 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
0de8e387 2374 }
f89c7050 2375
1c611bbd 2376 // Receive the (4 Byte) "random" nonce
6a1f2d82 2377 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2378 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
1c611bbd 2379 continue;
2380 }
2381
1c611bbd 2382 previous_nt = nt;
2383 nt = bytes_to_num(receivedAnswer, 4);
2384
2385 // Transmit reader nonce with fake par
9492e0b0 2386 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
1c611bbd 2387
2388 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2389 int nt_distance = dist_nt(previous_nt, nt);
2390 if (nt_distance == 0) {
2391 nt_attacked = nt;
0de8e387 2392 } else {
c830303d 2393 if (nt_distance == -99999) { // invalid nonce received
0de8e387 2394 unexpected_random++;
3bc7b13d 2395 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
c830303d 2396 isOK = -3; // Card has an unpredictable PRNG. Give up
2397 break;
2398 } else {
2399 continue; // continue trying...
2400 }
1c611bbd 2401 }
0de8e387 2402 if (++sync_tries > MAX_SYNC_TRIES) {
3bc7b13d 2403 if (strategy > MAX_STRATEGY || MF_DBGLEVEL < 3) {
0de8e387 2404 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2405 break;
2406 } else { // continue for a while, just to collect some debug info
4a71da5a 2407 ++debug_info_nr;
2408 debug_info[strategy][debug_info_nr] = nt_distance;
3bc7b13d 2409 if (debug_info_nr == NUM_DEBUG_INFOS) {
4a71da5a 2410 ++strategy;
3bc7b13d 2411 debug_info_nr = 0;
2412 }
0de8e387 2413 continue;
2414 }
2415 }
3bc7b13d 2416 sync_cycles = (sync_cycles - nt_distance/elapsed_prng_sequences);
0de8e387 2417 if (sync_cycles <= 0) {
2418 sync_cycles += PRNG_SEQUENCE_LENGTH;
2419 }
2420 if (MF_DBGLEVEL >= 3) {
3bc7b13d 2421 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
0de8e387 2422 }
1c611bbd 2423 continue;
2424 }
2425 }
2426
2427 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2428 catch_up_cycles = -dist_nt(nt_attacked, nt);
c830303d 2429 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
1c611bbd 2430 catch_up_cycles = 0;
2431 continue;
2432 }
3bc7b13d 2433 catch_up_cycles /= elapsed_prng_sequences;
1c611bbd 2434 if (catch_up_cycles == last_catch_up) {
4a71da5a 2435 ++consecutive_resyncs;
1c611bbd 2436 }
2437 else {
2438 last_catch_up = catch_up_cycles;
2439 consecutive_resyncs = 0;
2440 }
2441 if (consecutive_resyncs < 3) {
9492e0b0 2442 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
1c611bbd 2443 }
2444 else {
2445 sync_cycles = sync_cycles + catch_up_cycles;
9492e0b0 2446 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
3bc7b13d 2447 last_catch_up = 0;
2448 catch_up_cycles = 0;
2449 consecutive_resyncs = 0;
1c611bbd 2450 }
2451 continue;
2452 }
2453
2454 consecutive_resyncs = 0;
2455
2456 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
3bc7b13d 2457 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2458 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
1c611bbd 2459
495d7f13 2460 if (nt_diff == 0)
6a1f2d82 2461 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
1c611bbd 2462
2463 led_on = !led_on;
2464 if(led_on) LED_B_ON(); else LED_B_OFF();
2465
6a1f2d82 2466 par_list[nt_diff] = SwapBits(par[0], 8);
1c611bbd 2467 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2468
2469 // Test if the information is complete
2470 if (nt_diff == 0x07) {
2471 isOK = 1;
2472 break;
2473 }
2474
2475 nt_diff = (nt_diff + 1) & 0x07;
2476 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
6a1f2d82 2477 par[0] = par_low;
1c611bbd 2478 } else {
495d7f13 2479 if (nt_diff == 0 && first_try) {
6a1f2d82 2480 par[0]++;
5ebcb867 2481 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
c830303d 2482 isOK = -2;
2483 break;
2484 }
1c611bbd 2485 } else {
6a1f2d82 2486 par[0] = ((par[0] & 0x1F) + 1) | par_low;
1c611bbd 2487 }
2488 }
2489 }
2490
1c611bbd 2491 mf_nr_ar[3] &= 0x1F;
5ebcb867 2492
2493 WDT_HIT();
2494
0de8e387 2495 if (isOK == -4) {
2496 if (MF_DBGLEVEL >= 3) {
4a71da5a 2497 for (uint16_t i = 0; i <= MAX_STRATEGY; ++i) {
2498 for(uint16_t j = 0; j < NUM_DEBUG_INFOS; ++j) {
3bc7b13d 2499 Dbprintf("collected debug info[%d][%d] = %d", i, j, debug_info[i][j]);
2500 }
0de8e387 2501 }
2502 }
2503 }
d26849d4 2504
495d7f13 2505 byte_t buf[28] = {0x00};
1c611bbd 2506 memcpy(buf + 0, uid, 4);
2507 num_to_bytes(nt, 4, buf + 4);
2508 memcpy(buf + 8, par_list, 8);
2509 memcpy(buf + 16, ks_list, 8);
2510 memcpy(buf + 24, mf_nr_ar, 4);
2511
2512 cmd_send(CMD_ACK,isOK,0,0,buf,28);
2513
99cf19d9 2514 // Thats it...
1c611bbd 2515 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2516 LEDsoff();
99cf19d9 2517
2518 set_tracing(FALSE);
20f9a2a1 2519}
1c611bbd 2520
0de8e387 2521/**
d2f487af 2522 *MIFARE 1K simulate.
2523 *
2524 *@param flags :
2525 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2526 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2527 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2528 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2529 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2530 */
2531void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
20f9a2a1 2532{
50193c1e 2533 int cardSTATE = MFEMUL_NOFIELD;
8556b852 2534 int _7BUID = 0;
9ca155ba 2535 int vHf = 0; // in mV
8f51ddb0 2536 int res;
0a39986e
M
2537 uint32_t selTimer = 0;
2538 uint32_t authTimer = 0;
6a1f2d82 2539 uint16_t len = 0;
8f51ddb0 2540 uint8_t cardWRBL = 0;
9ca155ba
M
2541 uint8_t cardAUTHSC = 0;
2542 uint8_t cardAUTHKEY = 0xff; // no authentication
c3c241f3 2543// uint32_t cardRr = 0;
9ca155ba 2544 uint32_t cuid = 0;
d2f487af 2545 //uint32_t rn_enc = 0;
51969283 2546 uint32_t ans = 0;
0014cb46
M
2547 uint32_t cardINTREG = 0;
2548 uint8_t cardINTBLOCK = 0;
9ca155ba
M
2549 struct Crypto1State mpcs = {0, 0};
2550 struct Crypto1State *pcs;
2551 pcs = &mpcs;
d2f487af 2552 uint32_t numReads = 0;//Counts numer of times reader read a block
5ebcb867 2553 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
2554 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
2555 uint8_t response[MAX_MIFARE_FRAME_SIZE] = {0x00};
2556 uint8_t response_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
9ca155ba 2557
d2f487af 2558 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2559 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2560 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
94422fa2 2561 uint8_t rSAK[] = {0x08, 0xb6, 0xdd}; // Mifare Classic
2562 //uint8_t rSAK[] = {0x09, 0x3f, 0xcc }; // Mifare Mini
d2f487af 2563 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
9ca155ba 2564
02a40596 2565 //uint8_t rAUTH_NT[] = {0x01, 0x01, 0x01, 0x01};
2566 uint8_t rAUTH_NT[] = {0x55, 0x41, 0x49, 0x92};
d2f487af 2567 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
7bc95e2e 2568
2b1f4228 2569 //Here, we collect UID1,UID2,NT,AR,NR,0,0,NT2,AR2,NR2
d2f487af 2570 // This can be used in a reader-only attack.
2571 // (it can also be retrieved via 'hf 14a list', but hey...
c3c241f3 2572 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0,0,0};
d2f487af 2573 uint8_t ar_nr_collected = 0;
0014cb46 2574
7bc95e2e 2575 // Authenticate response - nonce
51969283 2576 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
7bc95e2e 2577
d2f487af 2578 //-- Determine the UID
2579 // Can be set from emulator memory, incoming data
2580 // and can be 7 or 4 bytes long
7bc95e2e 2581 if (flags & FLAG_4B_UID_IN_DATA)
d2f487af 2582 {
2583 // 4B uid comes from data-portion of packet
2584 memcpy(rUIDBCC1,datain,4);
8556b852 2585 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
8556b852 2586
7bc95e2e 2587 } else if (flags & FLAG_7B_UID_IN_DATA) {
d2f487af 2588 // 7B uid comes from data-portion of packet
2589 memcpy(&rUIDBCC1[1],datain,3);
2590 memcpy(rUIDBCC2, datain+3, 4);
2591 _7BUID = true;
7bc95e2e 2592 } else {
d2f487af 2593 // get UID from emul memory
2594 emlGetMemBt(receivedCmd, 7, 1);
2595 _7BUID = !(receivedCmd[0] == 0x00);
2596 if (!_7BUID) { // ---------- 4BUID
2597 emlGetMemBt(rUIDBCC1, 0, 4);
2598 } else { // ---------- 7BUID
2599 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2600 emlGetMemBt(rUIDBCC2, 3, 4);
2601 }
2602 }
7bc95e2e 2603
c3c241f3 2604 // save uid.
2605 ar_nr_responses[0*5] = bytes_to_num(rUIDBCC1+1, 3);
2606 if ( _7BUID )
2607 ar_nr_responses[0*5+1] = bytes_to_num(rUIDBCC2, 4);
2608
d2f487af 2609 /*
2610 * Regardless of what method was used to set the UID, set fifth byte and modify
2611 * the ATQA for 4 or 7-byte UID
2612 */
d2f487af 2613 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
7bc95e2e 2614 if (_7BUID) {
d2f487af 2615 rATQA[0] = 0x44;
8556b852 2616 rUIDBCC1[0] = 0x88;
d26849d4 2617 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
8556b852
M
2618 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2619 }
2620
d2f487af 2621 if (MF_DBGLEVEL >= 1) {
2622 if (!_7BUID) {
b03c0f2d 2623 Dbprintf("4B UID: %02x%02x%02x%02x",
2624 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
7bc95e2e 2625 } else {
b03c0f2d 2626 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2627 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2628 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
d2f487af 2629 }
2630 }
7bc95e2e 2631
99cf19d9 2632 // We need to listen to the high-frequency, peak-detected path.
2633 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2634
2635 // free eventually allocated BigBuf memory but keep Emulator Memory
2636 BigBuf_free_keep_EM();
2637
2638 // clear trace
2639 clear_trace();
2640 set_tracing(TRUE);
2641
2642
7bc95e2e 2643 bool finished = FALSE;
2b1f4228 2644 while (!BUTTON_PRESS() && !finished && !usb_poll_validate_length()) {
9ca155ba 2645 WDT_HIT();
9ca155ba
M
2646
2647 // find reader field
9ca155ba 2648 if (cardSTATE == MFEMUL_NOFIELD) {
0c8d25eb 2649 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
9ca155ba 2650 if (vHf > MF_MINFIELDV) {
0014cb46 2651 cardSTATE_TO_IDLE();
9ca155ba
M
2652 LED_A_ON();
2653 }
2654 }
d2f487af 2655 if(cardSTATE == MFEMUL_NOFIELD) continue;
9ca155ba 2656
d2f487af 2657 //Now, get data
6a1f2d82 2658 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
d2f487af 2659 if (res == 2) { //Field is off!
2660 cardSTATE = MFEMUL_NOFIELD;
2661 LEDsoff();
2662 continue;
7bc95e2e 2663 } else if (res == 1) {
2664 break; //return value 1 means button press
2665 }
2666
d2f487af 2667 // REQ or WUP request in ANY state and WUP in HALTED state
2668 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2669 selTimer = GetTickCount();
2670 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2671 cardSTATE = MFEMUL_SELECT1;
2672
2673 // init crypto block
2674 LED_B_OFF();
2675 LED_C_OFF();
2676 crypto1_destroy(pcs);
2677 cardAUTHKEY = 0xff;
2678 continue;
0a39986e 2679 }
7bc95e2e 2680
50193c1e 2681 switch (cardSTATE) {
d2f487af 2682 case MFEMUL_NOFIELD:
2683 case MFEMUL_HALTED:
50193c1e 2684 case MFEMUL_IDLE:{
6a1f2d82 2685 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
50193c1e
M
2686 break;
2687 }
2688 case MFEMUL_SELECT1:{
9ca155ba
M
2689 // select all
2690 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
d2f487af 2691 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
9ca155ba 2692 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
0014cb46 2693 break;
9ca155ba
M
2694 }
2695
d2f487af 2696 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2697 {
2698 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2699 }
9ca155ba 2700 // select card
0a39986e
M
2701 if (len == 9 &&
2702 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
bfb6a143 2703 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
9ca155ba 2704 cuid = bytes_to_num(rUIDBCC1, 4);
8556b852
M
2705 if (!_7BUID) {
2706 cardSTATE = MFEMUL_WORK;
0014cb46
M
2707 LED_B_ON();
2708 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2709 break;
8556b852
M
2710 } else {
2711 cardSTATE = MFEMUL_SELECT2;
8556b852 2712 }
9ca155ba 2713 }
50193c1e
M
2714 break;
2715 }
d2f487af 2716 case MFEMUL_AUTH1:{
495d7f13 2717 if( len != 8) {
d2f487af 2718 cardSTATE_TO_IDLE();
6a1f2d82 2719 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2720 break;
2721 }
0c8d25eb 2722
d2f487af 2723 uint32_t ar = bytes_to_num(receivedCmd, 4);
6a1f2d82 2724 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
d2f487af 2725
2726 //Collect AR/NR
46cd801c 2727 //if(ar_nr_collected < 2 && cardAUTHSC == 2){
495d7f13 2728 if(ar_nr_collected < 2) {
2729 if(ar_nr_responses[2] != ar) {
2730 // Avoid duplicates... probably not necessary, ar should vary.
c3c241f3 2731 //ar_nr_responses[ar_nr_collected*5] = 0;
2732 //ar_nr_responses[ar_nr_collected*5+1] = 0;
2733 ar_nr_responses[ar_nr_collected*5+2] = nonce;
2734 ar_nr_responses[ar_nr_collected*5+3] = nr;
2735 ar_nr_responses[ar_nr_collected*5+4] = ar;
273b57a7 2736 ar_nr_collected++;
12d708fe 2737 }
2738 // Interactive mode flag, means we need to send ACK
2739 if(flags & FLAG_INTERACTIVE && ar_nr_collected == 2)
12d708fe 2740 finished = true;
d2f487af 2741 }
2742
2743 // --- crypto
c3c241f3 2744 //crypto1_word(pcs, ar , 1);
2745 //cardRr = nr ^ crypto1_word(pcs, 0, 0);
2746
2747 //test if auth OK
2748 //if (cardRr != prng_successor(nonce, 64)){
2749
2750 //if (MF_DBGLEVEL >= 4) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2751 // cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2752 // cardRr, prng_successor(nonce, 64));
7bc95e2e 2753 // Shouldn't we respond anything here?
d2f487af 2754 // Right now, we don't nack or anything, which causes the
2755 // reader to do a WUPA after a while. /Martin
b03c0f2d 2756 // -- which is the correct response. /piwi
c3c241f3 2757 //cardSTATE_TO_IDLE();
2758 //LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2759 //break;
2760 //}
d2f487af 2761
2762 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2763
2764 num_to_bytes(ans, 4, rAUTH_AT);
2765 // --- crypto
2766 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2767 LED_C_ON();
2768 cardSTATE = MFEMUL_WORK;
495d7f13 2769 if (MF_DBGLEVEL >= 4) {
2770 Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2771 cardAUTHSC,
2772 cardAUTHKEY == 0 ? 'A' : 'B',
2773 GetTickCount() - authTimer
2774 );
2775 }
d2f487af 2776 break;
2777 }
50193c1e 2778 case MFEMUL_SELECT2:{
7bc95e2e 2779 if (!len) {
6a1f2d82 2780 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2781 break;
2782 }
8556b852 2783 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
9ca155ba 2784 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
8556b852
M
2785 break;
2786 }
9ca155ba 2787
8556b852
M
2788 // select 2 card
2789 if (len == 9 &&
495d7f13 2790 (receivedCmd[0] == 0x95 &&
2791 receivedCmd[1] == 0x70 &&
2792 memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0) ) {
8556b852 2793 EmSendCmd(rSAK, sizeof(rSAK));
8556b852
M
2794 cuid = bytes_to_num(rUIDBCC2, 4);
2795 cardSTATE = MFEMUL_WORK;
2796 LED_B_ON();
0014cb46 2797 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
8556b852
M
2798 break;
2799 }
0014cb46
M
2800
2801 // i guess there is a command). go into the work state.
7bc95e2e 2802 if (len != 4) {
6a1f2d82 2803 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2804 break;
2805 }
0014cb46 2806 cardSTATE = MFEMUL_WORK;
d2f487af 2807 //goto lbWORK;
2808 //intentional fall-through to the next case-stmt
50193c1e 2809 }
51969283 2810
7bc95e2e 2811 case MFEMUL_WORK:{
2812 if (len == 0) {
6a1f2d82 2813 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2814 break;
2815 }
2816
d2f487af 2817 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2818
495d7f13 2819 // decrypt seqence
2820 if(encrypted_data)
51969283 2821 mf_crypto1_decrypt(pcs, receivedCmd, len);
7bc95e2e 2822
d2f487af 2823 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2824 authTimer = GetTickCount();
2825 cardAUTHSC = receivedCmd[1] / 4; // received block num
2826 cardAUTHKEY = receivedCmd[0] - 0x60;
2827 crypto1_destroy(pcs);//Added by martin
2828 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
51969283 2829
d2f487af 2830 if (!encrypted_data) { // first authentication
b03c0f2d 2831 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
51969283 2832
d2f487af 2833 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2834 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
7bc95e2e 2835 } else { // nested authentication
b03c0f2d 2836 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
7bc95e2e 2837 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
d2f487af 2838 num_to_bytes(ans, 4, rAUTH_AT);
2839 }
0c8d25eb 2840
d2f487af 2841 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2842 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2843 cardSTATE = MFEMUL_AUTH1;
2844 break;
51969283 2845 }
7bc95e2e 2846
8f51ddb0
M
2847 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2848 // BUT... ACK --> NACK
2849 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2850 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2851 break;
2852 }
2853
2854 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2855 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2856 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2857 break;
0a39986e
M
2858 }
2859
7bc95e2e 2860 if(len != 4) {
6a1f2d82 2861 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2862 break;
2863 }
d2f487af 2864
2865 if(receivedCmd[0] == 0x30 // read block
2866 || receivedCmd[0] == 0xA0 // write block
b03c0f2d 2867 || receivedCmd[0] == 0xC0 // inc
2868 || receivedCmd[0] == 0xC1 // dec
2869 || receivedCmd[0] == 0xC2 // restore
7bc95e2e 2870 || receivedCmd[0] == 0xB0) { // transfer
2871 if (receivedCmd[1] >= 16 * 4) {
d2f487af 2872 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
c3c241f3 2873 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
d2f487af 2874 break;
2875 }
2876
7bc95e2e 2877 if (receivedCmd[1] / 4 != cardAUTHSC) {
8f51ddb0 2878 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
c3c241f3 2879 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
8f51ddb0
M
2880 break;
2881 }
d2f487af 2882 }
2883 // read block
2884 if (receivedCmd[0] == 0x30) {
495d7f13 2885 if (MF_DBGLEVEL >= 4) Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2886
8f51ddb0
M
2887 emlGetMem(response, receivedCmd[1], 1);
2888 AppendCrc14443a(response, 16);
6a1f2d82 2889 mf_crypto1_encrypt(pcs, response, 18, response_par);
2890 EmSendCmdPar(response, 18, response_par);
d2f487af 2891 numReads++;
12d708fe 2892 if(exitAfterNReads > 0 && numReads >= exitAfterNReads) {
d2f487af 2893 Dbprintf("%d reads done, exiting", numReads);
2894 finished = true;
2895 }
0a39986e
M
2896 break;
2897 }
0a39986e 2898 // write block
d2f487af 2899 if (receivedCmd[0] == 0xA0) {
b03c0f2d 2900 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
8f51ddb0 2901 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
8f51ddb0
M
2902 cardSTATE = MFEMUL_WRITEBL2;
2903 cardWRBL = receivedCmd[1];
0a39986e 2904 break;
7bc95e2e 2905 }
0014cb46 2906 // increment, decrement, restore
d2f487af 2907 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
b03c0f2d 2908 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
d2f487af 2909 if (emlCheckValBl(receivedCmd[1])) {
c3c241f3 2910 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
0014cb46
M
2911 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2912 break;
2913 }
2914 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2915 if (receivedCmd[0] == 0xC1)
2916 cardSTATE = MFEMUL_INTREG_INC;
2917 if (receivedCmd[0] == 0xC0)
2918 cardSTATE = MFEMUL_INTREG_DEC;
2919 if (receivedCmd[0] == 0xC2)
2920 cardSTATE = MFEMUL_INTREG_REST;
2921 cardWRBL = receivedCmd[1];
0014cb46
M
2922 break;
2923 }
0014cb46 2924 // transfer
d2f487af 2925 if (receivedCmd[0] == 0xB0) {
b03c0f2d 2926 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
0014cb46
M
2927 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2928 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2929 else
2930 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0014cb46
M
2931 break;
2932 }
9ca155ba 2933 // halt
d2f487af 2934 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
9ca155ba 2935 LED_B_OFF();
0a39986e 2936 LED_C_OFF();
0014cb46
M
2937 cardSTATE = MFEMUL_HALTED;
2938 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
6a1f2d82 2939 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0a39986e 2940 break;
9ca155ba 2941 }
d2f487af 2942 // RATS
2943 if (receivedCmd[0] == 0xe0) {//RATS
8f51ddb0
M
2944 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2945 break;
2946 }
d2f487af 2947 // command not allowed
2948 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2949 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
51969283 2950 break;
8f51ddb0
M
2951 }
2952 case MFEMUL_WRITEBL2:{
495d7f13 2953 if (len == 18) {
8f51ddb0
M
2954 mf_crypto1_decrypt(pcs, receivedCmd, len);
2955 emlSetMem(receivedCmd, cardWRBL, 1);
2956 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2957 cardSTATE = MFEMUL_WORK;
51969283 2958 } else {
0014cb46 2959 cardSTATE_TO_IDLE();
6a1f2d82 2960 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
8f51ddb0 2961 }
8f51ddb0 2962 break;
50193c1e 2963 }
0014cb46
M
2964
2965 case MFEMUL_INTREG_INC:{
2966 mf_crypto1_decrypt(pcs, receivedCmd, len);
2967 memcpy(&ans, receivedCmd, 4);
2968 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2969 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2970 cardSTATE_TO_IDLE();
2971 break;
7bc95e2e 2972 }
6a1f2d82 2973 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2974 cardINTREG = cardINTREG + ans;
2975 cardSTATE = MFEMUL_WORK;
2976 break;
2977 }
2978 case MFEMUL_INTREG_DEC:{
2979 mf_crypto1_decrypt(pcs, receivedCmd, len);
2980 memcpy(&ans, receivedCmd, 4);
2981 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2982 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2983 cardSTATE_TO_IDLE();
2984 break;
2985 }
6a1f2d82 2986 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2987 cardINTREG = cardINTREG - ans;
2988 cardSTATE = MFEMUL_WORK;
2989 break;
2990 }
2991 case MFEMUL_INTREG_REST:{
2992 mf_crypto1_decrypt(pcs, receivedCmd, len);
2993 memcpy(&ans, receivedCmd, 4);
2994 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2995 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2996 cardSTATE_TO_IDLE();
2997 break;
2998 }
6a1f2d82 2999 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
3000 cardSTATE = MFEMUL_WORK;
3001 break;
3002 }
50193c1e 3003 }
50193c1e
M
3004 }
3005
9ca155ba
M
3006 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
3007 LEDsoff();
3008
d2f487af 3009 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
3010 {
3011 //May just aswell send the collected ar_nr in the response aswell
c3c241f3 3012 uint8_t len = ar_nr_collected*5*4;
3013 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, len, 0, &ar_nr_responses, len);
d2f487af 3014 }
d714d3ef 3015
12d708fe 3016 if(flags & FLAG_NR_AR_ATTACK && MF_DBGLEVEL >= 1 )
d2f487af 3017 {
12d708fe 3018 if(ar_nr_collected > 1 ) {
d2f487af 3019 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
c3c241f3 3020 Dbprintf("../tools/mfkey/mfkey32 %06x%08x %08x %08x %08x %08x %08x",
3021 ar_nr_responses[0], // UID1
3022 ar_nr_responses[1], // UID2
3023 ar_nr_responses[2], // NT
3024 ar_nr_responses[3], // AR1
3025 ar_nr_responses[4], // NR1
3026 ar_nr_responses[8], // AR2
3027 ar_nr_responses[9] // NR2
d2f487af 3028 );
7838f4be 3029 Dbprintf("../tools/mfkey/mfkey32v2 %06x%08x %08x %08x %08x %08x %08x %08x",
3030 ar_nr_responses[0], // UID1
3031 ar_nr_responses[1], // UID2
3032 ar_nr_responses[2], // NT1
3033 ar_nr_responses[3], // AR1
3034 ar_nr_responses[4], // NR1
3035 ar_nr_responses[7], // NT2
3036 ar_nr_responses[8], // AR2
3037 ar_nr_responses[9] // NR2
3038 );
7bc95e2e 3039 } else {
d2f487af 3040 Dbprintf("Failed to obtain two AR/NR pairs!");
12d708fe 3041 if(ar_nr_collected > 0 ) {
2b1f4228 3042 Dbprintf("Only got these: UID=%06x%08x, nonce=%08x, AR1=%08x, NR1=%08x",
c3c241f3 3043 ar_nr_responses[0], // UID1
3044 ar_nr_responses[1], // UID2
3045 ar_nr_responses[2], // NT
3046 ar_nr_responses[3], // AR1
3047 ar_nr_responses[4] // NR1
d2f487af 3048 );
3049 }
3050 }
3051 }
c3c241f3 3052 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
5ee53a0e 3053
3054 set_tracing(FALSE);
15c4dc5a 3055}
b62a5a84 3056
d2f487af 3057
b62a5a84
M
3058//-----------------------------------------------------------------------------
3059// MIFARE sniffer.
3060//
3061//-----------------------------------------------------------------------------
5cd9ec01
M
3062void RAMFUNC SniffMifare(uint8_t param) {
3063 // param:
3064 // bit 0 - trigger from first card answer
3065 // bit 1 - trigger from first reader 7-bit request
39864b0b
M
3066
3067 // C(red) A(yellow) B(green)
b62a5a84
M
3068 LEDsoff();
3069 // init trace buffer
3000dc4e
MHS
3070 clear_trace();
3071 set_tracing(TRUE);
b62a5a84 3072
b62a5a84
M
3073 // The command (reader -> tag) that we're receiving.
3074 // The length of a received command will in most cases be no more than 18 bytes.
3075 // So 32 should be enough!
495d7f13 3076 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
3077 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
b62a5a84 3078 // The response (tag -> reader) that we're receiving.
495d7f13 3079 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE] = {0x00};
3080 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE] = {0x00};
b62a5a84 3081
99cf19d9 3082 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
3083
3084 // free eventually allocated BigBuf memory
3085 BigBuf_free();
f71f4deb 3086 // allocate the DMA buffer, used to stream samples from the FPGA
3087 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
7bc95e2e 3088 uint8_t *data = dmaBuf;
3089 uint8_t previous_data = 0;
5cd9ec01
M
3090 int maxDataLen = 0;
3091 int dataLen = 0;
7bc95e2e 3092 bool ReaderIsActive = FALSE;
3093 bool TagIsActive = FALSE;
3094
b62a5a84 3095 // Set up the demodulator for tag -> reader responses.
6a1f2d82 3096 DemodInit(receivedResponse, receivedResponsePar);
b62a5a84
M
3097
3098 // Set up the demodulator for the reader -> tag commands
6a1f2d82 3099 UartInit(receivedCmd, receivedCmdPar);
b62a5a84
M
3100
3101 // Setup for the DMA.
7bc95e2e 3102 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
b62a5a84 3103
b62a5a84 3104 LED_D_OFF();
39864b0b
M
3105
3106 // init sniffer
3107 MfSniffInit();
b62a5a84 3108
b62a5a84 3109 // And now we loop, receiving samples.
7bc95e2e 3110 for(uint32_t sniffCounter = 0; TRUE; ) {
3111
5cd9ec01
M
3112 if(BUTTON_PRESS()) {
3113 DbpString("cancelled by button");
7bc95e2e 3114 break;
5cd9ec01
M
3115 }
3116
b62a5a84
M
3117 LED_A_ON();
3118 WDT_HIT();
39864b0b 3119
7bc95e2e 3120 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
3121 // check if a transaction is completed (timeout after 2000ms).
3122 // if yes, stop the DMA transfer and send what we have so far to the client
3123 if (MfSniffSend(2000)) {
3124 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
3125 sniffCounter = 0;
3126 data = dmaBuf;
3127 maxDataLen = 0;
3128 ReaderIsActive = FALSE;
3129 TagIsActive = FALSE;
3130 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
39864b0b 3131 }
39864b0b 3132 }
7bc95e2e 3133
3134 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
3135 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
495d7f13 3136
3137 if (readBufDataP <= dmaBufDataP) // we are processing the same block of data which is currently being transferred
7bc95e2e 3138 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
495d7f13 3139 else
7bc95e2e 3140 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
495d7f13 3141
5cd9ec01 3142 // test for length of buffer
7bc95e2e 3143 if(dataLen > maxDataLen) { // we are more behind than ever...
3144 maxDataLen = dataLen;
f71f4deb 3145 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
5cd9ec01 3146 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
7bc95e2e 3147 break;
b62a5a84
M
3148 }
3149 }
5cd9ec01 3150 if(dataLen < 1) continue;
b62a5a84 3151
7bc95e2e 3152 // primary buffer was stopped ( <-- we lost data!
5cd9ec01
M
3153 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
3154 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
3155 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
55acbb2a 3156 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
3157 }
3158 // secondary buffer sets as primary, secondary buffer was stopped
3159 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
3160 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
b62a5a84
M
3161 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
3162 }
5cd9ec01
M
3163
3164 LED_A_OFF();
b62a5a84 3165
7bc95e2e 3166 if (sniffCounter & 0x01) {
b62a5a84 3167
495d7f13 3168 // no need to try decoding tag data if the reader is sending
3169 if(!TagIsActive) {
7bc95e2e 3170 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
3171 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
3172 LED_C_INV();
495d7f13 3173
6a1f2d82 3174 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
b62a5a84 3175
7bc95e2e 3176 /* And ready to receive another command. */
f8ada309 3177 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 3178
3179 /* And also reset the demod code */
3180 DemodReset();
3181 }
3182 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
3183 }
3184
495d7f13 3185 // no need to try decoding tag data if the reader is sending
3186 if(!ReaderIsActive) {
7bc95e2e 3187 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
3188 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
3189 LED_C_INV();
b62a5a84 3190
6a1f2d82 3191 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
39864b0b 3192
7bc95e2e 3193 // And ready to receive another response.
3194 DemodReset();
495d7f13 3195
0ec548dc 3196 // And reset the Miller decoder including its (now outdated) input buffer
3197 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 3198 }
3199 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
3200 }
b62a5a84
M
3201 }
3202
7bc95e2e 3203 previous_data = *data;
3204 sniffCounter++;
5cd9ec01 3205 data++;
495d7f13 3206
3207 if(data == dmaBuf + DMA_BUFFER_SIZE)
5cd9ec01 3208 data = dmaBuf;
7bc95e2e 3209
b62a5a84
M
3210 } // main cycle
3211
55acbb2a 3212 FpgaDisableSscDma();
39864b0b 3213 MfSniffEnd();
b62a5a84 3214 LEDsoff();
7838f4be 3215 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
5ee53a0e 3216 set_tracing(FALSE);
3803d529 3217}
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