first import of dhwk.

[raggedstone] / dhwk / source / vergleich.vhd

-- VHDL model created from schematic vergleich.sch -- Jan 09 09:34:16 2007\r
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LIBRARY ieee;\r
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USE ieee.std_logic_1164.ALL;\r
USE ieee.numeric_std.ALL;\r
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entity VERGLEICH is\r
      Port (    IN_A : In    std_logic_vector (31 downto 0);\r
                IN_B : In    std_logic_vector (31 downto 0);\r
             GLEICH_OUT : Out   std_logic );\r
end VERGLEICH;\r
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architecture SCHEMATIC of VERGLEICH is\r
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   SIGNAL gnd : std_logic := '0';\r
   SIGNAL vcc : std_logic := '1';\r
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   signal   GLEICH : std_logic_vector (7 downto 0);\r
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   component VERG_2\r
      Port (    IN_A : In    std_logic_vector (1 downto 0);\r
                IN_B : In    std_logic_vector (1 downto 0);\r
              GLEICH : Out   std_logic );\r
   end component;\r
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   component VERG_8\r
      Port (  GLEICH : In    std_logic_vector (7 downto 0);\r
             GLEICH_OUT : Out   std_logic );\r
   end component;\r
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   component VERG_4\r
      Port (    IN_A : In    std_logic_vector (3 downto 0);\r
                IN_B : In    std_logic_vector (3 downto 0);\r
              GLEICH : Out   std_logic );\r
   end component;\r
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begin\r
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   I11 : VERG_2\r
      Port Map ( IN_A(1 downto 0)=>IN_A(3 downto 2),\r
                 IN_B(1 downto 0)=>IN_B(3 downto 2), GLEICH=>GLEICH(0) );\r
   I9 : VERG_8\r
      Port Map ( GLEICH(7 downto 0)=>GLEICH(7 downto 0),\r
                 GLEICH_OUT=>GLEICH_OUT );\r
   I8 : VERG_4\r
      Port Map ( IN_A(3 downto 0)=>IN_A(31 downto 28),\r
                 IN_B(3 downto 0)=>IN_B(31 downto 28), GLEICH=>GLEICH(7) );\r
   I7 : VERG_4\r
      Port Map ( IN_A(3 downto 0)=>IN_A(27 downto 24),\r
                 IN_B(3 downto 0)=>IN_B(27 downto 24), GLEICH=>GLEICH(6) );\r
   I6 : VERG_4\r
      Port Map ( IN_A(3 downto 0)=>IN_A(23 downto 20),\r
                 IN_B(3 downto 0)=>IN_B(23 downto 20), GLEICH=>GLEICH(5) );\r
   I5 : VERG_4\r
      Port Map ( IN_A(3 downto 0)=>IN_A(19 downto 16),\r
                 IN_B(3 downto 0)=>IN_B(19 downto 16), GLEICH=>GLEICH(4) );\r
   I4 : VERG_4\r
      Port Map ( IN_A(3 downto 0)=>IN_A(15 downto 12),\r
                 IN_B(3 downto 0)=>IN_B(15 downto 12), GLEICH=>GLEICH(3) );\r
   I3 : VERG_4\r
      Port Map ( IN_A(3 downto 0)=>IN_A(11 downto 8),\r
                 IN_B(3 downto 0)=>IN_B(11 downto 8), GLEICH=>GLEICH(2) );\r
   I2 : VERG_4\r
      Port Map ( IN_A(3 downto 0)=>IN_A(7 downto 4),\r
                 IN_B(3 downto 0)=>IN_B(7 downto 4), GLEICH=>GLEICH(1) );\r
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end SCHEMATIC;\r