first import of dhwk.
[raggedstone] / dhwk / source / vergleich.vhd
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377c0242 1-- VHDL model created from schematic vergleich.sch -- Jan 09 09:34:16 2007\r
2\r
3\r
4\r
5LIBRARY ieee;\r
6\r
7USE ieee.std_logic_1164.ALL;\r
8USE ieee.numeric_std.ALL;\r
9\r
10\r
11entity VERGLEICH is\r
12 Port ( IN_A : In std_logic_vector (31 downto 0);\r
13 IN_B : In std_logic_vector (31 downto 0);\r
14 GLEICH_OUT : Out std_logic );\r
15end VERGLEICH;\r
16\r
17architecture SCHEMATIC of VERGLEICH is\r
18\r
19 SIGNAL gnd : std_logic := '0';\r
20 SIGNAL vcc : std_logic := '1';\r
21\r
22 signal GLEICH : std_logic_vector (7 downto 0);\r
23\r
24 component VERG_2\r
25 Port ( IN_A : In std_logic_vector (1 downto 0);\r
26 IN_B : In std_logic_vector (1 downto 0);\r
27 GLEICH : Out std_logic );\r
28 end component;\r
29\r
30 component VERG_8\r
31 Port ( GLEICH : In std_logic_vector (7 downto 0);\r
32 GLEICH_OUT : Out std_logic );\r
33 end component;\r
34\r
35 component VERG_4\r
36 Port ( IN_A : In std_logic_vector (3 downto 0);\r
37 IN_B : In std_logic_vector (3 downto 0);\r
38 GLEICH : Out std_logic );\r
39 end component;\r
40\r
41begin\r
42\r
43 I11 : VERG_2\r
44 Port Map ( IN_A(1 downto 0)=>IN_A(3 downto 2),\r
45 IN_B(1 downto 0)=>IN_B(3 downto 2), GLEICH=>GLEICH(0) );\r
46 I9 : VERG_8\r
47 Port Map ( GLEICH(7 downto 0)=>GLEICH(7 downto 0),\r
48 GLEICH_OUT=>GLEICH_OUT );\r
49 I8 : VERG_4\r
50 Port Map ( IN_A(3 downto 0)=>IN_A(31 downto 28),\r
51 IN_B(3 downto 0)=>IN_B(31 downto 28), GLEICH=>GLEICH(7) );\r
52 I7 : VERG_4\r
53 Port Map ( IN_A(3 downto 0)=>IN_A(27 downto 24),\r
54 IN_B(3 downto 0)=>IN_B(27 downto 24), GLEICH=>GLEICH(6) );\r
55 I6 : VERG_4\r
56 Port Map ( IN_A(3 downto 0)=>IN_A(23 downto 20),\r
57 IN_B(3 downto 0)=>IN_B(23 downto 20), GLEICH=>GLEICH(5) );\r
58 I5 : VERG_4\r
59 Port Map ( IN_A(3 downto 0)=>IN_A(19 downto 16),\r
60 IN_B(3 downto 0)=>IN_B(19 downto 16), GLEICH=>GLEICH(4) );\r
61 I4 : VERG_4\r
62 Port Map ( IN_A(3 downto 0)=>IN_A(15 downto 12),\r
63 IN_B(3 downto 0)=>IN_B(15 downto 12), GLEICH=>GLEICH(3) );\r
64 I3 : VERG_4\r
65 Port Map ( IN_A(3 downto 0)=>IN_A(11 downto 8),\r
66 IN_B(3 downto 0)=>IN_B(11 downto 8), GLEICH=>GLEICH(2) );\r
67 I2 : VERG_4\r
68 Port Map ( IN_A(3 downto 0)=>IN_A(7 downto 4),\r
69 IN_B(3 downto 0)=>IN_B(7 downto 4), GLEICH=>GLEICH(1) );\r
70\r
71end SCHEMATIC;\r
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