first import of dhwk.
[raggedstone] / dhwk / source / vergleich.vhd
1 -- VHDL model created from schematic vergleich.sch -- Jan 09 09:34:16 2007
2
3
4
5 LIBRARY ieee;
6
7 USE ieee.std_logic_1164.ALL;
8 USE ieee.numeric_std.ALL;
9
10
11 entity VERGLEICH is
12 Port ( IN_A : In std_logic_vector (31 downto 0);
13 IN_B : In std_logic_vector (31 downto 0);
14 GLEICH_OUT : Out std_logic );
15 end VERGLEICH;
16
17 architecture SCHEMATIC of VERGLEICH is
18
19 SIGNAL gnd : std_logic := '0';
20 SIGNAL vcc : std_logic := '1';
21
22 signal GLEICH : std_logic_vector (7 downto 0);
23
24 component VERG_2
25 Port ( IN_A : In std_logic_vector (1 downto 0);
26 IN_B : In std_logic_vector (1 downto 0);
27 GLEICH : Out std_logic );
28 end component;
29
30 component VERG_8
31 Port ( GLEICH : In std_logic_vector (7 downto 0);
32 GLEICH_OUT : Out std_logic );
33 end component;
34
35 component VERG_4
36 Port ( IN_A : In std_logic_vector (3 downto 0);
37 IN_B : In std_logic_vector (3 downto 0);
38 GLEICH : Out std_logic );
39 end component;
40
41 begin
42
43 I11 : VERG_2
44 Port Map ( IN_A(1 downto 0)=>IN_A(3 downto 2),
45 IN_B(1 downto 0)=>IN_B(3 downto 2), GLEICH=>GLEICH(0) );
46 I9 : VERG_8
47 Port Map ( GLEICH(7 downto 0)=>GLEICH(7 downto 0),
48 GLEICH_OUT=>GLEICH_OUT );
49 I8 : VERG_4
50 Port Map ( IN_A(3 downto 0)=>IN_A(31 downto 28),
51 IN_B(3 downto 0)=>IN_B(31 downto 28), GLEICH=>GLEICH(7) );
52 I7 : VERG_4
53 Port Map ( IN_A(3 downto 0)=>IN_A(27 downto 24),
54 IN_B(3 downto 0)=>IN_B(27 downto 24), GLEICH=>GLEICH(6) );
55 I6 : VERG_4
56 Port Map ( IN_A(3 downto 0)=>IN_A(23 downto 20),
57 IN_B(3 downto 0)=>IN_B(23 downto 20), GLEICH=>GLEICH(5) );
58 I5 : VERG_4
59 Port Map ( IN_A(3 downto 0)=>IN_A(19 downto 16),
60 IN_B(3 downto 0)=>IN_B(19 downto 16), GLEICH=>GLEICH(4) );
61 I4 : VERG_4
62 Port Map ( IN_A(3 downto 0)=>IN_A(15 downto 12),
63 IN_B(3 downto 0)=>IN_B(15 downto 12), GLEICH=>GLEICH(3) );
64 I3 : VERG_4
65 Port Map ( IN_A(3 downto 0)=>IN_A(11 downto 8),
66 IN_B(3 downto 0)=>IN_B(11 downto 8), GLEICH=>GLEICH(2) );
67 I2 : VERG_4
68 Port Map ( IN_A(3 downto 0)=>IN_A(7 downto 4),
69 IN_B(3 downto 0)=>IN_B(7 downto 4), GLEICH=>GLEICH(1) );
70
71 end SCHEMATIC;
Impressum, Datenschutz